TWI364081B - Failure analysis vehicle for yield enhancement with self test at speed burnin capability for reliability testing - Google Patents

Description

1364081 IX. Description of the invention: [Technical field to which the invention pertains] This month is related to the manufacture of integrated circuits, and it is more clearly stated that it is a test sample used to verify a new process. [Prior Art] In the development of the new process of the 'product circuit', specific design rules will be created to define the process capability. With the development of manufacturing capabilities, the design: Ten people will begin to design new integrated circuits. The parallel results of new process development and product design make it important for the process to use these design rules to produce integrated circuits. The 4th sling core includes the following: minimum line width, minimum distance between lines, maximum number of through holes that can be stacked on top of each other, 乂 and its parameters. In general, the manufacturer will guarantee that as long as the part is . These design rules for a process can produce good components, allowing the designers to start the integrated circuit design in a few months after the process is ready. After the first production of a certain integrated circuit design, 35 Changfen had a period of failure analysis, and it was necessary to adjust the design and the process to produce a successful product. The analysis of the root cause of failure of some integrated circuits can be very time consuming, sometimes taking days or even weeks to isolate the single: single defect on the chip. The failure analysis techniques available to development engineers include the following: Mechanical 4 measurement, beam induced current (OBIC), beam induced resistance change (〇birch) 6 1^64081 picosecond imaging circuit PTr A, ^ (PICA), light induced Voltage change (LIVA), charge induced electric dust change (CIVA, ow #4a & A(dVA) various scanning electron microscopy (SEM) techniques, active and passive electric dust comparison, electron beam (E-Beam) ), as well as the well-known techniques in the art, can also use destructive testing (such as etching and grinding) to isolate and confirm the problem. In the case of more than δ, the integrated circuit Design may limit or hinder specific techniques used to pinpoint defects. For example, to use laser technology to detect a particular path, it is convenient to have a different metal in the direction of the path of interest. In addition, these various technologies may only isolate a problem from a particular part of the circuit system, but cannot be limited to a particular line or via. ^Compatible with active and passive voltage comparison techniques The E-Beam method can be used to effectively analyze boards that are not normally available with other viewing technologies. Active voltage contrast technology allows visual confirmation of the current electrical state of an integrated circuit wafer structure. The relative brightness of the structure will show whether a structure is in VDD state, grounded state, or some intermediate state. Generally, the grounder will appear dark, while the prescription and VDD will be bright. If necessary, the effect of the light and dark appearance can also be reversed. Passive voltage contrast technology works in the same way, no power supply is applied to the circuit. The substrate will be grounded, and the electrons from SEM or E-Beam The ungrounded structure will be charged' and the grounded structure will not accept the charge. During the fabrication of the wafer, each layer of the wafer can be used to view each layer using a passive voltage contrast technique. A number of layers of a wafer can be used after being 7 1364081

Dynamic voltage contrast technology to more precise anvil 烚 P 两 two in-situ inspection of the paste layer. These grounded structures are usually dark, and the 箄 技 砝 X X X 寻 接地 接地 接地 接地 接地 接地 接地 接地 接地 接地 接地 接地 接地 接地 接地 接地And use the active voltage contrast technology to print, y Λ ^ can also reverse the shading effect of the grounded structure and the ungrounded structure if necessary. During the development and verification process, the important work between tongue and tongue is to isolate defects to precise locations. For example, 诵礼可泸 > encounter j has a very high resistivity. In order to be able to correct the process, the position of the through hole must be reliably found. Failure analysis techniques that only isolate part of the electrical path are not sufficient to fine tune the process. The present invention provides a system and method for performing an integrated circuit process that overcomes the shortcomings and limitations of the prior art while allowing the failure analyst to potentially access the most individual connections and components. Quickly confirming the columns and rows of defective circuit cells accelerates the failure analysis process for more efficient process testing. In addition, the present invention can be used to test the use of DC static performance and to test dynamic performance with high speed operating frequencies. The integrated circuit designed under the constraints of the process provides a complete and fast failure analysis, enabling rapid identification of manufacturing defects and improved process. Therefore, the embodiment of the present invention may include a test for the integrated circuit, including: a plurality of unit delay cells, each of which is delayed, a sentence c including 4 cell inputs, a cell output, and a a library driver cell (sin (3) dnv) ng ceU), and an interconnect module in which the cell input is connected to the bank driver cell, and the bank driver cell is connected to the 8 1364081 group. The interconnect module is further connected to the unit cell output, and the plurality of delay cells from the unit delay cell output to the unit delay cell input are connected to each other 'to generate a string of unit delay cells; An input signal line 'which is connected to the cell input of the first cell delay cell in the string cell delay cell; and an output signal line that is connected to the cell of the string delay cell in the last cell delay cell Output. Embodiments of the present invention may further include a method for testing a process of an integrated circuit test carrier, which includes the steps of: designing the integrated φ circuit test carrier; using the process to fabricate the integrated circuit test Carrying a test signal to the input signal line of the integrated circuit test carrier', reading a generated signal from the output signal line of the integrated circuit test carrier, and generating the signal with a predetermined The reference signal is compared; and if the generated signal does not match the predetermined reference signal, the process is inferred to be defective. The integrated circuit test carrier includes a plurality of unit delay cells, wherein each of the unit delay cells includes a unit cell input, a unit cell output, a bank driver cell, and an interconnect module, wherein the cell input Will be connected to the library driver cell, the library driver cell will be further connected to the interconnect module 'the interconnect module will be further connected to the cell output, the plurality of cells delay cells from the cell Delaying cell output to the cell delay cell inputs are connected to each other in tandem to generate a string of cell delay cells; an input number line 'which is connected to the cell input of the first cell delay cell in the string cell delay cell; and an output A signal line that is connected to the cell output of the last cell delay cell in the string cell delay cell. Embodiments of the invention may further include a test 9 1364081 carrier for an integrated circuit comprising: a plurality of unit delay cells, wherein each unit delay cell comprises a plurality of unit delay cell inputs, a plurality of cell delay cells Outputting, a plurality of side-by-side library driver cells 'and a plurality of interconnect modules arranged above the overlap layer' wherein a plurality of unit delay cell inputs in the plurality of cell delay cell inputs are connected to the plurality of cells a single bank driver cell in the bank driver cell, the single bank driver cell being connected to a single interconnect module of the plurality of interconnect modules, the single interconnect module being connected to the plurality of cells Delaying single cell delay cell output in the cell output; the plurality of φ cell delay cells outputting from the plurality of cell delay cell outputs to the plurality of cell delay cell inputs in series with each other to generate a string of cell delay cells a plurality of input signal lines 'they are connected to a plurality of cell inputs of the first cell delay cell of the string cell delay cell; and a plurality of output signals Lines, which are connected to the complex cell outputs of the last cell delay cell in the string cell delay cell. Embodiments of the present invention may further include a method for testing a process of an integrated circuit test carrier, comprising the steps of: designing the integrated circuit test carrier; using the process to fabricate the integrated circuit test a plurality of test signals are applied to the plurality of input signal lines of the integrated circuit test carrier; and the plurality of generated signals are read from the plurality of output signal lines of the integrated circuit test carrier; Comparing the plurality of generated signals with a plurality of predetermined reference signals; and inferring that the plurality of generated signals do not match the plurality of predetermined reference signals. The integrated circuit test carrier includes a plurality of unit delay cells, wherein each unit delay cell includes a plurality of unit delay cell inputs, a plurality of cell delay cell outputs, a plurality of side-by-side bank driver cells, and are arranged in an overlap a plurality of interconnect modules above the layer, wherein a single unit delay cell input of the plurality of unit delay cell inputs is coupled to a single bank driver cell of the plurality of bank driver cells, the single bank driver cell Will be connected to a single interconnect module of the plurality of interconnect modules, the single-interconnect module being coupled to a single unit delay cell output of the plurality of unit delay cell rounds; A plurality of unit delay cells are outputted from the plurality of unit delay cells to the plurality of unit delay cell inputs being serially connected to each other to generate a series of unit delay cells; a plurality of input signal lines that are connected to the string The unit delays the first unit of the cell to delay the plurality of cell inputs of the cell; and the plurality of output signal lines that are connected to the last bit of the string of cells The delay cell outputs a plurality of unit cells. Embodiments of the present invention may further include a test carrier for an integrated circuit including: a plurality of integrated circuit cells, wherein the column row numbers on all metal layers of the integrated circuit are utilized to visually identify the And each of the plurality of integrated circuit cells. Embodiments of the present invention may further include a method for viewing an integrated circuit including the steps of: designing a test carrier; manufacturing the test carrier using an integrated circuit process; visually viewing the Testing the carrier; and identifying an integrated circuit cell by examining the column number on the metal layers. Wherein the test carrier includes a plurality of integrated circuit cells, wherein each of the plurality of integrated circuit cells can be visually identified by using column row numbers on all metal layers of the integrated circuit. Embodiments of the present invention may further include a test 1304081 for an integrated circuit. The eighth embodiment includes a test circuit pattern placed on one of the integrated circuit wafers; a plurality of through holes 'Used to connect the test circuit pattern to the S-spindle circuit wafer.

a layer of Mi, one of the plurality of electrical connections between the plurality of through holes on the second layer of the integrated circuit wafer; and the plurality of through holes are formed in the integrated circuit The upper portion of the test circuit pattern layer is electrically isolated so that only the second layer in the integrated circuit wafer is completed between the plurality of via holes of the test circuit pattern - electrical connection line. An embodiment of the invention may further comprise - a method for testing a process of an integrated circuit test carrier, comprising the steps of: designing the integrated circuit test carrier: using the process to fabricate the integrated circuit test a carrier; detecting the test circuit pattern layer to detect a defect by using a passive voltage contrast when generating the test circuit pattern layer; comparing a plurality of passive voltage contrast images with a plurality of preset reference passive voltage contrast images Whether the test circuit pattern is defective; and if the plurality of passive voltage contrast images do not match the plurality of predetermined reference passive voltages • Φ contrast images, the process is inferred to be defective. The integrated circuit test carrier includes a test circuit pattern placed on one of the layers of the integrated circuit wafer, and a plurality of via holes for connecting the test circuit pattern. a second layer in the daytime circle of the thickened circuit; - an electrical connection line between the plurality of through holes of the alpha layer above the first layer of the scoop of the integrated circuit wafer; and the plurality of through holes are The test circuit pattern layer of the integrated circuit wafer is electrically isolated, such that only the second layer in the integrated circuit wafer is completed between the plurality of vias of the test circuit pattern An electrical cable. 12 The embodiment of the present invention may further include I#Kongmu... A method for inspecting an integrated circuit test carrier of a process, which includes a pre-throttle technique. Β1 β includes the following steps. The integrated package is listed as a carrier; the process is applied to the von von a I w integrated circuit-circuit test carrier; the residual and 胄-type and passive voltage comparison are used to check the 忒 忒 carrier to find the defect; Determining whether the test circuit pattern is defective by comparing the 兮 contrast image with a plurality of preset test voltage and passive voltages; if the main and i motion= voltage contrast images do not match And other preset reference active t-type lightning: 'When pressing the contrast image, remove all layers except the circuit pattern layer in the integrated circuit test carrier; use passive voltage comparison to check the test circuit pattern layer; The equilateral temple test circuit pattern broken voltage pair and a plurality of preset reference test circuits are compared with the n voltage contrast image; and in the test circuit pattern, the test circuit pattern is not compared with the coin voltage image match Preset reference test circuit like a passive contrast image = place at a defect determination. The integrated circuit measuring π includes a singular test circuit (4) placed on one of the integrated circuit wafers; and a plurality of through holes for connecting the test to the integrated body. a second layer in the circuit wafer; an electrical connection line between the plurality of via holes on the white first layer of the integrated circuit wafer; and the plurality of via holes are formed in the integrated circuit The test circuit of the wafer is isolated on the round layer so that only the second layer in the integrated circuit wafer is completed between the plurality of vias of the circuit pattern. Electrical connection line. The advantages of the present invention can be used to create an integrated circuit that highlights a number of design constraints in the process. In addition, complete and unconstrained testing of a number of closely connected signals 13 1364081 lines allows engineers or technicians to quickly identify the root cause of failure—to quickly determine that specific improvements or changes must be made to the process. In addition, a process can be monitored and verified by periodically manufacturing and testing the test vehicle. [Embodiment] FIG. 1 is a schematic diagram of a step interconnection embodiment 100 between two bank cells 102 and 1-4 of an integrated circuit. There are two power busses 106 and 丨08 that provide power to the bank cells 1〇2 and 1〇4. The signal line leaving the bank (7) 2 begins above metal 2 > t 110 and is passed through via 114 to metal 112. The signal line is transmitted to the metal 4 layer 116 through the via 118. The signal line will continue to be transmitted in the form of aphid to the metal 5 layer 120, the metal 6 I 122, the metal 7 layer 124, and the $8 layer 12". The signal line will continue to be transmitted to the metal 9 layer 12攸 9 9 9 9 9 9 9 9 9 M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M蜒 荦 荦 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Similarly, the line 13 of the bus bar (10), the power bus lines 136, 138 are drawn by '140, 142' and 144 will also be arranged in the ', the father is wrong. This evening, in the Department ^ I +, injury In the example, the line originating from one of the lightning source busbars can be placed below the line of the line 6. The circuit can be used within the scope of the process parameters. ^ 4 4 Lines can be 禊# / 3 You can get close to each other here. The signal line J is bare at the top of the integrated circuit, and you can use various failure points 14 1364081 In some embodiments, a power line path can be placed below the signal line. In many cases, each layer of the integrated circuit must contain a specific minimum amount of metal to minimize The stress induced in the die of the integrated circuit. Those skilled in the art can use this design to satisfy such situations. In some cases, the additional lines in each layer may be constructed in a manner that meets the minimum metal Requirement. In other embodiments, the minimum number of metal requirements can be met with a basic step design. The bare test contacts residing on the metal 9 layer are connected to the signal lines in each metal layer. The dot 46 will be connected to the metal 2 layer 110, the contact M8 will be connected to the metal 3 layer U2, the contact 5 will be connected to the metal 4 layer 116, and the contact 152 will be connected to the metal 5 layer 120, The contact 154 will be connected to the metal 6 layer 122, and the contact 156 will be connected to the metal 7 layer 124. The contact may also appear in the lower portion of the step. The step interconnect 100 is available To highlight the process weight The product of the nature, the circuit design. All the signal line widths may be the minimum size, and the minimum spacing between the widths. In addition, there are a large number of through holes in the signal lines between the two cells 102 and 104. In the typical (four) circuit process, the 'through-hole is the item 3 of the PM project, which highlights the importance of the process. The step interconnect line 1 is the needle-type I, and the design of the test and defect isolation is sealed. Each signal line on each layer has a corresponding test contact, and the test contact 4 can be accessed from the metal 9 layer. Thus, many test techniques can be used to find and isolate a single fracture. Through hole. It is the root of judging a certain failure. 15 1364081 For this reason, we would like to find the exact through hole or line where the failure occurred. In the illusion, if a through hole in the metal 5 layer fails, the mask, die, or other processing equipment can be inspected for the particular layer. If the right 4 defect is not isolated from a particular layer and a particular via in the layer, then the process cannot be thoroughly checked, so the pace of process development will slow down. This embodiment allows process development engineers to create designs that are difficult to manufacture, while providing engineers with a number of mechanisms to evaluate failures. Using a cascade of interconnects 100 to fabricate integrated circuits, not only can process, J-samples be made in accordance with process constraints, but many of the necessary failure analysis techniques can be used for rapid evaluation to identify any defects. Those skilled in the art will be able to design a step interconnect having various metal layer numbers and various minimum path widths or various minimum spacings between signal paths while retaining the spirit and intent of the present invention. Fig. 2 is a schematic circuit diagram showing the height of the step interconnect line 2, in which stacked vias and non-stacked vias are used. The signal path 2〇2 enters the step in a certain logical cell on the metal layer 1 204. The via 2〇6 transmits the signal to the metal 2 layer 2〇7. There are three stacked vias 208, 210, and 212 directly above the via 2〇6. The signal path is also transmitted to the metal 3 layer 209 at the via 214. Similarly, three stacked through holes 218, 220, and 222 are placed directly above the through hole 214. The through hole 224 has a through hole 226 below it, and there are two through holes 228 and 23〇 at the top. The through holes 232 have through holes 234 and 236, and the through holes 232 have through holes 238. The through holes 242, 244, and 246 are located in the through hole 240. The vias 248, 16 1364081 250, 252, 254, 256, and 258 do not have any stacked vias. The step interconnect 200 can test many possible via geometries within a single-step. In the lower portion of the step (i.e., vias 248, 25A, 252, 254, 256, and 258), the individual vias between each of the integrated circuits do not have (4) stacked vias. In the upper portion of the step, the signal transmission via is included in each stacked via combination. In some embodiments, stacked vias may be present in both portions of the rung. This embodiment can be used to evaluate the process of stacking vias that are particularly problematic and whose manufacturing parameters are to be evaluated. There are many integrated circuit processes that have limitations on the number of stacked vias. This limitation may be due in part to the stress applied to the integrated circuit due to the relationship of the stacked vias. In the embodiment of the step interconnect 2 2, the maximum number of stack holes may be four. Therefore, each stacked via hole f: or arrangement can be designed. Those skilled in the art will be able to provide a plurality of cascade interconnects in the integrated circuit, wherein the maximum number of stacked vias ranges from the total number of metal layers. In some embodiments, the _ can be not designed in the step. Then, in various embodiments, the number of layers in the integrated circuit may be different. :. Hai product, for each layer of the circuit, both the die and the & cover must be manufactured, and the heart will increase the cost. Therefore, for the early process development, it is possible to construct a three- to five-layer embodiment to implement the initial opening [following; needle = final process development stage to use the process to construct the largest number of layers. example. There may be different maximum number of layers for each integrated circuit process. 17 1364081 is a schematic diagram of an embodiment 300 of a unit delay circuit shown in FIG. The data input 302 will go through a circuit to reach the data output 3〇4. The circuit includes a buffer 306, a via step 308, an inverse (n〇rm 31〇, a second step 312, a reverse (NAND) gate 314, a third step 316, and an inverter 3 1 8 And a fourth step 3丨9. The power bus including vdd 320 and VCC 322' will be connected to the inverse or gate 3丨〇 and the inverse gate 314, so that a positive signal can be transmitted via the circuit. The time it takes for the signal to pass through the circuit can be known. In an exemplary embodiment, circuit 300 can be repeatedly connected in an end-to-end manner many times, and may be repeatedly connected hundreds or thousands of times in a single integrated circuit. The unit delay circuit 300 can be used in a number of different practical embodiments. Figure 4 is a schematic diagram of an embodiment 400 of the physical arrangement of cell delay cells shown in Figure 3. The circuit includes a buffer 4. 〇6' a first step 408, a reverse gate 410, a second step 412, a reverse gate 414, a third step 416, an inverter 418, and a fourth step 419. The power bus VDD 420 and VCC 422 are shown. The arrangement is such that the power busbars are aligned with each other. Such a configuration can easily achieve the mechanical interleaving effect of the circuits for viewing the problem area. In the interlaced regions, because of the repeating pattern relationship of the embodiment 4 Therefore, it is known that a good line can be compared with a suspected bad line. Figure 5 is a schematic view of the embodiment of the stuck at fault test. The data input line 502 is transmitted through a series of Unit 18 1364081 delays cell 504 and leaves the data output line 5() 6. The unit of the delay unit 504. Some embodiments may contain tens of thousands of unit delay cells. ^Double ten when data input line 502 I is high At the time of registration, the signal will delay the cell through each cell until a defect is reached. Example ^ If a single-through hole has been opened or exhibits a high resistance value, the signal will be transmitted until the defect is reached. Since the test leads are available, the test engineer can easily and quickly determine the exact position of the through hole, including the metal layer where the through hole is located. Each unit has four steps, each step contains a number of through holes. In a typical red shoe Φ 1 I red, through hole during process development or 1 integrated body The failure rate of the circuit components may range from 1:100,000 or higher. Therefore, it may be quite practical to make the circuit have at least _, _ or 1, _, GGG strips for failure analysis. The process must be manufactured. A very large number of through holes or other difficult-to-manufacture features can be easily tested by applying a certain amount of electric dust to the data input 502 and reading the voltage at the data output 5〇6. There are many different testing techniques that can be used to determine where a # problem is. The X ladder, and the two. have two test contacts. These test contacts are available for mechanical detection. They can also be used in the following technologies: front or back φ ac laser detection, front or DC emission. Microscopy, DC current monitoring for resistive defects 〇BIC and 〇BIRCH, piCA ac emission acquisition method, DC defect isolation method, Ε·ΒΕΑΜ AC signal acquisition method, e_beam pattern 19 Ϊ364081 dependent DC passive electric (four) ratio method, (4) Passive electric comparison method and mechanical detection method (including AC active micro-detection method, DC voltage detection method, and DC active control detection method. The unit delay cell design shown in the round person can make people The top is directly adjacent to all the lines inside the 4 steps, completely covering various failure analysis techniques. For example, because the signal lines can be seen from the top, various laser excitation failure analysis techniques can be used to isolate any signal (4) (4) Part (4). In the debugging of other integrated circuits that are not designed for serviceability, some signal path parts may be confused due to overlapping lines. 6 is a schematic diagram of an embodiment of a shift register, wherein the soap 602 will be configured to easily perform a high speed test. The lean feed A 604 will pass through a forward-reverse device. 608. After a series of unit delay cells 602 arrive at a first-n: the first positive-reverse 610 should be abruptly. The signal is removed from the second flip-flop (four), and the second-stage unit delays the cell 6〇2 to reach a first Three positives: 612. The signal will move out of the third forward and backward 612, and pass through the first delay cell 602 to reach a fourth flip-flop 61. [All the positive and negative pianos enjoy a common clock line. By each clock cycle, the data must be transmitted through the units to delay the columns of cells 602. If one of these cells delays one of the cells, the data will not be correctly transmitted and will be destroyed. These problems will become more pronounced when the pulse speed is high. The Beben embodiment is for high-speed testing of integrated circuits, while the embodiment 5 is for static testing of the circuit system. When testing at high speed, this 20 〇北〇4〇81 Example will detect between 亓70 More subtle changes in resistance, and the process can be tested more thoroughly. In various embodiments, the delay 207 can be of different lengths from the oo-μ string early το and the number of flip-flops is also different. For example, when using a lot of unit delay cells, the 4th pass will be long and the clock speed will be slower. When the available test equipment is slower than enough to test the K-News This example can be quite useful when delaying the string. In some implementations, the number of delayed cells may range from one to hundreds or even higher. The number of columns in the shift register may be more or more. In other words, the end view can fully test the number of cell delay cells required for the sine term process and the available die space of the integrated circuit. In some embodiments, the shift register embodiment 600 and the fixed defect test κ yoke 500 may be present on a single integrated circuit. Other embodiments can be made by those skilled in the art, incorporating other test circuits while retaining the spirit and intent of the present invention. A schematic diagram of an embodiment 700 of a string of unit delay cells 710 is shown in FIG. The embodiment 700 and the unit delay cell disclosed in accordance with the description of Figs. 3 and 4 are the same as the "minimum definable unit delay cell 71" consisting of a single bank driver cell 704 and a single interconnect module 7〇8. As disclosed in the description of FIG. 5, the unit delay cells 710 may be connected together to produce various embodiments that may be composed of thousands or hundreds of thousands of unit delay cells. An input/output (10) data input signal 702 is sent to the first bank driver cell 704' and then to the interconnect module 7A8. If necessary, the library driver cell 704 (which will be connected to the interconnect module 708) can be sequenced a number of times 21 1364081 to generate a library driver string sufficient to test the process. The result of the string of unit delay cells 710 is represented by a data output signal 7〇6 at the end of the unit delay string. The 1 〇 data output ^ salt 706 can be compared with the expected result to determine whether the test vehicle has any defects. For each cell delay cell in the string, 'each bank driver cell 704 is used in conjunction with a single layer interconnect module 708. The single library driver cell 7〇4 may be one of the logical devices δ 玄玄逻辑装置 includes but is not limited to: inverter, inverse gate, inverse or gate, buffer benefit, etc. The single layer interconnect module 7〇8 may be composed of a plurality of test circuit patterns. The test circuit patterns include, but are not limited to, a metal comb, a germanium component, a terminal/through hole. String...etc. . The Haizizi/Through String can use more than one layer to create the interconnect module. 8 is a schematic diagram of an embodiment 8 of a series of unit delay cells 8 12, which is placed on a plurality of layers having corresponding plurality of library driver cells 804 to place two interconnected groups 8 1 0, which It will be configured to use all layers of the integrated circuit wafer more efficiently. The overlapping layers of the multi-layer library driver cells 804 and the interconnect modules 81A will be disclosed in more detail in the description of ® 9. The multi-layered library-driven monthly package and the overlapping layers of the interconnect modules 810 will now be discussed with respect to Figure 8 for a more complete understanding of this embodiment. Each bank driver cell can use six to seven layers of integrated circuit wafers. The interconnect modules use the layer to 曰k, or in the case of a terminal or a via string, only a few layers are required. Because the interconnect module 8 j 5 such as 5 hai appears in the library drive must be generated (4) 8〇 4 of the 6- to 7-layer wafer order, so the embodiment 800 can be placed side by side with two or more banks, so that the corresponding interconnect module 810 of 22 1364081. They can be stacked on top of each other. The bank drivers 804 are connected to different, corresponding interconnect modules 810, which may be placed on different layers of the integrated circuit wafer, so that the The entire width of the plurality of banks drives the cells 804. Compared to the integrated circuit used in a single test pattern when using a single-layer interconnect module 810. The wafer area, using multiple layers of the interconnect modules, allows the person skilled in the art to use the same integrated circuit More test patterns are placed in the wafer area. Each bank driver cell 804 has an isolated input of 8〇2, 8〇8. Embodiment 8 (VIII) • The library driver cells 804 and the interconnect modules 81A may be serially connected in a manner similar to that disclosed in the description of FIG. For the embodiment 8 of the present invention using multiple interconnect module layers 8 ι and multiple bank driver cells 804, the smallest definable unit delay cell 812 is defined to be connected to a single interconnect module 81. The single library drives the cell 804. The unit delay cell 812 of the embodiment 8() shown in the figure is composed of two separate unit delay cells 812, and due to the multiple ('layer interconnect module 8 1 〇 relationship, the two units The delay cells $12 overlap. The interconnect modules 810 are stacked on top of each other such that the single-element delay cell 8 1 2 is driven by a single bank driver 8 and contains the selected bank. The interconnecting module layer 8 of the interconnecting module 810 of the driving cell 804 is formed. The data 802, 808 is usually isolated, but if necessary, those skilled in the art can also The two are connected together. There are a plurality of data output signals 8〇6 and 814 at the end of the delayed cell 812 string, and the output signals are used to indicate the result of the unit delayed signal 81 2 strings. The data output signals 806, 814 can be compared with the expected values of the unit delay 812 strings to determine if there are any process defects. The same as the embodiment disclosed in the description of Figure 7 23 1364081, More or less unit delays in the string, 8丨2 and different types of interconnect modes 81〇, the embodiment 800 (which has a plurality of driving monthly packages 8〇4 and a plurality of interconnecting module layers 81〇) can be arranged into various configurations. The library driving cells 8〇4 may be coefficient logic devices. Among these, the logic devices include, but are not limited to, inverters, anti-gates or gates, buffers, etc. These interconnect modules 8 may be composed of several test circuit patterns. The test circuit patterns include, but are not limited to, a capacitor, a metal comb, a cymbal member, a terminal/via string, etc. The unit arrangement 900 of the embodiment of the embodiment shown in FIG. A three-dimensional diagram in which a plurality of interconnecting modules 910, 912 are placed on a plurality of layers having corresponding plurality of library driving cells y06, 908. The quaternary library driving cells 906, 908 use a plurality of integrated circuits. In embodiment 900, the bank driver cells 〇6, 〇8 are inverters, but the bank driver cells 906, 908 may also be one of logic devices, etc. Including but not limited to: reverser, reverse and anti, idle or idle, buffer = etc. Each interconnect module 9]0' 912 usually uses a single layer of the integrated circuit wafer, and may be composed of several test circuit patterns. The test circuit pattern includes, but is not limited to, capacitors, metal combs, and P-pieces/through-hole strings. The embodiment 900 is a bowl of interconnecting interconnects 9 1 0 and a metal comb interconnecting module 91 2 , each of which has a single layer of D-chip integrated circuit wafers. Use multiple drive cells

9 0 8, ancient female 癸 r, soil I ^ with modules 91 〇, 912 can be stacked on top of each other to maximize space usage, and maximize the use of a single test carrier circuit process Test level. The first bank driver cell 906 will receive a 24 1364081 barium input signal 902, which will be processed by the first bank driver cell 906. The nickname then enters the 蜿蜒 interconnect module 91〇 on the same layer as the 〇 data input signal 9〇2. Once the signal passes through the 蜿蜒 interconnecting module 910, the signal is transmitted to the 1 〇 输出 output 914 over the same layer as the 10 data input 902. The second bank driver cell 908 receives a second data entry 9〇4 on top of the same layer as the first 10-batch input 902. The second ίο data input 904 is processed by the second library driver cell 〇8. The signal then enters the metal comb interconnect module 912 on the different layers of the library driver cell 908 output and the data port 9〇4. Once the signal passes through the metal comb interconnect module 912, the signal is returned to the layers of the data wheel 904 and is output as a data output signal gig. The data output signals 914, 918 can be attached to an external ι〇 connection signal or to another unit delay cell in a string of delayed cells. The number of driver cells 906, 908 can be expanded to match the available layers of the selected interconnect module 910, 912_. Those skilled in the art can also configure the interconnect modules 910, 912 to access the entire layer or share a small portion of a layer with another interconnect module. For example, only a small portion of the multi-layered vias occupying an integrated circuit can be used in conjunction with other test circuit patterns. These other test circuit patterns occupy the remaining width of the integrated circuit layer. i υ shows a diagram of an embodiment 1000 of τ~Heart Fertilizer 1, which uses an external clock 〇 pulse 1006 as a lean input to allow for frequency testing. Example i 〇〇〇 T T uses the same logic as Figure 5

One of the embodiments created. Outside A. p clock 1 006 can be used to drive 25^04081 string unit delay cells 1010. The smallest definable unit delay cell 1〇1〇 consists of a single 4-drive cell and a single-interconnect module. The signal will delay cell 1010 through the string until it reaches the end of the string cell delay cell and is output in the form of clock output signal 1008. The clock output signal 1008 can be compared to the expected round-out signal for use in determining. Are there any process defects in the beta-type carrier? The bank driver 1 may be one of a plurality of logical devices including, but not limited to, an S-channel, an inverse, an inverse, a buffer, a buffer, and the like. The interconnect modules 1004 may be comprised of a plurality of test circuit patterns including, but not limited to, capacitors, metal combs, germanium components, terminals/via strings, and the like. Figure 11 is a diagram of an embodiment 丨100 of a series of unit delay cells η 14 that is configured to operate as a ring oscillator without the need for an external neighbor % 1 1 08. Test the higher frequency test of the vehicle. The & oscillation embodiment 1 00 will use a plurality of reverse selection cells 2 to select the external clock 丨丨 08 or to delay the unit 1114 _ input and output connections back to the original Reverse select cell J丨02 to generate a ring oscillator circuit. Single bank driver cell 4 (which will be connected to a single interconnect module 丨1〇6) is the smallest definable cell delay cell n丨4. When a unit delay string is used as a ring oscillator 1 , the external clock input is not required. 1〇8, because the reverse selection cell will send the unit delayed cell output signal as a unit. The delayed string input is substituted for the external clock input I丨〇8. The ring oscillator actuates input 11 and is a switcher that turns the ring oscillator circuit on and off. When the ring oscillator actuates the input! When 10 〇 is turned on, the signal will pass 26 1364081 through the s circuit until it is connected back to the original reverse select 丨丨〇 2 input. The state change of the conduction signal of the unit delay string causes the reverse selection cell 1102 to output a change state, and the state change is transmitted via the cell delay cell 1 Π4 _. The frequency of the ring oscillator is the cumulative delay of each of the bank driver cells 11 in the test string plus the reciprocal of the cumulative delay of each of the interconnect layer core groups 1 106. By connecting the output of one of the unit delay cells 1114 to the reverse selection cell of the cell delay rate of the other cell "02 external clock input 11〇6, the different unit delay cell can operate on the .iiio string Different frequencies. The ring oscillator configuration ιι〇〇 allows the test carrier to operate internally at ultra-high frequencies, ie two hundred MHz or even more gates, while still producing a clock output that can be split into lower frequencies |Π2. Therefore, the clock output signal 1112 can be measured using an inexpensive frequency meter. This high internal frequency allows for testing from hundreds of MHz to GHz closer to the integrated circuit product; it also allows for long-term testing because the circuit is faster, allowing for shorter time periods The same number of state changes as the embodiment dependent on the external clock.吁: It is quite advantageous to reduce the output of the 1112 frequency because the cost will increase as the frequency range is increased. 12A-D is a schematic view of an embodiment of an integrated circuit cell row number 1206 placed on all gold layers of an integrated circuit wafer, which facilitates visual recognition of integrated circuit cells. The material 1201 shown in Fig. 12A is a plan view of an embodiment in which a metal layer is provided. Fig. 12B is a side view of an embodiment in which the metal layer 丨210 is not shown in the schematic view of the embodiment when the metal layer is not blurred. Fig. 12d is a plan view showing a schematic view of a 杳n of the metal layer 122 when the metal layer 122 is blurred. The row number 1206 is located in the metal layers 丨21 〇, 丨214, 丨2 to identify the columns and rows of the integrated circuit cells. The top views 12〇1, 12〇2 of this embodiment are the best schematic views of the column row numbers. When the metal ^ is removed, the row number is not visible to 1208, 1222 until the other layer is exposed. When the metal layer is removed but the oxide layer between the metal layers is all visible, the layer removal process poses a problem. The side view (10), the shaving system shows how the oxidation (4) 1212, 1218 blurs the best schematic of the row number 1206 of the dragon circuit cell. 13A-D are schematic views of a conventional example 1300 of integrated circuit cell row numbers 13〇8, i3i2 placed on all metal layers 1316, 1 320, 1328 of an integrated circuit wafer, The integrated circuit wafer has a plurality of through holes or terminals 〇3〇6, 丨3丨〇, 1 3 14 , 1 3Μ built in the row number to allow easy identification of the integrated circuit cells even if the metal layer 1316丨32〇, 1328 are not barely exposed. Fig. 13A is a plan view showing an embodiment of the metal layer of the schematic ι3〇ι. Figure 13 is a plan view of the embodiment of the embodiment in which the metal layer is blurred. The schematic view 13〇3 shown in Fig. 13C is a side view of an embodiment in which the metal layer 13 16 is attached. Figure 3 is a plan view showing an embodiment of the case where the 304-based metal layer 1328 is blurred. The same as the embodiment disclosed in the description of Fig. 12, the lamp number 1 308 representing the integrated circuit cell is placed over all of the metal layers 1316, 1320, 1328 of the integrated circuit wafer. The vias and/or terminals 13〇6, 131〇, 13M, 1 324 can be placed in the integrated circuit array row numbers 13〇8, ι3ΐ2 and extended to other layers in the integrated circuit wafer. When located above the metal layer 28 1364081 1316 ' 1320 ' 1 328, the integrated circuit array row numbers 1308, 1312 and the vias and/or terminals 1306, 1310, 1314, 1324 are visible 1312' 1330. The vias and/or terminals 1306, 1310, 1314, 13 24 continue through a plurality of layers, so that the vias and/or terminals πιο and 丨 are still visible when the metal layer 1316 is removed, 1312, 1 3 30 ' 324. Top view 1 30 1 , 1 302 is the best schematic diagram of how the integrated circuit row numbers 丨3〇8, 1 3 1 2 appear when viewing; and the side view 丨3〇3, 1 3〇4 is even Only the oxide layers 13 1 8 and 1326 are shown to be able to see the best schematic of the vias and/or terminals 1306, 1310, 1314, 1324. The reason why this embodiment is valuable is that in order to achieve a correct failure analysis, it may be necessary to perform the inspection operation when the oxide layers 1318, 1326 are exposed. Those skilled in the art will appreciate that the vias and/or terminals 13 〇 6, 131 〇, 1314, 1324 should originate from the integrated circuit layer for proper failure analysis purposes. A top view of an embodiment of the isolated signal fingers 141, 丨 42 所示 shown in Figures 14A-C allows for voltage contrast and E_Beam viewing techniques to be performed to easily locate defects 1416 in the integrated circuit. As shown in Fig. A: Intent 1451 shows an embodiment in which all metal layers and via holes are shown. Fig. 1 145 is an embodiment in which only the integrated circuit layer of the test circuit pattern is not shown. The dry sound m,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Circuit wafer 1 mail + day yen round - the upper layer is isolated from the test month and the circuit pattern part of the benefits. A Feng Zhao & cow's metal comb 1412 will be attached to the signal line metal layer 14 using the through hole M06 2. The other half of the gold 29-genre comb (4) 2 is attached to the ground line metal layer 1404 using a plurality of vias 1408. If a defect 1416 occurs in the integrated circuit process, the integrated circuit layer 1422 can be removed to reveal the Test the metal layer of the circuit for inspection purposes. Because the metal comb circuit may be composed of thousands of comb fingers, using a typical inspection technique to find a single defect can be quite lengthy. Pw is off a single layer. Test the complex circuit pattern In part, a defective integrated circuit can be removed from the electrical connection metal layer to expose the isolated test circuit pattern to help locate the defect. Each individual comb in the signal portion of the metal comb circuit The fingers 1410, 1414, 1420 are electrically isolated from the test circuit pattern metal layer. The signal fingers 1410 of the metal comb are electrically connected to the signal line metal layer 1402 by a plurality of vias 14A. The via connection between the metal layers can provide electrical continuity, and the electrical signal can be transmitted by the metal comb 141 2 . When the defect 1416 ^ is detected, the integrated circuit layer can be exposed to expose the test circuit round metal. The layer 22 and the test circuit pattern metal layer 1422 are in the form of isolated signals. 卩1 41 4, 1 420. Using the isolated signal fingers 1 44, 142. When using voltage In contrast to the (4) coffee failure analysis technique, only the grounding wire of the metal comb 1418 and the individual signal fingers 1414 containing the defect will be grounded (ie, dark). The signal finger isolation can be tested on the metal comb. Among the circuit patterns 1442 Quickly and easily locate the defect 1416»When the complex layer circuit layer is removed but the oxide layer blurs the metal comb layer 1430, the voltage contrast and E_Beam failure analysis techniques can be used to view the vias. Decide which signal finger Μ% is grounded (ie, which is dark). The grounded via 1 428 will also exhibit 30 1364081 dark color, matching the grounded signal fingers 1426. When using voltage comparison In the case of the E-Beam failure analysis technique, these ungrounded signals are fingered. P 1424 will appear bright. Even if the metal comb layer is not directly exposed! 430, the through hole through the oxide layer in the figure, μ %, 1428, signal finger isolation also allows the failure analyst to quickly and easily locate the defect 1416. A side view of the isolated signal fingers 1504, 1512 embodiment 1500 shown in Figure 14A-ct, which allows the implementation of voltage versus ratio and E-Beam viewing techniques to easily implement the product. Find the defect 1 5 14 in the body circuit. A side view of Example 15A shows a metal comb test integrated circuit pattern over a metal layer that is electrically connected to a signal line metal layer 1506 using a plurality of vias 15〇2. The ground line metal layer and the metal comb ground line are not shown, as the side view of the embodiment 15 is not required for the ground line metal layer and the metal comb ground line. The signal fingers 1504, 1512 of the metal comb are projections that traverse the page, and the ground fingers 1510 of the metal comb are projections that enter the page. The signal line metal layer 1506 in the figure illustrates the final electrical connection of the signal fingers 1 5 04, 1 5 1 2 of the metal comb. The signal fingers 1504, 1512 are electrically isolated from the metal comb layer. The via 1 502 connects the metal comb isolation signal fingers 1 5〇4, 5] 2 to the signal line metal layer 1506. The metal comb circuit can be isolated by providing the vias 15〇2 with enlarged contacts for attachment to the isolated signal fingers 1 5 04, 1 5 1 2 on the metal comb layer. Each of the signal fingers 1504, 1512. The line 1508 in the figure illustrates where the signal line 31 1364081 metal 1506 is removed to view the vias 1502. The electrical connections of the metal comb signal fingers are established by the signal line metal layer 1 506. The signal line metal layer 15 5 is connected to the metal comb layer by a plurality of through holes 丨 5 〇 2 Each signal finger 1504, 1 5 12 . If there is a defect 514 on the single signal finger 1512 of the s-ceramic comb circuit and the "wire metal layer 1500 is at the correct position, then when the voltage contrast technique is used, the entire signal metal comb structure will be presented. Ground state (ie, dark color). Once the signal line metal layer 1506 is removed 1508, the appropriate holes 15〇2 connected to each of the signal fingers 15〇4, 1512 allow for passive voltage comparison or The E Beam failure analysis technique reveals that only the through-holes of the signal fingers 丨5丨2 that are affected by the defect 1 5 14 are grounded (ie, dark-colored). All other isolated signal fingers and associated Via 1 504 will be in a normal state (ie, bright state), so the defect 1 $ 快速 can be quickly found in the large interconnect module test circuit. The part that isolates the interconnect circuit pattern is not limited to Metal comb structure. The stiff pattern and other test patterns can also be isolated into a plurality of smaller sections, and the electrical connection of the signals is completed by using the vias between the plurality of layers on the other removable layer (4) Isolating other patterns will have the same improved defect finding effect as seen in the metal comb test circuit pattern. The embodiments disclosed herein are suitable for developing and verifying integrated circuit processes. In typical use, Lee &# uses the target design parameters of the new I辁 to set one of the embodiments. These sets of clocks can be used to include the minimum line width and the maximum number of stacked vias. The new process is an embodiment to form an integrated circuit. The U-call of the integrated circuit can be quickly separated by 32 1364081 at the exact through hole or line where the problem occurs. The specific process, reticle or other necessary manufacturing problem is reversed = the problem. When the process can produce the __ or multiple embodiments of the present invention without any defects, then the process It is confirmed and mass production can begin. The embodiments disclosed herein may be further adapted to verify existing processes. For the established process, we may wish to periodically manufacture this One of the various embodiments' is used to evaluate any of the processes and to verify the correct mode of operation. The present invention has been presented in the foregoing for the purpose of illustration and description, but the purpose is not to exhaust The invention may be limited to the disclosed stereotypes, and other modifications and variations of the present invention are possible in accordance with the above teachings. The principles selected and described herein are for the principles of the present invention and its practical application. The best explanation is to enable those skilled in the art to best practice in various embodiments and various modifications: the present invention is adapted to the particular mode of use contemplated. Included Patent Application: Other Alternative Embodiments [Further Description of the Drawings] Figure 1 is a schematic diagram of two stages of interconnection in an integrated circuit. The ladder between the early and the second is not represented by the representative circuit of the height of the step interconnect. You do not think about the use of stacked vias and non-stacked vias. ' 33 1364081 FIG. 3 is a schematic diagram of an embodiment of a unit delay circuit. Figure 4 is a schematic illustration of an embodiment of the physical arrangement of cell delay cells shown in Figure 3t. The embodiment of the stuck at fault test shown in Figure 5 is intended. Figure 6 is a schematic diagram of an embodiment of a shift register in which the unit delay cells are configured to easily perform high speed testing. Figure 7 is a schematic diagram of an embodiment of a string of unit delayed cells. Figure 8 is a schematic diagram of an embodiment of a string of unit delay cells in which a plurality of interconnect modules are placed over a plurality of layers having corresponding plurality of bank drive cells, which are configured to be more efficient Use all layers of the integrated circuit wafer. Figure 3 is a three dimensional schematic diagram of the physical arrangement of cell delay cells of the embodiment shown in Figure 8, wherein a plurality of interconnect modules are placed over a plurality of layers having corresponding plurality of bank drive cells. Figure 1 is a schematic diagram of an embodiment of a series of unit delay cells that allows an external clock to be used as a data input to allow for frequency testing. A schematic diagram of an embodiment of a string of unit delay cells, shown in Figure 11, will be configured to operate in a ring oscillator mode without the need for an external clock to perform a higher frequency test of the test carrier. 1A-D are schematic views of an embodiment of an integrated circuit cell row number placed on all metal layers of an integrated circuit wafer, which allows for easy visual recognition of integrated circuit cells. 13A-D is a schematic view showing an embodiment of an integrated circuit cell row number placed on a layer of all metal 34 1364081 of an integrated circuit wafer, which is provided with a plurality of links in the q彳_ number Holes or terminals to allow easy identification of the integrated cells, even if a metal layer is not exposed. A top view of the isolated signal finger embodiment shown in Figures 14A-c allows voltage contrast and E-Beam viewing techniques to be performed to easily identify defects in the sinusoidal circuit. Figure 15 is a side view of the isolated signal finger embodiment shown in Figures 14A-C, which allows for voltage contrast and E_Beam view φ techniques to be easily found in the integrated circuit. Defects. [Main component symbol description] 100 step interconnect 102 bank 104 cell 106 power bus 108 power bus 110 metal 2 layer 112 metal 3 layer 114 through hole 116 metal 4 layer 118 through hole 120 metal 5 layer 122 metal 6 Layer 124 metal 7 layer 35 1364081

126 Metal 8 layer 128 Metal 9 layer 130 Metal 2 layer 132 Signal line 134 Power bus line 136 Power bus line 138 Power bus line 140 Power bus line 142 Power bus line 144 Power bus line 146 Contact 148 Touch Point 150 contact 152 contact 154 contact 156 contact 200 step interconnect 202 signal path 204 metal 1 layer 206 through hole 207 metal 2 layer 208 stack via 209 metal 3 layer 210 stack through hole 36 1364081

212 Stacking Through Hole 214 Through Hole 216 Through Hole 218 Stacking Through Hole 220 Stacking Through Hole 222 Stacking Through Hole 224 Through Hole 226 Through Hole 228 Through Hole 230 Through Hole 232 Through Hole 234 Through Hole 236 Through Hole 238 Through Hole 240 Through Hole 242 Through Hole 244 Through Hole 246 Through Hole 248 Through Hole 250 Through Hole 252 Through Hole 254 Through Hole 256 Through Hole 258 Through Hole 37 1364081

300 unit delay circuit 302 data input 304 data ¥ m out 306 buffer 308 step 310 reverse or gate 312 step 314 reverse gate 316 step 318 reverser 319 step 320 power bus VDD 322 power bus VCC 400 unit delay cell Physical arrangement 406 Buffer 408 Step 410 Reverse or Gate 412 Step 414 Reverse Gate 416 Step 418 Inverter 419 Step 420 Power Bus VDD 422 Power Bus VCC 38 1364081 500 Fix Defect Test Logic Configuration 502 Data Input Line 504 Unit Delay cell 506 data output line 600 shift register 602 unit delay cell 604 data input 606 data output 608 flip-flop 610 flip-flop 612 flip-flop 614 flip-flop 700 unit delay cell string 702 input / output (10) Data input signal 704 library driver cell 706 input/output (10) data output signal 708 interconnection module 710 unit delay cell 800 unit delay cell string 802 10 data input 804 library driver cell 806 10 data output 808 10 data input 810 interconnect module 39 1364081

812 unit delay cell 814 10 data output 900 unit delay cell entity arrangement 902 10 data input 904 10 data input 906 library driver cell 908 library driver cell 910 interconnection module 912 interconnection module 914 IO data output 918 10 poor material output 1000 Unit Delay Cell String 1002 Library Driver Cell 1004 Interconnect Module 1006 External Clock 1008 Clock Output 1010 Unit Delay Cell 1100 Cell Delay Cell String 1102 Reverse Select Cell 1 104 Library Driver Cell 1106 Interconnect Module 1108 External Clock 1110 unit delay cell 1112 clock output 40 1364081

1114 Unit Delay Cell 1206 Column Number 1210 Metal Layer 1212 Oxide Layer 1214 Metal Layer 1218 Oxide Layer 1220 Metal Layer 1306 Through Hole or Terminal 1308 Column Number 1310 Through Hole or Terminal 1312 Column Number 1314 Through Hole or Terminal 1316 Metal Layer 1318 oxide layer 1320 metal layer 1324 via or terminal 1326 oxide layer 1328 metal layer 1402 signal line metal layer 1404 ground line metal layer 1406 via 1408 via 1410 isolated signal finger 1412 metal comb 41 1364081

1414 1416 1418 1420 1422 1424 1426 1428 1430 1502 1504 1506 1510 1512 1514 Isolated signal finger defect metal comb isolated signal finger test circuit pattern metal layer ungrounded signal finger grounded signal finger Partially grounded through hole metal comb layer through hole is isolated signal finger signal line metal layer grounding layer isolated signal finger defect

42

Claims (1)

1364081 X. Patent application scope: 1. A test vehicle for an integrated circuit, comprising: a t of each of the unit delay cells including one a plurality of unit delay cells, wherein the cell input, a cell output, an input signal line is coupled to the cell input of the first cell delay cell in the string cell delay cell; and an output semaphore line Connected to the cell output of the last cell delay cell in the string cell delay cell. 2. The test vehicle of claim </ RTI> wherein the library driver cell comprises at least one of the group consisting of: a gate, a reverse gate, a buffer, and an inverter . 3. The test carrier of claim </ RTI> wherein the interconnecting module comprises at least one of the group consisting of: a capacitor, a metal comb, a cymbal component, a terminal string, and a pass Hole string. 4. The test carrier of claim 1, wherein the input signal line is coupled to an external clock signal, and the output signal line writes a clock output signal that is logically associated with the external clock. . 5. The test vehicle of claim 4, further comprising: a reverse selection cell, wherein the reverse selection cell has a ring oscillator for 43 input 'selection cell data round, 纟一选# The cell data is rotated: the selection of the cytoplasmic output is connected to the input signal line; Θ and so on, the two selected cells are input to the pulse signal; ^ 4 when the two selected cells are input into the 纟In addition, the delayed string output signal line; the state of the Xuanyuanyuan&quot;Xuanyizheng tween input determines whether the two selected cell inputs are reversed and transmitted to the selected cell data output; The output signal line of the 7C delay cell is transmitted to the clock output signal. 6. The test vehicle of claim 5, wherein the clock pulse and the step-by-step are connected to the two selected cell data input persons as the external clock signal β 7. A method for testing a process of an integrated circuit test carrier, comprising the steps of: - designing the integrated circuit test carrier, the integrated circuit test carrier comprising: a plurality of unit delay cells, each of which The unit delay cells each include a unit cell input, a unit cell wheel, a library driver cell, and an interconnection module, wherein the cell input is connected to the bank driver cell, and the library driver cell is connected; To the interconnect module, the interconnect module is further connected to the single cell output, and the plurality of cell delay cells are delayed from the cell output to the cell delaying the cells to be connected to each other' Generating-serial unit delay ^-input signal line connected to the cell input of the first 7C delay cell in the first cell delay cell; and an output signal line connected to the string cell delay cell by 44 1364081 Last unit a cell output of the late cell; using the process to manufacture the integrated circuit test carrier; applying a test 4 signal to the input signal line of the integrated circuit test carrier; and testing the output signal of the carrier from the integrated circuit The line signal; comparing the generated signal with a predetermined reference signal; and if the generated signal does not match the preset reference signal, the circuit is inferred to be defective. 8. The method of claim 7, wherein the integrated circuit measuring device further comprises: - the library driving cells comprising at least one of the following groups: anti-gate, anti- Or gate, buffer' and inverter. η 9 二 9 凊 凊 凊 凊 凊 凊 凊 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ The mold includes at least two of the group consisting of the following, a terminal string, and a through-hole string. The method of applying the seventh paragraph of the patent scope in May, the first one of the trial vehicles further includes: /, medium &quot;Haizhong body circuit test that the wheel signal line is connected to - the outer signal line is written to the logic" 5唬'And the round number. The clock wheel associated with the material clock is associated with the letter 1 1 · The method of claim 10 of the scope of the patent test vehicle further includes: , , , /, the integrated circuit 45 1364081 - a reverse selection cell, wherein the reverse selection cell has a ring vibrator input, two selection cell data inputs, and a selection cell data rotation. The selected cell data output is coupled to the input signal line; One of the two selected cell data inputs is connected to the external Zou clock signal; the two selected cell data inputs are the other of which are connected to the single_delayed string output signal line; the ring oscillator The state of the actuating input determines which of the two selected cell data inputs is inverted and is transmitted to the selected cell data output; and the output signal line of the string of cell delay cells is transmitted to the outside to become the clock input 12. The method of claim 5, wherein the integrated circuit measuring the S-type carrier further comprises: the clock output signal further connected to the one of the two selected cell data inputs as the External clock signal. 1 3. A test vehicle for an integrated circuit, comprising: a module, the single a plurality of single-/' unit delay library drivers, and a group arranged above the overlap layer, wherein the single inputs of the plurality of unit delay cell inputs are connected to the plurality of library drivers a single unit in a cell that delays cell output; a single bank driver cell is coupled to the plurality of interconnect modules in the plurality of interconnect modules, the single interconnect module being coupled to the plurality of cells 46 1364081 A plurality of unit delay cells are output from the plurality of unit delay cells. a plurality of unit delay cell inputs are connected to each other in series to generate a string of unit delay cells; a plurality of input signal lines connected to a plurality of unit cell inputs of the first unit delay cell of the string unit delay cell; and a plurality of Strip output signal lines that are connected to a plurality of unit cell outputs of the last unit delay cell in the string unit delay cell. 14. The test vehicle of claim 13, wherein the library φ drive cells comprise at least one of the group consisting of: a sluice gate, a reverse gate, a buffer, and a reverse Device. 15. The test carrier of claim 13, wherein the interconnecting modules comprise at least one of the group consisting of: a capacitor, a metal comb, a tantalum component, a terminal string, and a pass. Hole string. 16. A method for testing a process for testing an integrated circuit test carrier, comprising the steps of: a 6 hp integrated circuit test carrier, the integrated circuit test carrier comprising: Φ a plurality of unit delay cells Each of the unit delay cells includes a plurality of unit delay cell inputs, a plurality of cell delay cell outputs, a plurality of side-by-side bank driver cells, and a plurality of interconnect modules arranged on the stack. A single unit delay cell input in a plurality of unit delay cell inputs is coupled to a single bank driver cell of the plurality of bank driver cells, the single bank driver cell being coupled to a single one of the plurality of interconnect modules a module, an interconnect module is coupled to the single 711 delayed cell output of the plurality of cell delay cell outputs; the plurality of cell delay cells from the plurality of 47 I364 〇 8i • cells delayed cell Outputting to the plurality of unit delay cell inputs are connected to each other in series, thereby generating a string of unit delay cells; a plurality of input signal lines, • they are connected to the first of the string unit delay cells a plurality of single 7L cell inputs of the meta-delay; and a plurality of output signal lines connected to the plurality of cell outputs of the delayed cell delay cell of the string unit; using the process to fabricate the integrated circuit test load Applying a plurality of test signals to the plurality of input signal lines of the integrated circuit test carrier; reading a plurality of the plurality of output signal lines of the reference k k5 measuring device Generating a signal; comparing 4 π complex generation signals with a plurality of preset reference signals to 1 to the right Qiansi plural to generate a test signal, it is inferred that the process is defective. 17. If the patent application scope is 6-1 test load The method further includes: the integrated circuit of the bank, the bank driver cells comprising a group consisting of: a reverse, a closed, a closed or a buffer, and an inverter. 18. The test vehicle of claim 6 is further comprising: wherein the interconnecting circuit comprises one of the groups consisting of τ faces. Capacitors, metal combs, bowls 蜒Parts, terminal strings, =. 】9.- Test strip for the integrated circuit, the whole number of integrated circuit cells, including the serial number of all metal layers 48 of the edge integrated circuit are visually identified. Each of the plurality of integrated circuit cells has an integrated circuit cell. 20. The test of claim 19, further comprising: ', ^ a plurality of through holes placed in the row number, such that when viewed from the top end of the integrated circuit, The vias produce the column row number. 21 'A test as claimed in item 19 of the patent application, which further includes: 'When a plurality of terminals placed in the array line number are caused to be viewed from the top end portion of the integrated body road' The column number is generated by the terminal. 22_ - A method for viewing an integrated circuit, comprising the steps of: /, beta measuring a test carrier, the test carrier comprising a plurality of integrated circuit cells, wherein the integrated circuit is used on all metal layers The row number of the array is visually identified for each of the plurality of integrated circuit cells; the test device is fabricated using an integrated circuit process; the test carrier is visually viewed; An integrated circuit cell is identified by examining the column number on the metal layers. 23. The method of claim 22, further comprising the steps of: further designing the integrated circuit test carrier, the integrated circuit test carrier further comprising a plurality of passes disposed within the column number Holes, such that when viewed from the top end portion of the integrated circuit, the vias create the column number of 13 1364081; remove a metal layer leaving only the intermediate oxide layer; and by reviewing such The vias identify the column row numbers of an integrated circuit to identify an integrated circuit cell. 24. The method of claim 22, further comprising the steps of: further designing the integrated circuit test carrier, the integrated circuit test carrier 2 further comprising a plurality of terminals placed within the column row number When the top portion of the integrated circuit is viewed, the terminals generate the column row number; a metal layer is removed leaving only the intermediate oxide layer; and the terminals are identified by examining the terminals The column number of an integrated circuit is used to identify an integrated circuit cell. 25. A test carrier for an integrated circuit, comprising: a test circuit pattern placed on one of an integrated circuit wafer; • a plurality of vias for patterning the test circuit Connecting to the second layer in the integrated circuit wafer; an electrical connection line between the plurality of via holes on the second layer of the integrated circuit wafer; and the plurality of through holes in the integrated body The test circuit pattern layer of the circuit wafer is electrically isolated, such that only the second layer in the integrated circuit wafer is completed between the plurality of vias of the 5 s circuit pattern An electrical cable. 50 1364081 26. The 25th circuit pattern as claimed in the patent application includes the test vehicle of the following, wherein at least one of the group of the test μ into the Kuncheng group, the φ, the metal comb,蜿蜒 Parts, 'Ύ 耆. Electricity 27. - Kind for testing - integrated 乂 and through-hole strings. The method comprises the following steps: &quot;testing the manufacturing process of the carrier, designing the integrated circuit test carrier, and the integrated circuit test carrier comprises: an inspection circuit diagram on one of the layers of the An. The second layer; a second = map, to the electrical connection between the plurality of vias on the second layer of the integrated circuit, the test circuit of the bulk circuit wafer is electrically isolated, so that only And forming an electrical connection line between the plurality of through holes of the test circuit pattern on the second layer of the integrated circuit wafer; using the process to manufacture the integrated circuit test carrier Passing the passive voltage comparison to check the s-type circuit pattern layer to find the defect when generating the test circuit diagram to draw the mm, 1 &lt; ^ ^ eucalyptus layer; the plurality of passive voltage contrast images and a plurality of presets Referring to the passive voltage comparison image for comparison to determine whether the test circuit pattern is defective; and if the plurality of passive voltage contrast images do not match the plurality of predetermined reference passive voltage pairs It is inferred that the process is defective than the image. 28. The method of claim 27, wherein the integrated circuit &gt; the test carrier further comprises: 51 1364081 The test circuit pattern comprises at least one of the group consisting of: capacitor 'metal Comb, 蜿蜒 component" string. 7A and through hole 29. - A method for testing the integrated circuit test carrier of the process, comprising the following steps: designing the integrated circuit test carrier 'the integrated body The circuit test carrier includes: a test circuit board placed on an integrated circuit wafer, a test circuit board on the An T layer, and a plurality of through holes for connecting the test circuit port to the integrated circuit a second layer in the wafer; an electrical connection line between the plurality of via holes of the second two temples of the integrated circuit wafer; and the test circuit pattern of the plurality of via holes in the integrated circuit wafer丄 丄 丄 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 层 ( 层 ( ( 层 ( 层 ( ( 层 层 ( ( ( ( ( ( ( ( ( ( ( Using the process to manufacture the integrated circuit test load Applying the power supply and not applying power to the active ohmic, passive voltage comparison to check the test carrier to identify defects; to compare the active and passive voltage contrast images with a plurality of preset...dynamic and passive voltages Comparing the images for comparison to determine whether the test circuit pattern is defective; if the active and passive voltages do not match the preset reference active and passive voltage comparisons, Removing all layers of the test circuit pattern layer in the integrated circuit test carrier; checking the test circuit pattern I by passive voltage comparison; and slanting the test circuit pattern to the passive screen A plurality of pre-52 1364081 reference test circuit passive voltage comparison images are compared; and: the test circuit pattern in the test circuit pattern passive voltage contrast image does not match the information, the image, the reference, etc. Test the circuit where the passive voltage contrasts the shirt image to determine a defect. 3〇·If you apply for a patent The 29th test carrier further includes: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 1 What is the string, and the through hole XI, the pattern: as the next page 53