TWI364058B - Cabon allotropy of circuit structure and fabrication method thereof - Google Patents

Description

MEGA 06-020TW-P05014 • Nine: Inventions. Ming:·············································································· It relates to the structure and process of a semiconductor circuit component in which a metal line is replaced by a carbon nanotube. [Prior Art] The carbon nanotube is a tube of carbon diameter composed of nanometers. The nanotube was first discovered by Iijima in the product of arc discharge in 1991. See Natiire for details. , V〇1.354, P.56, carbon nanotubes have the characteristics of light weight, high strength, high heat, flexibility, high surface area, large surface curvature, high thermal conductivity, and electrical conductivity. The carbon nanotubes may exhibit metallic or semiconducting properties due to changes in the length, diameter and function of the screw. Among them, the metallic carbon nanotubes themselves can be used as a molecular metal wire in nanoelectronics. Areas such as materials science play an important role. However, today's semiconductor components use metal as the wiring material, and according to the most famous Moore's Law in the semiconductor industry, the density of the transistor per unit wafer is approximately doubled every two years. Therefore, in recent years, semiconductor components have entered the sub-micron process. Nano-process, entering this nano-process must have nano-level development technology and production technology, and after the semiconductor component enters the nano-process, the number of transistors per unit area can be greatly increased, so it can represent both the transistor and the wafer. Shrinking. Smaller, the current nano-process is also developed from the original 90 nm process 1364058 • * MEGA 06-020TW-P05014 60 nm and 45 nm, but when the semiconductor components develop to 45 nm.. , also reached a certain level of technical bottlenecks, and to overcome this technology '·: bottlenecks, the current industry is the "nano carbon tube" as an important index -. -. Tube applications in today's semiconductor are accompanied by expectations. In view of the above, the present invention is directed to various technologies of the above passive semiconductor components, and proposes a nanocarbon tube circuit component structure and a method for continuously electroplating a circuit component and a circuit component structure thereof for use in the field of semiconductor passive components. . SUMMARY OF THE INVENTION The main object of the present invention is to provide a carbon nanotube circuit component. The structure and the process thereof are made of a conductive carbon nanotube as a material of a semiconductor component line, utilizing the conductivity characteristics of the carbon nanotube. Flexibility and high strength make the wiring of semiconductor components thinner and denser. Another object of the present invention is to provide a carbon nanotube circuit component structure and a process thereof, wherein a carbon nanotube is disposed on a semiconductor component, and the heat dissipation of the semiconductor component is performed by utilizing nanometer (high thermal conductivity of the carbon nanotube) For the above purpose of the present invention, a circuit component structure is provided, comprising: a semiconductor substrate; a thin wiring structure, on the semiconductor substrate. The thin wiring structure has at least one pad a protective layer, located in the thin connection; structurally, the pad is exposed in one of the openings of the protective layer; at least one nanometer; a carbon tube layer is located on the thin connecting structure and the protective layer, The carbon nanotube layer is electrically connected to the pad; a first metal layer is located on the carbon nanotube layer. MEGA06-020TW-P05014 · For the purpose of the present invention, a circuit component structure is proposed. Including 1 half of the leading edge substrate, a wire junction structure is also on the semiconductor substrate, a protective layer, located on the fine wire structure; at least a first carbon nanotube layer - in On the protective layer, the second carbon nanotube layer comprises a first wire 圏.. For the above purpose of the present invention, a circuit component structure is proposed. The package- _ ' · · · includes a conductive read substrate, a thin wire structure, located on the semiconductor substrate. ' The thin wire structure has a cover less a pad; a protective layer on the thin wire structure, the two pads are respectively exposed in the two openings of the protective layer; a carbon nanotube layer, located on the protective layer and connecting the two openings, The carbon nanotube layer is electrically connected to the two pads. For the above purpose of the present invention, a circuit component structure is proposed, including a semiconductor substrate; a protective layer on the semiconductor substrate; and a carbon nanotube layer For the above-mentioned aspects of the present invention, a wiring element structure is provided, comprising a semiconductor substrate having a first surface and a second surface, a plurality of half. The conductor element is located at the first a thin wiring structure on the first surface of the semiconductor substrate, the thin wiring structure comprising at least one pad; a protective layer on the fine wire structure; a nano carbon The tube layer is located on the second surface. The purpose of the present invention, the technical contents, the features and the effects achieved by the present invention will be more readily understood by the specific embodiments and the accompanying drawings. [Embodiment] 1364058 MEGA 06-020TW-P05014 a . ····_··. 1. The present invention is a structure and a process for the structure of a circuit element, wherein several different types of semi-conductor element structures are disclosed in the invention. Each type of semi-conductive 'earphone' has a part of the line system; the carbon nanotube is used as the material.?. • The first aspect of the seventh embodiment: Please refer to the first la-picture to provide a Substrate 1 〇, substrate 10 is usually a silicon stibstrate 'this base can be a .intrinsic 矽 base, a p, type 矽 base or a n-type dream base . For high-performance silicon, the wafer is made of SiGe or SiGe, Silicon-On-Insulator (SOI) substrate. Wherein, the base of the stone scorpion includes an epitaxial layer on the surface of the ruthenium substrate, and the cover layer on the other of the insulating layer includes an insulating layer (preferably oxidized stone eve) on the bottom of the base. The upper layer and the epitaxial layer are formed on the insulating layer. Referring to FIG. 1b, a device layer 12 is formed on the substrate 1 '. The device layer 12 generally includes at least one semiconductor device: and the device layer 12 is Within the surface of the substrate 1 and/or on the surface. The 'semiconductor component can be a MOS transistor 14, such as an N-type, a NMOS transistor (n_chai; nel MOS transistor) or a P-type MOS transistor (PMOS transistor). , ρ-channel MOS transistor), and the 'gold oxide half transistor 14 includes a source 16, a drain 18 and a gate 20, and the gate. 2 〇 is usually a polycrystalline dream. (poly Silicon), a polycrystalline metal-tungsten polycide, a tungsten silicide, a titanium silicide, a cobalt silicide, or a stone slab (salicide gate). In addition, the semiconductor device may also be a double carrier 1364058 MEGA06-020TW-P05014 (· c· transistor (bipolar. transistor)., diffusion metal oxide semiconductor (Difhised 'MOS / DMOS), lateral diffusion 'metal oxide semiconductor (Lateral Diffused :: ivte)S ; t0MOS), Chafged-Coupled Device (CCD), Complementary Gold-Thick Oxide Semiconductor (CMOS) Sensing Element, Photo-sensitive Diode, Resistor Element: A piece (formed by a polycrystalline layer or a diffusion zone in a crucible base). Various semiconductor circuits can be formed by using these semiconductor packages, such as a complementary metal oxide semiconductor (CMOS) circuit, an N-type MOS circuit, a P-type MOS semiconductor, and a bi-carrier complementary metal oxide conductor (BiCMOS). A circuit, a complementary metal oxide semiconductor sensor circuit, a diffusion metal oxide semiconductor power supply circuit, a laterally diffused metal oxide semiconductor circuit, or the like. In addition, the component layer 12 also includes a NOR gate or a NAND gate, and may also be an inverter, an AND gate, or a gate (an AND gate). OR gate) SRAM cell, DRAM cell, non-volatile meinory cell, and a flash memory Han unit ( Flash memory cell), an EPROM cell, a ROM cell, a magnetic RAM (JViRAM) cell, a sense amplifier (sense amplifier), operational amplifier (Op Amp, OPA), an adder (adder), a multiplexer (multiplexer), a pair of workers (diplexer), one. Multiplier, a class of analog/digital converter (A/D converter), a digital/analog converter (I)/A converter), a complementary metal oxide semiconductor 10 1364058 MEGA 06-020TW-P05014 sensing Yuan: CMOS sensor cell, a light-sensitive thin film · (photo-se Nsitive diode),. Mutual complement. Take the oxide half-nightmare, -v: double. Carrier complementary gold shame and semi-conductor. Body., a pair: sub-circuit (bipolar'citciiit). Or an analog circuit. In addition, in the Republic of China Invention Patent No. 239071 "Manufacturing Method of Nano Carbon Tubes", a method for fabricating a carbon nanotube transistor has been disclosed, which is also based on a germanium wafer on a germanium wafer. Forming a carbon nanotube transistor, Inver is not discussed in the present invention. C® Referring to Fig. 1c, a fine line structure 22 is formed on the substrate 10 and the component layer 12. The thin circuit structure 22 includes a fine-line conductivity Iayer 24 and a plurality of fine lines. A fine-line dielectric layer 26 and a plurality of openings 28 in the fine-line dielectric layer 20 and a conductive plug (fine_iine via piUg) in the opening 28. The uppermost thin line The road layer 24 can have at least one or a plurality of regions defined as a mattress 32. The thin circuit layer 24 is selected from aluminum metal, copper metal material in this embodiment or, more specifically, can be sputtered. The formed aluminum layer or the copper layer formed by the in-situ formation. Therefore, the fine circuit layer 24 may be: (1) all of the fine circuit layers 24 are aluminum layers; (2) all of the fine circuit layers 24 are copper layers; and (3) the fine circuit layer 24 of the bottom layer is an aluminum layer. The fine circuit layer of the top layer 24 is a copper layer; or (4) the fine circuit layer 24 of the bottom layer is a copper layer, and the fine circuit layer 24 of the top layer is an aluminum layer. In addition, the thickness of each thin circuit layer 24 is between 微米.〇5 μm (μιη) and 2 μm, and the thickness between 0.2 μm and 1 μm is 11 1364058 MEGA 06-020TW-P05014 Preferably, if the thin circuit layer 24 is a line, the lateral design standard (width) is between 2N nanometers and IS micrometers, and is between 2 nanometers and 2 micrometers. Jane is a poor person. First, the thin circuit layer 24 is an aluminum layer, and the aluminum layer of the thin circuit layer 24 is usually formed by physical vapor deposition (Physical Vapor Deposition., +ρν·ρ) to form a method such as "sputtering". To form, then: through the deposition of a thickness between 0.1 microns and 4 microns (preferably between 0.3 microns and 2 meters) of a layer of light to map the layer. Case. The best way to do this is to dry the wafer (dry piasnia) etching (usually containing fluorine paste). . Another 'adhesion/barrier layer can be selectively formed under the aluminum layer, wherein the adhesion/barrier layer can be titanium, titanium tungsten alloy, titanium nitride or a composite layer formed by the above materials. An anti-reflective layer (such as titanium nitride) may also be selectively formed on the aluminum layer. 9 In addition, the opening 28 may be selected by chemical vapor deposition (CVD) tungsten metal. The manner is filled, and then the tungsten metal layer is ground in a chemical mechanical polish (CMP) manner to form a conductive plug 30. Next, it is explained that the thin circuit layer 24 is a copper layer, and the copper layer of the thin circuit layer 24 is often formed by a plating and damascene process, which is described as follows: (1) deposition of a copper diffusion a barrier layer (for example, an oxynitride layer or a nitride layer having a thickness of between 0.05 μm and 0.25 μm); (2) plasma enhanced CVD (PECyD), spin coating ( Spin-on c〇ating) or high-density electropolymerization gas 12 1364058 MEGA 06-020TW-P05014 phase deposition (High Density Plasma CVD, .hdpcvd) with a thickness ranging from G1 micron to 2.5 micron - fine line Electrical layer 26, ', in this: Tianyuan Road dielectric layer% is between 〇3 micro to 1 $ micro: the thickness between the senses is more ambiguous. (3) using sediment thickness between 〇 ι micro-finishes a two-photoresist layer between 4 micrometers to pattern the visible dielectric layer %, wherein the photoresist layer has c·c·, ,, between 〇.3 micro 歩 to 2 micro. Preferably, the photoresist layer is exposed and developed to form a plurality of openings and 7 or a plurality of trenches. Then removing the light-emitting layer; (4) depositing a barrier/barrier layer and a sub-layer by using _ or chemical vapor deposition ((10) cutting (7). The following: the barrier layer includes germanium, nitride The button, titanium nitride, titanium or titanium tungsten is a composite layer formed by the above materials. In addition, the seed: 7 疋 steel layer 'and the copper layer can be made of (4) copper metal, chemical J ' steel metal 'Or formed by chemical vapor deposition of a copper metal and then bribe metal; (7) the thickness of the electricity money is between G. still slightly - the copper layer is on the seed layer, which in turn is a copper bond: Further, a steel layer between 2 μm and 1 μm is preferred; (6) and (preferably a chemical mechanical polishing) wafer is removed in a manner not to be in the fine-line dielectric layer 26 The copper layer, species and/or barrier layer in the opening or trench, from the ancient to the exposed thin dielectric layer under the adhesion/barrier layer, after the chemical mechanical grinding of the left drinking, only the opening is in the opening Or the golden part of the ditch. 〆Ϊ (4) "The metal (4) called as the metal (the line or the pick 30 (the thin circuit layer 24 connecting the two phases. In addition, the "° double-damascene process simultaneously forms conductive plugs 30 and metal in one electric clock process and human chemical mechanical grinding. 13

I36405S MEGA 06-020TW-P05014 Line or metal plane. Two photolithography processes and two electroplating processes are suitable: use a dual damascene process. The double damascene process is in the above-mentioned single-V. _ inlaid process patterning a dielectric Zhanzhi step (3) and deposited metal. Layer: stepping (4) 'increase' 吏 multi-deposition and patterning The step of making the dielectric layer. '〇〇·: c· Then say that the fine dielectric layer 26' is a fine-line dielectric layer 26 which is a system of vaporization and vaporization, and it is assisted by electric propellers. Deposition, high-density electrification, vapor deposition or spin-on formation. The material of the fine-line dielectric layer 26 includes silicon oxide, Siiicpn nitride, silicon oxynitride, and tetraethoxy monoxide formed by plasma-assisted chemical vapor deposition. (PECVD TEOS), spin-on glass (SQG, Dream Oxide or Oxygen), Fluorinated Silicate Glass (FSG) or a low dielectric constant (low-K) material such as black diamond film (Black) Diamond, which is a product of Applied Materials, the company's translation is called Application. Material Company), ULK CORAL (product of NoVellus), SiLK (IBM) low dielectric constant dielectric material. Cerium oxide formed by electric paddle assisted chemical gas deposition, tetraethoxysilane formed by plasma assisted chemical vapor deposition or oxide formed by high density plasma having a dielectric constant between 3.5 and 4.5 K; a pulverized glass formed by plasma-assisted chemical vapor deposition or a gas-parameter glass formed at a density of 1% and having a dielectric constant value between 3.0 and 3.5, and a low dielectric The constant dielectric material has a dielectric constant value between 1.5 and 3.5. A low-k dielectric dielectric, such as a black diamond: a film, which is porous, and includes oxygen, carbon, helium and oxygen, has a molecular formula of HwCxSiyOz. This thin line dielectric layer 26 is typically

mmE MEGA 06-020TW-P05014 includes inorganic materials (inorganic.material), used to achieve a large thickness of .2 . micro. m 6 each, the thickness of the fine-line dielectric layer 26 is between 0.05 micron to 2 microns - between. The openings 28 in each of the dielectric layers 26 are formed by etching the patterned photoresist layer by wet or dry etching, wherein the preferred etching method is dry etching. Dry silver engraving. The species includes flu〇rine plasm.a. . . . c. c. Referring to Figure lc, a protective layer 34 is formed on the thin wiring structure 22, which plays a very important role in the present invention. The protective layer 34 is in the integrated circuit industry. Medium is an important part of the process, as described in the book "Silicon Processing in the VLSI era", Volume 2, published by Lattice Press in 199, and the protective layer 34 is in the integrated circuit process. It is defined as the final layer and is deposited on the entire upper surface of the wafer. The protective layer 34 is an insulating and protective layer that prevents mechanical and chemical damage during assembly and packaging. In addition to preventing mechanical scratches, the protective layer 34 also prevents mobile ions (such as sodium ions), and transition metals such as gold and steel from penetrating into The integrated circuit components below. In addition, the protective layer 34 can also protect the underlying components and connection lines (fine line metal structure and fine line dielectric layer) from moisture intrusion. The protective layer 34 typically comprises a silicon nitride layer and/or a silicon oxynitride layer and has a thickness between 0.2 microns and 1.5 microns and is between 〇.3. The thickness between the micron and the ι·〇 micron is preferred. The other materials used in the protective layer 300 are yttrium oxide formed by plasma-assisted chemical vapor deposition, and the plasma-enhanced type of bismuth tetraethylene 15 Τ 364 ϋ 58 MEGA 06-020TW-P05014 base-based salt (plasma-enhanced, tptrap.thyl orthosilicat, :PETEO.S). Oxygen. Compound, scale, glass (phosphosilicate.glkss, .. PSG), boron fill An oxide of borophospho silicate glass (BP.SG) and a density of electricity (HDP). Next, some examples of the protective layer consisting of composite layers are described. The order from bottom to top is: (1) The thickness is between 0.1 μm and 1.0 μm (the preferred thickness is between . micro c· c· Tantalum oxide with a thickness of between 〇25 μm and 12 mm (preferably between 0.35 μm and 1.〇μm) between meters and 0.7 μm The layer .34 is usually covered on a metal connecting line formed of aluminum, wherein the metal connecting line formed by aluminum is generally included in the process of sputtering aluminum and etching aluminum, and (2) the thickness is between 0. 05 micrometers to 〇. Nitrogen oxides per 100 micrometers (preferably between 0.1 and 0.2 micrometers thick) have a thickness of between 0.2 micrometers and 1.2 micrometers (preferably between 1 micrometer and 2 micrometers). The oxide/thickness of the oxide/thickness between 〇.2 μm and 12 μL (preferably thick between 0.3 μm and 0.5 μm) is between 〇2 = m and 1 _2 μm (better thickness) An oxide of between 3 micrometers and 6 micrometers. This type of protective layer 34ii is often covered with gold formed of copper. Connection line, wherein the copper form. To the connecting line generally comprises a metal electric clock, and the chemical mechanical polishing damascene process. In addition, the oxide layer in the above two examples may be an oxide oxide formed by plasma-assisted chemical vapor deposition, plasma-enhanced tetraethyl ortho-ruthenium hydride/plasma-plasma The oxide of PETE〇s) utilizes an oxide formed by a high-density slurry. The above content 咎 field recognition is applicable to all implementations of the present invention. 16 1364058 ~~~~~~~~~~ • * MEGA 06-020TW-P05014. Please refer to Fig. 14, in which the protective layer 34 forms at least one opening 36, the opening of the protective layer .34. .36 is formed by wet etching or dry etching, wherein dry etching is preferred. In addition, the opening 36: has a size of between 0.1 micrometers and 200 micrometers, and preferably between 1 micrometer and 100 micrometers or between 5 micrometers and 30 micrometers, and the other opening 36. The shape can be a round square, a rectangle or a polygon, so the above

The size of the mouth 36 refers to the diameter of the circle, the length of the square, the longest diagonal of the polygon, or the width of the rectangle, wherein the length of the rectangle is between 1 micrometer and 1 centimeter, and 5 microns to 200 microns are preferred. The opening 36 of the protective layer 34 also has different sizes for the components of the component layer 12. Generally, the size of the opening 36 of the protective layer 34 is between 0.1 micrometers and 100 micrometers, and is between 0.3 micrometers and 30 micrometers. ―...micron is preferred; if the voltage regulator, transformer and ESD protection circuit are set in the component layer 12, the size of the blue port is larger, and the range is between 1 micron and Between 150 microns and between 5 microns and 100 C® microns is preferred. In addition, the opening 36 exposes the uppermost metal pad 32 of the thin circuit layer 24 for electrically connecting the over-passing line or plane of the protective layer 36. The structure described above is defined as a wafer, such as a silicon wafer, which is fabricated using integrated circuit processing techniques of different generations, such as 1 micron, 0.8 micron, 0.6 micron, 0.5 micron, 0.35 micron, 0.25 micron, 0.18 micron, 0.25 micron, 0.13 micron, 90 nanometer (nm), 65 nm, 45 nm, 35 nm, 25 nm technology, and these 17 MEGA 06-020TW-P05014 - product The generation of the technology is defined by the gate of the oxy-period 14: length: gate lengih or charuiel length. The size of the wafer is, for example, 5 ' '6 吋, 8 pairs, 12 忖 or 18.-: 吋. The substrate 10 is fabricated using a lithography process that includes coating, exposing, and developing photoresist: The photoresist used to make the substrate 10 has a thickness between 0.1 micron and 04 micron' and is exposed to a five-fold (5X) stepper or scanner. Wherein, the multiple of the stepper is that when the light beam is projected onto the wafer from a reticle (usually composed of quartz), the ratio of the pattern on the light to the wafer is reduced by five times (5X). It means that the proportion of the pattern on the mask is five times that of the pattern on the wafer. Scanners that use the previous generation of integrated circuit process technology are usually scaled down by four times (4 inches) to improve the resolution. The beam wavelength used by the stepper or sweeper is 436 nm (g-lipe), 365 nm (i_iine), 248 nm (deep UV, DUV), 193 nm (DUV), 157 Nano (DUV) or 13.5 nm (very short UV 'EUV). Another 'high-index immersion' lithography technique can also be used to complete the fine circuit layer 24 on the wafer. In addition, the wafer is fabricated in a clean room (class 1) or better (e.g., level 1). Level 1 () clean room allows. The maximum number of dust particles per cubic inch is: contains more than or equal to 1 micron of dust particles no more than .1, containing greater than or equal to 5.5 microns. No more than .10 particles containing more than or equal to 〇3 μm. No more than 30 pieces of dust particles containing greater than or equal to 〇.2 μm are not over 75 particles containing no more than or equal to micrometers. More than 35〇1364058 ~ MEGA 06-020TW-P05014 .>> and wait for 'level:::1, no dust" room; then, let each stand. Fang Yingxi's largest gray grain: the number of children is Dust containing more than or equal to .5 micron does not exceed 1:,..:: contains more than or equal: dust particles of 0.3 micron are not more than 3,; particles, containing ί..:: , having a particle size greater than or equal to .. 〇·2 microns. No more than 7 particles, containing more than v ...... or equal to .0.1. Micro. meters. Gray. Dust particles. No. 3 5. When copper is used as the fine wiring layer 24, it is necessary to use a metal/metal cap (not shown) to protect the opening of the protective layer 34. 30.

The copper pad 32 is provided to protect the pad 32 from oxidation and damage, and can be used as a subsequent wafer. The metal top layer comprises a layer of aluminium, a layer of gold, a layer of titanium (Ti), a layer of titanium-tungsten alloy, a layer of Ta (Ta), a layer of tantalum nitride (TaN) or A layer of nickel (milk). Wherein, when the top layer of the metal is a layer of inscription, a barriei layer is formed on the copper pad and the metal top layer, and the barrier layer comprises tantalum, titanium crane, titanium nitride, tantalum Nitride button, chromium (Cr) or nickel. Next, an over-jia^sivation scheme is formed: wherein the structure on the protective layer in this embodiment comprises a circuit layer composed of a carbon naiiotube. First, please refer to the "Ip" household) t, the formation of a sticky, adhesion layer (adhesion / barrie-r layer) 38 on the protective layer 34 and the pad 32, the adhesive barrier layer 38 The material may be titanium, crane, drill, nickel, nitride, titanium tungsten alloy; |fl, chrome, sodium, chrome-copper alloy, tantalum, tantalum nitride, alloy formed by the above materials or It is a composite layer composed of the above materials. In addition, the adhesion/barrier layer can be formed by electroplating (eUcttoplating), f:M (electioleiss plating), chemical vapor deposition or physical vapor deposition (for example, deplating), wherein

136405S MEGA 06-020TW-P05014 ::Physical: The gas phase accumulates into a more sinuous shape. The method is: for example, metal plating process Λ another. H" ... this adhesion. / barrier barrier plus - thickness / thickness: Department of Dragons 0)..02. Micron to 0.8 years old. It is between: ά.:05: Weiwei, to: 0:2 micro. The thickness between the two is Vv. Please refer to the map: lf: lf diagram; shown: the shape of the following: · the thickness is between 1 micron to. 1〇丨;.: Micro..m: The T-catalyst metal layer 40 is on the adhesion barrier layer 38. This catalyst metal layer 40 forms an important step of the carbon nanotube: layer, and the following describes: Media gold 乂. belongs to the 'layer 40 formation side _ method: -

A method for forming a dielectric metal layer 40: in this manner, a catalytic metal layer is formed by a solution method: 40, first, a catalyst metal is attached to a precious metal particle, and the catalyst metal includes iron, cobalt, and nickel. The metal, and the precious metal particles include gold, silver, turn, and copper or alloys thereof. The preferred precious metal is silver metal, and the particle size of the precious metal particles is between 〇·〇! to 10 microns. There are two ways to attach the catalyst metal to the precious metal particles. The first method is the impregnation method, and the second method is the sedimentation method. Both methods require the precious metal particles to be dispersed in the water.

The impregnation method uniformly disperses the precious metal particles in the solution by ultrasonic wave aqueous solution in an ultrasonic wave oscillating manner, and then adds the catalyst-containing metal salt solution and uniformly mixes the two metal solutions, for example, nitrate. The solution or the sulfate solution is then concentrated by heating, and then the solvent in the mixed solution is removed, so that the catalyst metal can be distributed on the precious metal particles. The deposition precipitation method is to add an aqueous solution containing precious metal particles to an aqueous alkaline solution, such as ammonia, to make the pH of the mixed solution between 8 and 9, and then heat the mixed solution. Thus, the precious metal particles 20 Π64058 * · MEGA 06-020TW-P05014 . The sub-surface is changed to be alkaline, and then the aqueous solution containing the catalytic metal salt is added and the interference is uniform. The class is, for example, a nitrate or a sulfate, and then: a human precipitate is added: the agent and the reducing agent precipitate and reduce the catalytic metal, the sinking agent such as ammonia water, and the reducing agent such as an oxime chain, Finally, the solvent in the mixed solution is removed, so that the contact-agent metal can be distributed on the precious metal particles.

C. Next, the precious metal particles to which the catalytic metal has been attached are scattered on the surface of the adhesive barrier layer 38, wherein the precious metal particles to which the catalytic metal has been attached are dispersed on the surface of the adhesive barrier layer 38 in a number of ways. In the first method, the particles are mixed in a polymer glue, wherein the ratio of the precious metal particles of the catalytic metal to the polymer mash is 1:10 to 1:3, and the polymer glue contains one Cellulose resin (35 wt%), solvent dl-1-pair-dl-a-terpineol 50 wt%+, as a dispersant. .ate) 1 Owt% and glass powder 15wt%. The function of this glass frit is to increase the adhesion. Then, the mixed colloid is coated on the surface of the adhesive barrier layer 38, baked and baked in air at 300 ° C to 500 ° C to remove the polymer glue, so that the catalyst metal can be attached. The precious metal particles are interspersed on the adhesive barrier layer 38. The second type of dispersion is to add precious metal particles with a catalyst metal attached thereto to an organic solvent such as ethanol, which is ultrasonically oscillated to disperse the particles in the mixture, and then directly apply the mixture to the adhesive. On the barrier layer 38, the organic solvent is removed by baking, and the greedy metal particles to which the catalyst metal is adhered are spread on the adhesion barrier layer 38. : 21 1364058 MEGA 06-020TW-P05014 The second method for forming the riding metal layer 40: The second method for forming the catalytic metal layer 40 is to use a method of collecting a clock, which is a formula. Provide a town full: a total target, nickel silver. He/gold target., nickel-palladium alloy target., nickel. Platinum alloy target or: record copper i alloy target, among which better target In the case of a nickel. silver alloy, nickel silver metal is formed on the substrate in the reaction chamber. :

Referring to FIG. 1g, a substrate 10 is placed in a reactor for thermal chemical vapor deposition to form a nanometer having a thickness between 100 nm and 20 μm on the surface of the catalytic metal layer 40. Carbon tube layer 42. The reaction gas includes an inert gas (such as helium, argon, nitrogen, etc.), hydrogen and a carbon source gas, wherein the carbon source gas includes hydrocarbon or carbon monoxide, the reaction temperature is 400 ° C to 600 ° C, and the reaction pressure is 0.5 to 3 large ammonia pressure, and the diameter of the carbon nanotube layer 42 formed after the reaction is distributed between 1 and 200 nm. Alternatively, a magnetic device may be disposed on the lower surface or below the substrate 10, so that a conductive carbon nanotube is attracted to the catalytic metal layer 40 when the carbon nanotube layer 42 is formed. Referring to FIG. 1h, an adhesive barrier layer 44 is formed on the nano-carbon mask layer 42. The method of forming the adhesive barrier layer 44 is the same as the formation of the adhesive barrier layer 38 described above. Discussion. Referring to Figure li, a sub-layer 46 is formed over the adhesion barrier layer 44. This seed layer 46 facilitates the placement of subsequent metal lines, and thus the material of the seed layer 46 also varies with subsequent metal line materials. When the seed layer 46 is plated to form a metal line of copper material, the material of the seed layer 46. is preferably copper; when the metal material is formed by electroplating to form a silver material: the material of the seed layer 46 is preferably silver. When the metal line of 22 1364058 "7- MEGA 06-020TW-P05014 is to be electroplated to form a palladium material, the material of the seed layer 46 is preferably palladium; when electroplating is formed to form a metal line of platinum material, the seed layer 46 The material of the material is preferably platinum; when it is electroplated to form the metal material of the bismuth material, the material of the seed layer 46. is recorded as '/: good; when the metal wire is to be plated to form a nail material哼, seed layer 46: the material is preferably 钌; when electroplating to form the metal line of bismuth material, the seed layer.. 46. The material is better than ;; when: to form a nickel-poor metal line The material of the seed layer 46 is preferably recorded. .

(1) As shown in FIG. 1j, a patterned photoresist layer 48 is formed on the seed layer 46. The patterned photoresist layer 48 has at least one opening .50. The opening 50 exposes a portion of the seed layer 46. The patterned photoresist layer 48 has two types: a formula, which is: (1) a liquid photoresist which is formed by a single or multiple spin coating method or a printing method. The thickness of the wet film photoresist is between 3 microns and 60 microns, preferably between 5 microns and 40 microns; and (2) the dry film photoiesist, which utilizes Forming a laminating method (laminating.imethod). The thickness of the dry film photoresist is between 30 micrometers and 300 micrometers, and preferably between 50 micrometers and 150 micrometers. In addition, the photoresist may be positive. Positive-type or negative-type, and in the case of better resolution, positive-type thick photoresist is preferred. (aligner) or double (IX) stepper exposes the photoresist. This double (IX) refers to when the beam is from a reticle ( When the film is usually projected on a wafer by quartz or glaze, the pattern on the reticle is reduced in proportion to the circle on the crystal, and the pattern ratio on the reticle is the same as the pattern on the wafer. The 23 imm MEGA 06-020TW-P05014 beam wavelength system of the 准 or double stepper is 436 nm (g-line), 397 nm (h-line), 365 奈:. I-line), g/h line (combined with g-line and :h-line) or g/h/i linq (combined

;. with -i-line). Use beam wavelength. It is g/h.line. or g/h/L:....line one step. Into the exposure machine (: or double alignment machine) can be in thick photoresist or thick Sense.. • Light emulsion polymer.. provides greater light intensity (light .. 'intensity) ·; · ilfc, this case of 'the photoresist layer 48 of the opening 50 - shape package · 栝: Coil shape, square or round, etc. · Refer to the lk diagram. A metal layer 52 is formed by electroplating on the seed layer 46 in the C® opening .5.0 and on the buffer layer 34. The metal layer 52 is, for example, gold, copper, silver. ,:::Zhao, sister, .. lack, red, chain or town _ single layer of gold. is a layer of structure. Or a composite layer composed of the above metal materials, the metal layer formed by the above metal material The thickness of 52 is between 1 micrometer and 50 micrometers, and the thickness may be between 2 micrometers and 30 micrometers. In the embodiment, the metal layer 52 is made of gold; When the opening 50 of the resist layer 4S is in the shape of a coil, the carbon nanotube layer 42 and the metal layer 52 are used as inductors. The components are used.., .1... Please refer to the 1L. figure to remove the patterned photoresist layer. 48, wherein the patterned photoresist layer 48 can be removed by using an organic solvent, such as acrylonitrile, alcohol, etc., and can also be removed by using an inorganic solvent, such as sulfuric acid and hydrogen peroxide (H2S04, Η202), etc. The patterned photoresist layer 48 can also be removed by high pressure oxygen (〇2) firing. < .. - Referring to the lm diagram, the rafter layer 46, the adhesive apex layer 44, the carbon nanotube layer 42, the catalytic metal layer 40, and the adhesive layer not under the metal layer 52 are removed. The barrier layer 38, wherein if the material of the seed layer 46 is gold, it can be < δ 24 MEGA 06-020TW-P05014 ... using the iodine-containing rice engraving solution, : 3⁄4 to remove the adhesion: the barrier Layer 44· and adhesion resistance... barrier layer. More than 3 ways are divided into dry etching and wet teaching, where the dry type is like ^. Using high pressure argon gas to smear recording:, and wet etching When the adhesion barrier layer .44, . , 38 is a titanium tungsten alloy, it can be removed with hydrogen peroxide, and the carbon layer: tube layer 42 can be removed by high pressure oxygen (〇 2) burning, and then The catalyst layer 40 can also be removed by high pressure argon (Ar), or by hydrogen peroxide and ammonia (NH4OH, H2〇2) or hydrogen peroxide and hydrogen halide (H2〇2, HC1). Remove. G· Please refer to the ln diagram to perform a dicing step to generate a plurality of semiconductor wafers _.(chip) 54' and then use a wire bonding process to form a wire 56 on the surface of the metal layer 52, whereby the wire 56 is electrically connected to the external circuit. on. The first aspect of the first embodiment is explained above. The second aspect of the first embodiment: .. Please refer to FIG. 1 , the second aspect is similar to the structure of the first aspect. The difference is that the second aspect can form a thickness of 2 μm. A polymer layer 58 between 50 microns is overlying the protective layer 34 and the metal layer 52 and forms at least one open exposed metal layer 52 surface. The polymer layer .58 may be a polyimide. Polyimide 'PI', benzocyclobutene (BCB), paryl0ne, epoxy-based material, such as epoxy resin or by Renens in Switzerland The ph〇toepoxy. SU-8, elastic material (elastomer) provided by Sotec Microsystems, for example, silky silk. When the polymer layer 58 is a photosensitive material, the polymer layer 58 can be patterned only by a lithography process (without engraving process); then, see ip FIG. 25 MEGA 06-020IW -P05014 shows the curing step of the polymer layer 58 and then cutting. The steps are also the same as the semi-conductor: the wafer wafer (chLip) 54, and then the wire-forming process. The wire 56: in the polymer The metal layer 52 in the opening 58 of the layer 58 is electrically connected to the external circuit by the wire 56. The above-described example of the second embodiment is completed. The third aspect of the first embodiment. Referring to the lq figure, the third aspect is similar in structure to the second aspect and the first aspect, and the difference is in the first aspect and the second aspect. The wire 56 is formed directly above the pad 32 of the thin circuit structure 22, and the third aspect is formed on the side of the opening 36 of the protective layer 34 when the metal layer 52 is formed. A partial region is defined on the surface of the metal substrate 52 as a metal pad 62. The metal pad 62 is viewed from a top view in a different position from the pad 32 in the opening 36 of the protective layer 34. The structure of the third aspect In the + industry, it is called "Redistribution. Layer (RDL)"; see the lr figure, then the patterned photoresist layer 48' is also removed and the seed layer not under the metal layer 52 is removed. 46. Adhesive barrier layer 44, nanocarbon layer 42, catalytic metal layer 4Q, and adhesion barrier layer 38; see also shown in Figure I. Polymer layer 58 is also formed in protective layer 34 and metal layer 52. And the polymer layer 58 also forms at least one opening 60 to expose a portion of the metal layer 52; see the Figure It diagram, also The layer 58 is: a cure step, and the dicing step also produces a plurality of semiconductor chips 54 which are formed by the wire bonding process to form the surface of the metal layer 52 of the wires 56 in the openings 60 of the polymer layer 58. By this wire, the electrical connection is made to the external circuit. The third state of the first embodiment is completed above. TT64m MEGA 06-020TW-P05014 The fourth aspect of the first embodiment.: Please refer to the ..lu diagram, the lvth adjustment and the lwth diagram, the fourth aspect and the first to third embodiments. The structure is similar. The difference in structure is that there is another polymer layer between the gold layer of .4 and the protective layer 34 having a thickness between 2. micrometers and .50 micrometers. The polymer layer 64 functions to buffer the stress during the wire bonding process, so that the component layer 12 under the metal layer 52 is not easily damaged. The polymer layer 64 is the same as the polymer layer 58 and has the same structure. The lu map, the lv graph, and the lw graph are shown. The above description of all the embodiments of the c. an embodiment is completed. In addition, it is to be noted that many of the structural parts of the following embodiments are the same as the processes, materials, and physical properties of the first embodiment, and therefore will not be discussed. For example, the substrate 10, the element layer i2, and the MOS semiconductor 14 of the first embodiment are not discussed. The source electrode 16, the drain electrode 18', the gate electrode 20, the thin circuit structure 22, the pad 32, the protective layer 34, the adhesion barrier layer 38, the catalytic metal layer 40, the nano carbon layer 42 and the like, so the following embodiments The mere explanation of the differences in the construction or feature technology is specifically stated here.

The first aspect of the second embodiment: Referring to FIG. 2a, the substrate 10, the element layer 12, the thin wiring structure 22, and the protective layer .34 of the second embodiment are identical in structure to the first embodiment, and the same portion It will not be discussed here, but the difference is that the second embodiment forms at least two openings 66 in the protective layer 34. The two openings 66 respectively expose one of the pads 68 of the thin circuit layer 24. The dimensions of the two openings 66 are Between 04 徼 and 200 μm, and preferably between 1 μm and 100 μm or between 5 μm and 30 μm, the shape of the other opening 66 may be a circle 27 1364058 MEGA 06-020TW- P05014 is a shape, a square, a rectangle or a polygon, so the size of the above-mentioned opening 68 is: the diameter of the circle: the length of the square, the longest dimension of the polygon, the length of the V-angle or the width of the rectangle: the size. The length dimension of the rectangle is between 1 micro and .1 centimeters and is better than .5 micrometer to 200 microseconds. . . Please refer to FIG. 2b, 'forming an adhesive barrier layer 70 on the protective layer 34 and the pad 68, the thickness of the adhesive barrier layer 70 is between α.〇2 micro:'.

Between m and 0.8 μm, and preferably between 0.05 μm and 0.1 μm: as shown in Fig. 2c, forming a thickness between 1 μm and 10 μm. a catalyst metal layer 72 is adhered to the barrier layer 70; as shown in FIG. 2d, a carbon nanotube layer 74 having a thickness between 100 nm and .20 μm is formed on the catalytic metal layer 72. As shown in FIG. 2e, a patterned photoresist layer 76 is formed on the carbon nanotube layer 74, wherein the patterned photoresist layer . . . 76 has a plurality of openings 78 exposing a portion of the carbon nanotube layer 74, Moreover, the thickness of the patterned photoresist layer 74 is between 3 micrometers and ¢0 micrometers, and preferably between 10 micrometers and 40 micrometers; as shown in FIG. 2f, C®: High-pressure argon (Ar) gas splashing removes the exposed carbon nanotube layer 74. and the catalytic metal layer 72, at which time the thickness of the patterned photoresist layer 74 is reduced to a certain extent. Therefore, the thickness of the patterned photoresist 76 must have a certain thickness. Preferably, the patterned photoresist layer 74 is more than three times thicker than the carbon nanotube layer 74; as shown in FIG. 2g, the patterned photoresist layer is removed. 76 ?Remove again The catalytic gold layer 7.2 and the adhesion barrier layer 70 under the carbon nanotube layer 74; as shown in Fig. 2h, a polymer layer 8 is formed, covering the protective layer 34 and the carbon nanotubes. On layer 74, the hardening step of the party layer 80 is performed; as shown in Fig. 2i, 28 1364058 MEGA 06-020TW-P05014. The cutting step is further performed to form the substrate 10. Forming a plurality of semiconductor wafers 5 The first aspect of the second embodiment is illustrated by: the connection of the carbon nanotube layer 74.; the upper pad. 68, which is the carbon tube layer: 7.4 as the connection line (interconnectib'n) Use 'also. From: as / internal connection line. Way and '·: non-external circuit connection, so the surface of the carbon nanotube layer 74 does not need to form. Other metal layers. So complete the second implementation The second aspect of the second embodiment. The second aspect of the second embodiment is similar to the first aspect The structure differs in that the carbon nanotube layer 74 and the protective layer 34 form a salty polymer layer 82. The carbon nanotube layer 74 is separated from the protective layer 34, and the polymer layer is formed. For the method of 82, please refer to the process of the polymer layer 5S of the first embodiment. The third aspect of the second embodiment;

Referring to FIG. 2k, the third embodiment of the second embodiment is similar to the first aspect structure, and the structural difference is that at least one opening 84 is provided on the polymer layer 80 to expose the carbon nanotube layer. 74, so the third aspect of the second embodiment is followed by the step of FIG. 2h, followed by a hardening step to harden the polymer layer 80; as shown in FIG. 2L, sequentially form a Adhesive barrier layer 86 and a sub-bump 88 are on polymer layer 80 and exposed carbon nanotube layer 74; as shown in FIG. 2m, a patterned photoresist layer 90 is formed on seed layer 88, which is patterned. A plurality of openings 92 of the photoresist layer 90 expose the seed layer 88; as shown in FIG. 2n, a seed layer 88 having a thickness between 1 micrometer and 30 micrometers and a metal layer/94 in the opening 92 may be formed; As shown in the 2nd Duke, go. Except for the patterned photoresist layer, 90, and go to the seed layer below 29 136405? MEGA 06-020TW-P05014' of the metal layer 94. .8 with barrier layer · % . The metal bay of this embodiment: 9 4 - can be Han.. The wire process is absolutely formed. The wire (not shown) is electrically connected to the external circuit. - The third embodiment:: ι. Aspect: .:. 参 * - * ·.. . - . .* ; *. . --···: ... color reading - the third - a - humiliation 10. The component layer U and the protection layer 34 are the same as those of the first embodiment, and the same portion is not discussed here, but differs in the first embodiment of the third embodiment. The protective layer 34 of the aspect does not have any openings exposing the pads 32. Referring to FIG. 3b, an adhesive barrier layer is formed. 9.6. On the protective layer 34, the thickness of the adhesive barrier layer 96 is between 微2 and 〇8 μm, and is referred to as S0. A thickness between .05 microns and 〇2 microns is preferred; as shown in Figure 3c, a -catalytic metal layer having a thickness between i microns and ι μm is formed. 98% on the adhesion barrier layer As shown in the figure, a carbon nanotube layer having a thickness between _ nanometer and 20 micrometers is formed on the catalytic metal layer 98; as shown in Fig. 3e, the thickness is formed黏2 between 0 micrometers and 0.8 micron, an adhesive barrier layer 1〇2 and a sub-layer 1〇4 are placed on the carbon nanotube layer; as shown in the third layer, a patterned photoresist layer is formed. 1〇6 is on the seed layer 1〇4, wherein the patterned photoresist layer 1 (10) has at least a coil-shaped opening (10) exposing a portion of the surface of the seed layer 104 and the patterned photoresist layer 1G6 has a thickness of 3 μm. Between 6 and 10 microns, and preferably between 5 and 40 microns; as shown in the % view, the electric clock forms a thickness between 1 micron and 3G _ - the metal layer is open at the opening 1 On the seed layer 104 in 8; as shown in FIG. 3h, the patterned photoresist layer 1〇6 is removed, and the seed layer 30 not under the metal layer 11〇 is removed. MEGA 06-020TW-P05014 1〇4, Adhesive resistance Barrier. ίο》, carbon nanotube layer 1〇〇, catalyst. Metal layer 98 and adhesion barrier layer 9.6; as shown in Fig. 3i, this metal layer exhibits a line shape 'this coil shape line system For the use of an inductor element, such as a 3nductor, a patterned polymer layer U2 is formed on the metal layer u and the layer 34, and at least one opening 114 of the patterned polymer layer 112 is formed. Exposing the surface of the metal layer 110, in this embodiment, the patterned polymer layer II2 has two openings II4 exposing the metal layer 11〇, and then performing a hardening step 'hardening the patterned polymer layer 112; as shown in the figure: 3k As shown, a cutting step is performed to scribe the substrate 10. The plurality of semiconductor wafers 54 are formed, and the wire 56 is formed on the surface of the metal layer 110 in the opening 114 by a wire bonding process, and electrically connected to the external circuit via the wires 56. Third Aspect of the Third Embodiment:: : Referring to Fig. 3L, the second embodiment of the third embodiment is similar to the first aspect of the third embodiment. The difference is that a polymer layer 116 is formed on the protective layer 34 before the step of forming the adhesive barrier layer 96. For the crucible, that is, a polymer layer is provided between the adhesive barrier layer 96 and the protective layer 34. 116. After the polymer layer 116 is hardened, the adhesion barrier layer 96 and the catalyst metal layer 98 are formed by the same process as the first embodiment of the third embodiment. , the carbon nanotube layer 1 〇〇, the adhesive layer and the barrier layer 102, the seed layer 104, the patterned photoresist layer 106, the metal layer 110, the patterned polymer layer 112 and the wires 56, etc., and the embodiment The polymer layer, 116 acts to enlarge the distance between the formed coiled carbon nanotube layers 100 and the fine line structure μ, because the coil shape of the nano carbon is connected when the external circuit is connected via the wire 56. Tube layer.1〇() 1364058 • » MEGA 06-020TW-P05014 By the current, that is, the induced electromotive force is generated, the thin circuit layer 24 under the protective layer 34 is induced, and the coil shape winter carbon nanotube layer 100 is generated. A lot of static electricity, too close to 1500 volts (V), so the polymer 116 must have a certain degree of thickness. The shape of the ring carbon nanotube Su wiring layer and the thin layer 1〇〇 spaced .24, .24 in order to prevent damage to the fine wiring layer. The first aspect of the fourth embodiment:

The first embodiment of the fourth embodiment is similar to the first embodiment of the third embodiment. Please refer to FIG. 4a, which is a third embodiment of the third embodiment. The adhesive barrier layer 118 is on the protective layer 34. The thickness of the adhesive barrier layer 118 is between Q.02 micrometers and 0.8 micrometers, and the thickness is preferably between 0.05 micrometers and 0.2 micrometers. As shown in the first " 4b, a catalyst 'metal layer 120 having a thickness between 1 micrometer and 10 micrometers is formed on the adhesion barrier layer 118; as shown in Fig. 4c, the formation has a twist of 100 A carbon nanotube layer 122 between nanometers and 20 micrometers is on the catalytic metal layer 120, and the carbon nanotube layer 122 is composed of a non-conductive carbon nanotube; as shown in Fig. 4d, a The patterned photoresist layer 124 is on the nanocarbon C®. tube layer 122, wherein the patterned photoresist layer 124 has a plurality of openings 126 exposing a portion of the carbon nanotube layer 122, and the thickness of the patterned photoresist layer 124 The system is between 3 microns and 60 microns, and preferably between 10 microns and 40 microns; as shown in Figure 4e, using high pressure argon (A) - gas splashing The exposed carbon nanotube layer 122 and the catalytic metal layer 120 are removed, and the thickness of the patterned photoresist layer 124 is reduced to a certain extent. Therefore, the thickness of the patterned photoresist layer 124 must have a certain thickness, preferably a pattern. The thickness of the photoresist layer 124 is more than three times greater than that of the carbon nanotube layer 122; as shown in FIG. 4f < B > 32 1364058 MEGA 06-020TW-P05014, the photo-resist layer 124 is removed. In addition to the lack of nano carbon: 瞢 layer · 122. Below the adhesive barrier layer 118, at this time the Nai. carbon tube layer] 2.2 series appears flat, from the gaze can be round, square or other geometric shape : as shown in FIG. 4g, the same as the cutting-step, the substrate 10 is formed into a Lu.. half-dream wafer 54, each of which has a planar nanocarbon. Tube layer I22. Therefore, the planar carbon nanotube layer 122 of the first aspect of the west embodiment is used as a heat sink, and the carbon nanotubes have good thermal conductivity.

The quality of the heat generated by the semi-conductive wafer 54 (current is over) is quickly removed. The second aspect of the fourth embodiment: Please refer to FIG. 4h, the second embodiment of the fourth embodiment is similar to the first aspect of the fourth embodiment, wherein the difference in structure is in the first aspect. The conductive carbon nanotube layer 122 is disposed on the protective layer 34 and is positioned above the active surface of the substrate 10, and the second aspect of the nanocarbon tube layer 1? 2 is disposed on the substrate 1 Active surface, while nano carbon; tube layer 122-

The advantage of being disposed on the inactive surface of the substrate 1 is that the damage of the protective layer 34 during the manufacturing process of the carbon nanotube layer 122 can be reduced, and the use space on the protective layer 34 is not required, for example, on the protective layer 34. Using a clock, a process, a redistribution layer (RpL), an intereonnection, an inductor, a bump, etc., or as in the first embodiment, The second embodiment and the third embodiment form a reconfigurable line of the nano tube material on the protective layer (Redistribution

Layer,. RD.L), connection line (interconneetioEi), inductance element (inductor) <bump, etc.' are not repeated here. : 33 1364058 MEGA 06-020TW-P05014 The present invention relates to a structure in which a carbon nanotube is applied to a protective layer of a semiconductor: · ( ) (cjveepakiyatioit.sclie.nie) and a thermal structure;营良. : \好:的: Conductive properties, flexibility and: high strength, make the circuit of the conductor element more: Ί

W finer, more dense 'set:, 'and use the high thermal conductivity of carbon nanotubes., so that the semi-conducting element: * heat dissipation is more sturdy. In the above description, the features of the present invention are described by way of example, and the purpose of the present invention is to enable the skilled person to understand the contents of the present invention and to implement it, and not to limit the patent of the present invention. The equivalent modifications or modifications made by G. G. Spirit are not included in the scope of the patent application described below. BRIEF DESCRIPTION OF THE DRAWINGS: The following is a schematic view of a first aspect of the first embodiment of the present invention. . . . 1 to lp are schematic diagrams showing the second aspect of the first embodiment of the present invention

1a to 1w are schematic diagrams showing a third aspect of the second embodiment of the present invention. . . : ' . 2a to 2i are schematic views showing a first aspect of the first pome embodiment of the present invention. . 2j is a schematic view showing a second aspect of the second embodiment of the present invention: . . . 2k to 2nd is a schematic diagram of the second aspect of the second embodiment. Fig. 3a to Fig. 3k are diagrams showing the first aspect of the third embodiment of the present invention. 34 1364058 MEGA 06-020TW-P05014 Fig.: ...Ο:..::..::. . . . Fig. 31/ is a schematic view showing a second aspect of the third embodiment of the present invention. :: 4a to 4g. Fig. 4 is a schematic view showing a first aspect of the fourth embodiment of the present invention, and Fig. 4h is a schematic view showing a second aspect of the fourth embodiment of the present invention. Figure number description

10 _. Substrate 12 Light layer 14 Gold oxide semi-transistor 16 Source 18 Deuterium 20 Blue Pole 22 Fine circuit structure 24 Thin circuit layer 26 Fine circuit dielectric layer 28 Opening 30 Conductive. Plug 32 Pad 34 Protective layer. 36 opening... 38: adhesive barrier layer 40 catalytic metal layer 42 nanocarbon layer. 44 adhesive barrier layer 46 seed layer 48 patterned photoresist layer 50 opening 5.2 metal layer 54 semiconductor wafer 56 wire 58 polymer Layer 60 opening 62 metal pad 64 polymer layer 66 opening 68 pad 70. adhesion barrier layer. 72 catalyst metal layer 74 nanotube. carbon tube. + layer 76. patterned photoresist layer 35 1364058

MEGA 06-020TW-P05014 78 . Opening. 80 82 · Polymer layer 84 86 Adhesive P and barrier layer. 88 90 Patterned photoresist layer 92 94 Metal layer 96 98 Catalyst metal layer 100 102 Adhesion barrier layer 104 106 Patterned photoresist layer 108 110 metal layer 112 114 opening 116 118 adhesion barrier layer 120 122 carbon nanotubes layer 124 126 open polymer layer opening seed layer opening adhesion barrier layer nano silicon tube layer seed layer π . Patterned polymer layer polymer layer catalyst metal. layer patterned photoresist layer cm

36

Claims (1)

1364058 Patent application No. 095143682 Chinese patent application scope #换本(February 101) X. Patent application scope 1. A wafer, including: a substrate; a first transistor disposed on the substrate; a second transistor disposed on the substrate; an insulating layer over the substrate, the insulating layer having a first opening and a second Opening a carbon nanotube line above the insulating layer between the first opening and the second opening, and the carbon nanotube circuit is connected to the first transistor via the first opening and via the second opening Connecting the second transistor; and a metal layer above the insulating layer, and the metal layer is connected to the carbon nanotube circuit. 2. The wafer of claim 1 further comprising a polymer layer above the insulating layer and above the carbon nanotube line. 3. The wafer of claim 1, wherein the metal layer is connected to a wire. 4. The wafer of claim 1, further comprising a voltage stabilizing element disposed on the substrate. 5. The wafer of claim 1, further comprising a transformer element disposed on the substrate. 6. The wafer of claim 1, further comprising a sensing element disposed on the substrate. The wafer of claim 1 further includes a static random access memory cell (SRAM cell) disposed on the substrate. 8. The wafer of claim 1, further comprising a DRAM cell disposed on the substrate. 9. The wafer of claim 1, further comprising a flash memory cell disposed on the substrate. The wafer of claim 1, further comprising a magnetic random access memory (MRAM) unit disposed on the substrate. 1 1. The wafer of claim 1, further comprising a memory cell disposed on the substrate. 12. The wafer of claim 1, further comprising an erasable programmable read only memory unit (EPROM cell) disposed on the substrate. 13. The wafer of claim 1, further comprising a ROM cell disposed on the substrate. 14. The wafer of claim 1, wherein the metal layer has a thickness of between 1 micrometer and 30 micrometers. The wafer of claim 1, wherein the insulating layer comprises silicon nitride having a thickness of between 0.25 micrometers and 1.2 micrometers. The wafer of claim 1, wherein the insulating layer comprises a nitride having a thickness of between 0.2 μm and 1.2 μm. 17. The wafer of claim 1, further comprising an electrostatic discharge protection circuit disposed on the substrate. 18. The wafer of claim 1, wherein the substrate is a substrate. The wafer of claim 1, wherein the substrate is selected from the group consisting of a gallium arsenide substrate, a germanium telluride substrate, or a substrate having an epitaxial germanium on a silicon-on-insulator (SOI). A wafer comprising: a substrate; a transistor disposed on the substrate; and an inductive component on the substrate, and the composition of the inductive component comprises a carbon nanotube. The wafer of claim 20, wherein the inductive component is connected to an external circuit via a wire. 2. The wafer of claim 20, further comprising a polymer layer over the inductive component. 2 3. The wafer of claim 20, further comprising a voltage stabilizing element disposed on the substrate. 2. The wafer of claim 20, further comprising a transformer element disposed on the substrate. 25. The wafer of claim 20, further comprising a sensing element disposed on the substrate of 143034-1010223.doc 1364058. 26. The wafer of claim 20, further comprising a static random access memory cell disposed on the substrate. 27. The wafer of claim 20, further comprising a dynamic random access memory cell disposed on the substrate. 28. The wafer of claim 20, further comprising a flash memory unit disposed on the substrate. 2. The wafer of claim 20, further comprising a magnetic random access memory unit disposed on the substrate. 30. The wafer of claim 20, further comprising a memory unit disposed on the substrate. 31. The wafer of claim 20, further comprising an erasable programmable read only memory unit disposed on the substrate. 3. The wafer of claim 20, further comprising a read-only memory unit disposed on the substrate. 3. The wafer of claim 20, wherein the inductive component is in the form of a coil. The wafer of claim 20, wherein the composition of the inductive component further comprises a catalytic metal. Floor. The wafer of claim 20, further comprising a polymer layer between the substrate and the inductive component. 3. The wafer of claim 20, further comprising an insulating layer between the substrate and the inductive component. 3 7. The wafer of claim 20, further comprising an electrostatic discharge protection circuit disposed on the substrate of 143034-1010223.doc 1364058. 38. The wafer of claim 20, wherein the substrate is a base substrate. The wafer of claim 20, wherein the substrate is selected from the group consisting of a gallium arsenide substrate, a germanium telluride substrate, or a substrate having a silicon-on-insulator (SOI). a wafer comprising: a substrate; a first transistor disposed on the substrate; a first polymer layer on the substrate, the first polymer layer having a first opening; and a A carbon nanotube circuit is disposed above the first polymer layer and the carbon nanotube circuit is connected to the first crystal via the first opening. 4. The wafer of claim 40, further comprising a second transistor disposed on the substrate, and the first polymer has a second opening through which the carbon nanotube circuit is The second port is connected to the second transistor. 42. The wafer of claim 41, wherein the carbon nanotube circuit is located above the first polymer layer between the first opening and the second opening. 43. The wafer of claim 40, further comprising a metal layer over the first polymer layer, the metal layer being bonded to the carbon nanotube circuit. The substrate of the present invention is the same as the wafer of claim 43 wherein the thickness of the metal layer is between 1 micrometer and 1 micrometer. 45. The wafer of claim 40, further comprising a sensing element disposed on the substrate. 4. The wafer of claim 40, further comprising a static random access memory cell disposed on the substrate. 4. The wafer of claim 40, further comprising a dynamic random access memory cell disposed on the substrate. 48. The wafer of claim 40, further comprising a flash memory unit disposed on the substrate. 4. The wafer of claim 40, further comprising a magnetic random access memory unit disposed on the substrate. 50. The wafer of claim 40, further comprising a memory unit disposed on the substrate. 5 1. The wafer of claim 40, further comprising an erasable programmable read only memory unit disposed on the substrate. 52. The wafer of claim 40, further comprising a read-only memory unit disposed on the substrate. 53. The wafer of claim 40, further comprising a second polymer layer above the first polymer layer and on the surface of the nanocarbon pipeline. 54. The wafer of claim 40, further comprising a voltage stabilizing element disposed on the substrate. 55. The wafer of claim 40, further comprising a transformer element disposed on the substrate of 143034-1010223.doc 1364058. 56. The wafer of claim 40, further comprising an electrostatic discharge protection circuit on the substrate. 57. The wafer of claim 40, wherein the wafer is a substrate. 58. The wafer of claim 40, wherein the substrate is selected from the group consisting of a deified substrate, a shredded substrate, or a substrate having a silicon-on-insulator (SOI). 143034-1010223.doc