TWI364041B - Low couple effect bit-line voltage generator and control method thereof - Google Patents

Low couple effect bit-line voltage generator and control method thereof Download PDF

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Publication number
TWI364041B
TWI364041B TW97100909A TW97100909A TWI364041B TW I364041 B TWI364041 B TW I364041B TW 97100909 A TW97100909 A TW 97100909A TW 97100909 A TW97100909 A TW 97100909A TW I364041 B TWI364041 B TW I364041B
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source
transistor
pole
voltage
gate
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TW97100909A
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Chinese (zh)
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TW200931431A (en
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Macronix Int Co Ltd
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1364041 九、發明說明: 【發明所屬之技術領域】 產生=係為-種電壓產生器,尤指—種低輕合效應位元線電壓 【先前技術】 記憶體是電翻來儲存資料和指令的裝置 習用之記憶體位元線電壓產生器之電路圖。該電:【含: ===元車L2 ’用以提供電壓至-記憶體陣列, 其中該電Μ調4 11係連接於該開關單元12, 係連接於該記憶體陣歹13。該電壓調節· u ° =相一R1和R2,其中該運算== ϋ ^ ^電壓vref,非反相輸人端係連接於電 知士帝曰触之間輸出^係連接至該拉高電晶體_之閘極。該 :ph ί源極係接收一電壓vpp ’汲極係連接至_ 端娜: 一端係連接於電阻ri之第二端,而第二 該開?!元12包含一開關電晶體Msw及一箝位電晶體 ΪΓΙΙΪ關電晶體Msw之雜係接收—㈣信號0,汲 該電壓Vpp,源極係連接於該箝位電晶體Με1_之没 ^。該推位電晶體Mclamp之間極係連接於該拉高電晶體_之沒 而源極係連接於該$憶體陣列13之位元線。該箝位電晶體 3有一寄生電容CP,該寄生電容CP係 :電阳體Mph進行預充電(precharse),而經由電阻R1 甘λ β進行放電。該記憶體陣列13係由複數個電晶體131所組成, 其中各電晶體131之閘極係分別連接至一高電壓V[^ 上述之該拉高電晶體Mph、該開關電晶體Msw、該箝位電晶體1364041 IX. Description of the invention: [Technical field of invention] Generation = is a type of voltage generator, especially a low-light effect bit line voltage [Prior Art] Memory is an electric turn to store data and instructions A circuit diagram of a memory bit line voltage generator used by the device. The electric: [including: === the vehicle L2] is used to provide a voltage to the memory array, wherein the electric switch 4 11 is connected to the switch unit 12 and is connected to the memory array 13 . The voltage regulation · u ° = phase one R1 and R2, wherein the operation == ϋ ^ ^ voltage vref, the non-inverting input terminal is connected to the output of the electric singer, and the output is connected to the high-voltage The gate of the crystal _. The :ph ί source receives a voltage vpp ′ 汲 系 连接 连接 _ : : : : : : : : : : : : : : : : : : : : : : : : : : : : : ! The element 12 includes a switching transistor Msw and a clamping transistor of the clamping transistor Msw. - (4) Signal 0, 汲 The voltage Vpp, the source is connected to the clamping transistor Με1_. The push-pull transistor Mclamp is connected to the pull-up transistor and the source is connected to the bit line of the $ memory array 13. The clamp transistor 3 has a parasitic capacitance CP which is precharged by the electrical anode Mph and discharged by the resistor R1 甘λ β. The memory array 13 is composed of a plurality of transistors 131, wherein the gates of the transistors 131 are respectively connected to a high voltage V[^ the above-mentioned pull-up transistor Mph, the switch transistor Msw, the tongs Bit transistor

Claims (1)

1364041 101年3月22日修正替換頁 十、申請專利範園·· 1· 一種位元線電壓產生器,其包含: - 強放電偏壓源,其包含—拉低電晶體,該拉低電晶體之 於該增強放電偏壓源之—輸出端,以提供該增強放電 偏壓源之該輸出端之一放電路徑;及 一開關單元,其包含: 出姓體’其閘極連接於該增強放電偏壓源之該輸 出4,其沒極接收一電壓; 今;晶體’其閑極接收一控制信號,其没極連接於 晶體之源極,其源極連接至—記憶體陣列,其; 柑位電晶體之閘極與源極之間具有一寄生電容. 八〜 端躺電Γ ’其第一端連接於該開關電晶體之及極,其第二 端祕電容,其第—端連接於該開關電晶體之汲極,其第二 進而穩定施加至該記憶體_的驗壓狀間_合效應, =申請專利範圍第!項所述之位 放電偏壓源包含: 电座生盗其中該增強 一相輸入端接收-參考電壓; 一ί:一極體,其陽極連接於該第-二極體之if ; -電饥源,其輸人端連接於二二, 接地; %極’其輪出端 一拉低電晶體,其閘極連接於 接於該電流源之輸出端; 、瓜"、]入蠕,其源極連 極接,其汲 14 101年2月15日修正替換頁 Γ364041 一第一電阻,其第一端連接於該拉高電晶體之源極,其第二 端連接於該運算放大器之反相輸入端;及 一第一電阻’其第一端連接於該運算放大器之反相輸入端, 其第二端接地。 3.如申睛專利範圍第2項所述之位元線電壓產生器,其中該第一 ίϊί、該第二二極體、該電流源、該拉高電晶體、^該拉低電 日日體係構成一AB類輸出級。 料概圍第2項所述之位元線電壓產生器,其中該拉高 電曰曰體之源極逹接於該箝位電晶體之閘極。 圍第1項所述之位猶電壓產生器,其中該增強 一,流源,其輸出端接地; - Git ’ ΐ源極連接於該電流源之輸入端; 流源之輸入端; ’其閘極接收-參考賴’其源極連接於該電 其源其源極,其難接收該電愿, 其馳其源極,奴極接收該電屢, 接收該電4;電明體其閉極連接於該第三電晶體之極,其沒極 電晶;i:s二ί:4連接於其汲極’其汲極連接於該第五 接岐體’相極連接於該第四電晶體之馳,其〉及極 連接讲ί:體=連=第:電晶體,,其_ 端連接於鄕—電晶體之^^於馳高電晶體心原極 ’其第二 15 Γ364041 1〇1年2月15日修正替換頁 端_第二電阻’其第—端連接於該第—電阻之第二端,其第二 t ^申請專利範圍第5項所述之位元線電壓 电曰曰體之源極連接於絲位電晶體之·^ ’其中該拉南 第1項所述之位元線電壓產生器,其中該增強 —電流源,其輸入端接收該電壓; 流源晶體,制極接收—參考龍,其汲極連接於該電 j二電晶體,歧極連接於該電流源之輸出端. 接地1三電晶體’其汲極連接於該第—電晶體之源極,其源極 -第四電晶體,其雜連接於該第 連接於該第二電晶體之源極,其源極接地·篮之間極其及極 ’f雜連接於其源極,歧極接收該電壓; 連接於1極連接於該第三電日日日體之閘極,其汲極 連接於該第五電晶體之源極,其源極接地; 接^電晶體,其間極連接於該第五電晶體之閘極,其汲極 連接祕,其汲極 二耦合電容,連接於該拉低電晶體之閘極與汲極之間; #由二第—電阻’其第—端連接於該拉高電晶體之源極,並第-端連接於該第二電晶體之閘極;及 ,、弟一 端接:第二電阻’其第—端連接於該第—電阻之第二端,其第二 ^如申請專利範圍第7項所述之位元線賴產生器,其中 電Μ體之源極連接於該箝位電晶體之閘極。 。 9·如申請翻翻第1項所述之位元線賴產生器,其中該開關 161364041 March 22, 2011 Revision Replacement Page 10, Patent Application Fan Park··1· A bit line voltage generator comprising: - a strong discharge bias source comprising - pulling a low crystal, the pull low a crystal at the output end of the enhanced discharge bias source to provide a discharge path of the output of the enhanced discharge bias source; and a switching unit comprising: a surname 'the gate is connected to the enhancement The output 4 of the discharge bias source receives a voltage from the pole; now; the crystal 'the idler receives a control signal, the pole is connected to the source of the crystal, and the source is connected to the memory array; There is a parasitic capacitance between the gate and the source of the citrus transistor. Eight~ lie at the end of the transistor. The first end is connected to the parallel pole of the switch transistor, and the second end of the capacitor is connected to the first end. In the drain of the switching transistor, the second and further stable application to the memory__pressure effect_, the patent application scope! The discharge bias source of the present invention comprises: a battery seat thief in which the enhancement one-phase input receives a reference voltage; a ί: a pole body whose anode is connected to the if-dipole body; Source, the input end is connected to the second and second, grounding; the % pole' has a low-voltage transistor pulled out from its wheel end, and its gate is connected to the output end connected to the current source; the melon ",] into the creep, The source is connected to the pole, and the first resistor is replaced by a first resistor, the first end of which is connected to the source of the pull-up transistor, and the second end of which is connected to the opposite of the operational amplifier. a phase input terminal; and a first resistor having a first end connected to the inverting input terminal of the operational amplifier and a second end grounded. 3. The bit line voltage generator according to claim 2, wherein the first voltage, the second diode, the current source, the pull-up transistor, and the low-voltage day The system constitutes an AB class output stage. The bit line voltage generator of item 2, wherein the source of the pull-up electrode body is connected to the gate of the clamp transistor. a voltage generator according to the first item, wherein the enhancement one, the current source, and the output end thereof are grounded; - the Git ' ΐ source is connected to the input end of the current source; the input end of the flow source; The pole receiving-reference 赖's source is connected to the source of the source of the electric source, and it is difficult to receive the electric wish, and its source is connected to the source, the slave receives the electric power repeatedly, receives the electric 4; the electric body has its closed end Connected to the pole of the third transistor, which has no pole crystal; i: s2: 4 is connected to its drain 'the drain is connected to the fifth junction', and the phase is connected to the fourth transistor Chichi, its > and the pole connection speak ί: body = even = the first: the transistor, its _ end is connected to the 鄕-transistor ^ ^ Yu Chi high-crystal crystal card original pole 'the second 15 Γ 364041 1〇1 On February 15th, the replacement page terminal _ second resistor' has its first end connected to the second end of the first resistor, and the second bit is the bit line voltage voltage described in item 5 of the patent application scope. The source of the body is connected to the wire-type transistor, wherein the bit line voltage generator described in the first item, wherein the enhancement-current source, the input end thereof Receiving the voltage; the source crystal, the pole receiving-reference dragon, the drain is connected to the electric diode, and the dipole is connected to the output end of the current source. The grounding 1 tri-crystal 'the drain is connected to the a source of the first transistor, a source-fourth transistor, the impurity is connected to the source connected to the second transistor, and the source is grounded and the basket is extremely connected to the pole a source, the pole receives the voltage; a gate connected to the first pole of the third electric day, the drain is connected to the source of the fifth transistor, and the source is grounded; a crystal having a pole connected to the gate of the fifth transistor, the drain of which is connected, and a drain-two coupling capacitor connected between the gate and the drain of the low-voltage transistor; 'The first end is connected to the source of the pull-up transistor, and the first end is connected to the gate of the second transistor; and, the other end is connected: the second resistor' has its first end connected to the first a second end of the resistor, the second of which is the bit line generator according to claim 7 of the patent application, wherein the electric body The source is connected to the gate of the clamp transistor. . 9. If the application is to turn over the bit line generator according to item 1, wherein the switch 16 1364041 電曰B體之源極係連接至該記憶體陣列之位元線。 10. —種位元線電壓產生器,其包含: 一、^1強放電偏壓源,其包含—拉低電晶體,該拉低電晶h 偏屡該增強放電偏慶源之一輸出端’以提供該增強放電 偏屢源之該輸出端之—放電路徑; 曰跳電 端,賴賊職料偏壓源之該輸出 =開關單元,具有一開關電晶體及一 增強^電纏源與—記憶體陣列之間, 麵接於該 同,電荷在該開關電晶體開啟與糊時幾乎相 、隹而籍^低該關單元與該增強放電偏_之間触人效庫, 進而穩疋%加至該記憶體陣列的偏壓。 σ應 曰tr專利範圍第10項所述之位元線電遷產生与,1中州 電之源_連接魏斷狀位猶。/、中該開 -增強:電:巧原壓產i生,該位元線電壓產生器包含 極連接於該增強ί=之體,該拉低電晶體之一汲 源之該輸出端之-放電路開^!供,增強放電偏麼 電晶體,其閘極連接於該增強放开包$-箝位 體之閘極與職之邮有—寄生電$,該箝位電晶 電;,該增_電==該寄生電容充 經由該增強穩定值時,該寄生電容 晶體其中該增強放電偏壓源包含一第—放電路徑係經過一拉低電 13.如申請專利範圍第丨2項所述 甘士主 閉時,該關電晶體之難電㈣為:該卿電晶體關 17 Γ364041 101年3月22日修正替換頁 14. 如申請專利範圍第12項所述之方法,其中該增強放電偏壓源 之放電路徑包含一第一放電路徑及該第二放電路徑。 15. 如申請專利範圍第14項所述之方法,其中該第二放電路徑係 由一第一電阻及一第二電阻所組成。1364041 The source of the B body is connected to the bit line of the memory array. 10. A bit line voltage generator, comprising: a ^1 strong discharge bias source, comprising: a pull-down transistor, the pull-down transistor h is repeatedly outputting one of the enhanced discharge bias sources 'to provide the enhanced discharge bias source of the output - the discharge path; the jumper end, the output of the bias source of the thief; the switch unit has a switching transistor and an enhanced ^ electric source - between the memory arrays, the surface is connected to the same, and the charge is almost phased when the switch transistor is turned on and the paste is turned on, and the contact between the off-cell and the enhanced discharge bias is stabilized. % is added to the bias of the memory array. The sigma line 曰tr patent range mentioned in item 10 of the bit line is relocated and the source of the Zhongzhou electric source is connected to the Wei-shaped position. /, the opening-enhancement: electricity: the original voltage generator, the bit line voltage generator includes a pole connected to the body of the enhancement, the output of the one of the low-voltage transistors is discharged The circuit is opened, and the discharge is biased to the transistor. The gate is connected to the gate of the enhanced release package $-clamp body and the postal message has - parasitic electricity $, the clamp is electro-crystalline;增电== When the parasitic capacitance is charged through the enhanced stability value, the parasitic capacitance crystal wherein the enhanced discharge bias source comprises a first discharge path is subjected to a pull-down power 13. As recited in claim 2 In the case of the main closure of the Gans, the hard-to-electricity of the transistor (4) is: The Qingdian transistor is closed. Γ 364041. The method of claim 12 is as described in claim 12, wherein the enhanced discharge is biased. The discharge path of the voltage source includes a first discharge path and the second discharge path. 15. The method of claim 14, wherein the second discharge path is comprised of a first resistor and a second resistor. 1818
TW97100909A 2008-01-09 2008-01-09 Low couple effect bit-line voltage generator and control method thereof TWI364041B (en)

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