TWI361025B - Printed circuit board - Google Patents

Printed circuit board Download PDF

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Publication number
TWI361025B
TWI361025B TW96134435A TW96134435A TWI361025B TW I361025 B TWI361025 B TW I361025B TW 96134435 A TW96134435 A TW 96134435A TW 96134435 A TW96134435 A TW 96134435A TW I361025 B TWI361025 B TW I361025B
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TW
Taiwan
Prior art keywords
differential
layer
signal
circuit board
printed circuit
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TW96134435A
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Chinese (zh)
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TW200913814A (en
Inventor
Chien Hung Liu
Shou Kuo Hsu
Yu Chang Pai
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Hon Hai Prec Ind Co Ltd
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Priority to TW96134435A priority Critical patent/TWI361025B/en
Publication of TW200913814A publication Critical patent/TW200913814A/en
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Publication of TWI361025B publication Critical patent/TWI361025B/en

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1361025 1100年U月16日修正^^~| 六、發明說明: 【發明所屬之技術領域】 [0001] 本發明係關於一種印刷電路板,尤指一種可降低串音雜 訊及節省佈線空間之印刷電路板。 【先前技術】 [0002] 串音雜訊係電路板上走線之間、連接線之間,走線與連 接線以及其他電子元件之間由於電磁場干擾而引起之電 磁耦合。習知之印刷電路板佈線方式主要有直角佈線、 45度角佈k、差分佈線、蛇形佈線等。由於差分訊號主 要應用在高速電路設計中,所以高速電路中最關鍵之訊 號都採用差分佈線之方式。 [0003]如圖1所示,為習知一種差分佈線方式之局部佈線圖,在 圖中’訊號層100位於介質層300與介質層400之間,訊 號層200位於介質層400與介質層500之間,介質層3〇〇又 位於訊號層100與參考接地層600之間,介質層500又位 於訊號層200與參考接地層7〇〇之間,差分對120之一正 相位差分線TX +及一負相位差分線TX-同時在訊號層1〇〇 上佈線,另一差分對140之一正相位差分線RX +及一負相 位差分線RX-同時在訊號層1〇〇上‘線^該參考接地層 6〇〇用於為訊號層i 00上之差分線TX+及TX-提供電流回流 路徑’該參考接地層700用於為訊號層200上之差分線 RX+及RX-提供電流回流路徑。 [0004] 但習知差分佈線存在以下之缺陷:每一差分對中之差分 線均佈線在同—訊號層中,該種傳統之佈線方式使得相 鄰兩訊號層中差分對之間不吁避免地存在串音雜訊,容 096134435 表翠編號A_ 第3頁/共10真 1003423111-0 1361025 _ 100年11月16日慘正替换頁 易造成電路之誤動,從而降低整個系統之性能,這是印 刷電路板佈線應該避免之情形。且傳統佈線方式中之參 考接地層為單獨按層佈線,故佔據了一定之佈線空間。 【發明内容】 [0005] 鑒於以上内容,有必要提供一種可降低印刷電路板訊號 間串音雜訊之印刷電路板。 [0006] —種印刷電路板,包括兩訊號層及一介質層,該介質層 位於該兩訊號層之間,該兩訊號層内具有兩差分對,該 兩差分對中之正相位差分線位於該兩訊號層中之一訊號 層内,該兩差分對中之負相位差分線位於該兩訊號層中 之另一訊號層内,該兩差分對之差分線在該兩訊號層内 成交錯式佈線,每一訊號層内位於差分線之兩側還設有 用於提供電流回流路徑之參考接地部。 [0007] 相較習知技術,印刷電路板中之差分對採用該層間交錯 式佈線,可大幅減少差分對間之串音雜訊,有助於改善 訊號傳輸品質、提高整個系統性能。 【實施方式】 [0008] 請參考圖2,本發·明印刷電路板之較佳實施方式包括一第 一訊號層10、一第二訊號層20、一第一介質層30、一第 二介質層40及一第三介質層50。該第一訊號層10位於該 第一介質層30與第二介質層40之間,該第二訊號層20位 於該第二介質層40與第三介質層50之間。 [0009] 該第一訊號層10與該第二訊號層20為相鄰之訊號層,該 兩訊號層内具有複數差分對,如差分對12 (包括一正相 096134435 表單编號A0101 第4頁/共10頁 1003423111-0 1361025 _100年.11月16日修正替換頁 位差分線打+ ' 一負相位差分線TX-)及差分對14 (包括 一正相位差分線RX+、一負相位差分線RX-),其他差分 對未示出’本實施方式僅以上述兩差分對舉例說明,其 他差分對佈線可類推,這裡不再贅述。 [0010] 該差分對12之正相位差分線TX +及差分對14之正相位差分 線*^+位於該第一訊號層10内且其兩側設有參考接地部16 ’該差分對12之負相位差分線TX-及差分對14之負相位差 分線RX-位於該第二訊號層2〇内且其兩側設有參考接地部 22 ’該差分對12之差分線ΤΧ+、τχ-及差分對14之差分線 RX+、RX-在該第一訊號層1〇及第二訊號層2〇内成交錯式 佈線’即該差分對12之正相位差分線ΤΧ +與負相位差分線 ΤΧ-成對角交錯佈線,差分對14之正相位差分線Rx +與負 相位RX-也成對角交錯佈線,並且兩相鄰差分線間距離相 等’亦即差分線TX +與RX+、RX +與TX-、TX-與RX-、Rx 與τχ+之間之垂直距離均相等。其中,該參考接地部16用 於為第一訊號層10上之差分線TX+及RX +提供電流回济 路徑’該參考接地部22用於為第二訊號層20上之差分 T X -及R X -提供電流回流路徑。 [0011] 設該差分線RX+對TX +之串音係數為K21,差分線+ _ TX-之串音係數為K24,差分線RX-對TX +之串音係數^ K31,差分線RX-對TX-之串音係數為K34,則該差分對12 與差分對14之間之串音係數K = (K21-K24)-(K3l~K34) 由於該差分對12之差分線TX+、 TX-及差分對14之差分線 RX+、RX-在該第一訊號層10及第二訊號層20内成正方形 交錯式佈線,即結構上對稱,且串音係數與導線距離之 096134435 表單編號A0101 第5頁/共10頁 1〇〇3423llK〇 1361025 100年11月16日修正替換頁 平方成反比’則易知’ K21=K24及K31=K34,故該差分對 與差分對14之間之串音係數1(理論上等於零,此時串音 雜訊達到最小。 [0012] 採用上述層間交錯式佈線方法,可以大幅減少差分對之 間之串音雜訊,有助於改善訊號傳輸品質,提高整個系 統性能;且該佈線中之參考接地部代替之傳統佈線方式 中之參考接地層,且5玄參考接地層是佈線於訊號層中而 未單獨按層佈線,從而大大節省了印刷電路板之佈線空 間。 .二 [0013] 综上所述,本發明符合發明專利要件,爰依法提出專利 申請。惟,以上所述者僅為本發明之較佳實施方式,舉 凡熟悉本案技藝之人士,在爰依本發明精神所作之等效 修飾或變化,皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0014] 圖1係習知一種印刷電路板之局部佈線圖β [0015] 圖2係本發明印刷電路板之較佳實施方式之局部佈線圖 【主要元件符號說明】 [0016] [習知] [⑻17]訊號層:100、200 [0018] 差分對:120、140 [0019] 介質層:300、400、500 [0020] 正相位差分線:ΤΧ+、RX+ [0021] 參考接地層:600、700 096134435 表單編琥Α0101 第6頁/共10頁 ^03423111-0 1361025 100年.11•月16日核正替換頁 [0022] 負相位差分線:TX-、RX- [0023] [本發明] [0024] 第一訊號層:10 [0025] 差分對:1 2、1 4 [0026] 參考接地部:16、22 [0027] 第二訊號層:20 [0028] 第一介質層:3 0 [0029] 第二介質層:40 [0030] 第三介質層:50 [0031] 正相位差分線:TX+、RX + [0032] 負相位差分線:TX-、RX_ 096134435 表單編號A0101 第7頁/共10頁 1003423111-01361025 1100 U 16th revision ^^~| VI. Description of the invention: [Technical field of invention] [0001] The present invention relates to a printed circuit board, especially to reduce crosstalk noise and save wiring space. A printed circuit board. [Prior Art] [0002] The electromagnetic coupling between the traces of the crosstalk noise on the circuit board, between the connection lines, between the traces and the connection wires, and other electronic components due to electromagnetic field interference. Conventional printed circuit board wiring methods mainly include right angle wiring, 45 degree angle cloth k, differential wiring, serpentine wiring, and the like. Since differential signals are primarily used in high-speed circuit design, the most critical signals in high-speed circuits use differential routing. As shown in FIG. 1 , a partial wiring diagram of a differential wiring method is known. In the figure, the signal layer 100 is located between the dielectric layer 300 and the dielectric layer 400 , and the signal layer 200 is located at the dielectric layer 400 and the dielectric layer 500 . Between the signal layer 100 and the reference ground layer 600, the dielectric layer 500 is located between the signal layer 200 and the reference ground layer 7〇〇, and the differential pair 120 has a positive phase difference line TX+. And a negative phase difference line TX- is simultaneously wired on the signal layer 1 ,, and another differential pair 140 has a positive phase difference line RX + and a negative phase difference line RX- simultaneously on the signal layer 1 ' 'line ^ The reference ground plane 6 is used to provide a current return path for the differential lines TX+ and TX- on the signal layer i 00. The reference ground layer 700 is used to provide a current return path for the differential lines RX+ and RX- on the signal layer 200. . [0004] However, the conventional differential wiring has the following drawbacks: the differential lines in each differential pair are wired in the same-signal layer, and the conventional wiring method avoids avoidance between differential pairs in adjacent two signal layers. There is crosstalk noise in the ground, the capacity of 096134435 table Cui number A_ page 3 / total 10 true 1003423111-0 1361025 _ 100 years of November, the misplaced page is easy to cause the circuit to malfunction, thereby reducing the performance of the entire system, which This is the case where printed circuit board wiring should be avoided. Moreover, the reference ground layer in the conventional wiring method is separately layer-by-layer wiring, so it occupies a certain wiring space. SUMMARY OF THE INVENTION [0005] In view of the above, it is necessary to provide a printed circuit board that can reduce crosstalk noise between printed circuit board signals. [0006] A printed circuit board comprising a two signal layer and a dielectric layer, the dielectric layer being located between the two signal layers, the two signal layers having two differential pairs, wherein the positive phase difference lines of the two differential pairs are located In one of the two signal layers, the negative phase difference line of the two differential pairs is located in another signal layer of the two signal layers, and the difference lines of the two differential pairs are interlaced in the two signal layers. Wiring, each of the signal layers is located on both sides of the differential line and is provided with a reference ground for providing a current return path. [0007] Compared with the prior art, the differential pair in the printed circuit board adopts the interlayer interleaved wiring, which can greatly reduce the crosstalk noise between the differential pairs, thereby improving the signal transmission quality and improving the overall system performance. [0008] Referring to FIG. 2, a preferred embodiment of the printed circuit board includes a first signal layer 10, a second signal layer 20, a first dielectric layer 30, and a second medium. Layer 40 and a third dielectric layer 50. The first signal layer 10 is located between the first dielectric layer 30 and the second dielectric layer 40, and the second signal layer 20 is located between the second dielectric layer 40 and the third dielectric layer 50. [0009] The first signal layer 10 and the second signal layer 20 are adjacent signal layers, and the two signal layers have complex differential pairs, such as a differential pair 12 (including a positive phase 096134435, form number A0101, page 4). / Total 10 pages 1003423111-0 1361025 _100 years. November 16 correction replacement page bit differential line + 'one negative phase difference line TX-) and differential pair 14 (including a positive phase difference line RX+, a negative phase difference line RX-), other differential pairs are not shown. This embodiment is exemplified only by the above two differential pairs, and other differential pair wirings can be analogized, and details are not described herein again. [0010] The positive phase difference line TX+ of the differential pair 12 and the positive phase difference line *^+ of the differential pair 14 are located in the first signal layer 10 and are provided with reference ground portions 16' on both sides thereof. The negative phase difference line TX- and the negative phase difference line RX- of the differential pair 14 are located in the second signal layer 2〇 and are provided on both sides thereof with a reference ground portion 22'. The differential line 该+, τχ- of the differential pair 12 The differential lines RX+, RX- of the differential pair 14 are interleaved in the first signal layer 1〇 and the second signal layer 2〇, ie, the positive phase difference line ΤΧ + and the negative phase difference line 该 of the differential pair 12 Diagonally staggered wiring, the positive phase difference line Rx + of the differential pair 14 and the negative phase RX- are also diagonally staggered, and the distance between two adjacent differential lines is equal 'that is, the differential lines TX + and RX+, RX + and The vertical distance between TX-, TX- and RX-, Rx and τχ+ is equal. The reference ground portion 16 is configured to provide a current return path for the differential lines TX+ and RX+ on the first signal layer 10. The reference ground portion 22 is used for the differential TX- and RX on the second signal layer 20. Provides a current return path. [0011] It is assumed that the crosstalk coefficient of the difference line RX+ to TX+ is K21, the crosstalk coefficient of the differential line +_TX- is K24, the crosstalk coefficient of the differential line RX-pair TX+^ K31, the differential line RX-pair The crosstalk coefficient of TX- is K34, then the crosstalk coefficient between the differential pair 12 and the differential pair 14 is K = (K21-K24) - (K3l ~ K34). Because of the differential line TX+, TX- and The differential lines RX+, RX- of the differential pair 14 are square-interleaved in the first signal layer 10 and the second signal layer 20, that is, structurally symmetric, and the crosstalk coefficient and the wire distance are 096134435. Form No. A0101 Page 5 / Total 10 pages 1 〇〇 3243llK 〇 1361025 On November 16th, 100, the replacement page is inversely proportional to the square 'is easy to know' K21=K24 and K31=K34, so the crosstalk between the differential pair and the differential pair 14 (There is theoretically equal to zero, at which time the crosstalk noise is minimized. [0012] By using the inter-layer interleaved wiring method described above, crosstalk noise between differential pairs can be greatly reduced, which contributes to improved signal transmission quality and overall system performance. And the reference grounding portion of the wiring replaces the reference ground layer in the conventional wiring manner, and the 5 reference ground is grounded It is wired in the signal layer and not separately layered, which greatly saves the wiring space of the printed circuit board. [0013] In summary, the present invention complies with the invention patent requirements, and patents are filed according to law. The present invention is only a preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. 1 is a partial wiring diagram of a printed circuit board. [0015] FIG. 2 is a partial wiring diagram of a preferred embodiment of the printed circuit board of the present invention. [Main component symbol description] [0016] [(8)17] Signal layer: 100, 200 [0018] Differential pair: 120, 140 [0019] Dielectric layer: 300, 400, 500 [0020] Positive phase difference line: ΤΧ+, RX+ [0021] Reference ground plane: 600 , 700 096134435 Form Α Α 0101 Page 6 / Total 10 pages ^ 03423111-0 1361025 100 years. 11 • 16th nuclear replacement page [0022] Negative phase difference line: TX-, RX- [0023] [The present invention [0024] First signal layer: 10 [0025] Differential pair: 1 2 1 4 [0026] Reference ground: 16, 22 [0027] Second signal layer: 20 [0028] First dielectric layer: 3 0 [0029] Second dielectric layer: 40 [0030] Third dielectric layer: 50 [ 0031] Positive phase difference line: TX+, RX + [0032] Negative phase difference line: TX-, RX_ 096134435 Form number A0101 Page 7 / Total 10 pages 1003423111-0

Claims (1)

1361025 100年11月16日核正替换頁 七、申請專利範圍: 1 . 一種印刷電路板,包括兩訊號層及一介質層,該介質層位 於該兩訊號層之間,其改良在於:該兩訊號層内具有兩差 分對,該兩差分對中之正相位差分線位於該兩訊號層中之 一訊號層内,該兩差分對中之負相位差分線位於該兩訊號 層中之另一訊號層内,該兩差分對之差分線在該兩訊號層 内成交錯式佈線,每一訊號層内位於差分線之兩側還設有 用於提供電流回流路徑之參考接地部。 2 .如申請專利範圍第1項所述之印刷電路板,其中該兩差分 對中相鄰兩差分線間距離相等。 096134435 表單编號A0101 第8頁/共10頁 1003423111-01361025 November 16th, 100th, the replacement page VII, the scope of the patent application: 1. A printed circuit board comprising two signal layers and a dielectric layer, the dielectric layer is located between the two signal layers, the improvement is: the two The signal layer has two differential pairs. The positive phase difference line of the two differential pairs is located in one of the two signal layers, and the negative phase difference line of the two differential pairs is located in the other signal layer. In the layer, the differential lines of the two differential pairs are interleaved in the two signal layers, and a reference ground portion for providing a current return path is disposed on each side of the differential layer in each signal layer. 2. The printed circuit board of claim 1, wherein the distance between two adjacent differential lines of the two differential pairs is equal. 096134435 Form No. A0101 Page 8 of 10 1003423111-0
TW96134435A 2007-09-14 2007-09-14 Printed circuit board TWI361025B (en)

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