1360947 六、發明說明： 【發明所屬之技術領域】 本發明係關於輸出缓衝器，特別是關於具有迴轉率 (slew-rate)提升輸出級電路之輸出緩衝器。 【先前技術】 在傳統運算放大器中，通常藉由增加電流或減少補償 電容來提升運算放大器之迴轉率。若使用運算放大器來驅 動液晶顯示面板中之晝素，則唯一提升迴轉率之方法就是 增加驅動電流。然而，增加電流會消耗靜態電流並降低運 算放大器之穩定度。 【發明内容】 本發明提供一種迴轉率提升輸出級電路，包括一第一 迴轉率提升電路、一第二迴轉率提升電路、一第一 PMOS 電晶體以及一第一 NMOS電晶體。第一迴轉率提升電路用 以接收一第一控制電壓並且輸出一第一電壓。第二迴轉率 提升電路用以接收一第二控制電壓並且輸出一第二電壓。 第一 PMOS電晶體具有一第一第一端耦接至一高電源電 壓，一第一控制端用以接收第一電壓，以及一第一第二端 耦接至一電壓輸出端。第一 NMOS電晶體具有一第二第一 端耦接至電壓輸出端，一第二控制端用以接收第二電壓， 以及一第二第二端耦接至一低電源電壓，其中第一電壓高 於第一控制電壓，並且第二電壓低於第二控制電壓。 1360947 本發明提供一種具有迴轉率提升輸出級電路之輸出緩 衝器，包括一運算放大器、一第一 PMOS電晶體、一第一 NMOS電晶體、一第一迴轉率提升電路、一第二迴轉率提 升電路、一第二PMOS電晶體以及一第二NMOS電晶體。 運算放大器具有一正輸入端用以接收一輸入電壓，一負輸 入端用以接收一輸出電壓，以及一輸出端用以輸出輸出電 壓。第一 PMOS電晶體具有一第一第一端耦接至一高電源 電壓，一第一控制端耦接至運算放大器中之一第一節點， φ 以及一第一第二端耦接至運算放大器之輸出端。第一 NM0S電晶體具有一第二第一端耦接至運算放大器之輸出 端，一第二控制端耦接至運算放大器中之一第二節點，以 及一第二第二端耦接至一低電源電壓。第一迴轉率提升電 路耦接至第一節點並且輸出一第一電壓。第二迴轉率提升 電路耦接至第二節點並且輸出一第二電壓。第二PMOS電 晶體具有一第三第一端耦接至高電源電壓，一第三控制端 用以接收第一電壓，以及一第三第二端耦接至運算放大器 • 之輸出端。第二NM0S電晶體具有一第四第一端耦接至運 算放大器之輸出端，一第四控制端用以接收第二電壓，以 及一第四第二端耦接至低電源電壓。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 5 1360947 第1圖係為本發明實施例之具有迴轉率（slew_rate)提升 輸出級電路之輸出緩衝器的示意圖。迴轉率提升輸出級電 路12用以提升輸出緩衝器1丨之迴轉率。輸出緩衝器n包 括一運算放大态13、一 PMOS電晶體pi以及一 NM〇s電 晶體N卜運具放大器13包括兩個輸入端與一輸出端，其 中一個輸入端接收輸入電壓Vin，而另一個輸入端接收由 輸出端所輸出之輸出電壓V噴。迴轉率提升輸出級電路 包括-第-迴轉率提升電路14、—第二迴轉率提升 15、一 PMOS電晶體P2以及_ NM〇s電晶體N2。第 顯示運算放大器13於一實施例中之節點c與節點 ： 態。當輸入電壓Vin急速上升時，節點c與節點A上<番 壓準位會急速下降。PMOS電b曰曰體P20而導通使得高^ 電墨VDD對輸出電壓V_充電，直到輸出電壓％ : 輸入電壓Vin為止。 於 當輸入電壓Vin急速下降時，節點D與節點B 壓準位會急速上升。蘭0S電晶體N2因而導通使得^ 電壓v_被放電，直到輪出電壓ν_等於輸入電壓出 ί止。當輸出電壓V_等於輸入電壓Vin時(即輸出J $ 11處於-穩定狀態）’第—迴轉率提升電路14將節~ 之電壓準位控制為高電源電壓VDD，並且第二迴轉接Λ 電路15將―點Β之電$準位控制為低電源電壓vss。外 PMOS電晶體p2與NM〇s電晶體N2皆完全關閉广 传靜態電流不會流過pM〇s電晶體p2與丽〇§電晶體^ ^在不具有迴轉率提升輪出級電路12之傳統設計中，。 於係使用PM〇S電晶體ρ1與NMOS電晶體N1來提供夫^ 惠 1360947 電流以便快速地將輸出電壓Vout充電或放電，因此必須增 加PMOS電晶體P1與NMOS電晶體N1之尺寸與長寬比 (W/L ratio)。當節點C或節點D變穩定時，PMOS電晶體 P1與NMOS電晶體N1仍然會導致靜態功率消耗，使得輸 出緩衝器11的效能降低。舉例而言，假設高電源電壓VDD 為18伏特(V)，當輸出電壓Vout變穩定時，節點C之電壓 準位約為15伏特，PMOS電晶體P1會稍微導通使得靜態 電流流過PMOS電晶體P1，而產生靜態電流就會導致靜態 φ 功率消耗。參考本發明第1圖，如圖所示，是由PMOS電 晶體P2而不是PMOS電晶體P1來提供大量電流以便將輸 出電壓Vout充電。因此，PMOS電晶體P1之尺寸可被縮 減。同樣地，NMOS電晶體N1之尺寸也可被縮減。 在第1圖中，PMOS電晶體P2與NMOS電晶體N2在 輸出電壓Vout變穩定時皆為關閉狀態。由於PMOS電.晶體 P1與NMOS電晶體N1具有較小的尺寸，因此減少了流過 PMOS電晶體P1與NMOS電晶體N1之靜態電流，也因此 • 減少由PMOS電晶體P1與NMOS電晶體N1所導致的靜態 功率消耗。1360947 VI. Description of the Invention: [Technical Field] The present invention relates to an output buffer, and more particularly to an output buffer having a slew-rate boost output stage circuit. [Prior Art] In a conventional operational amplifier, the slew rate of an operational amplifier is usually increased by increasing a current or reducing a compensation capacitor. If an op amp is used to drive the pixels in the LCD panel, the only way to increase the slew rate is to increase the drive current. However, increasing the current consumes quiescent current and reduces the stability of the op amp. SUMMARY OF THE INVENTION The present invention provides a slew rate boost output stage circuit including a first slew rate boosting circuit, a second slew rate boosting circuit, a first PMOS transistor, and a first NMOS transistor. The first slew rate boosting circuit is operative to receive a first control voltage and output a first voltage. The second slew rate boosting circuit is configured to receive a second control voltage and output a second voltage. The first PMOS transistor has a first first terminal coupled to a high power supply voltage, a first control terminal for receiving the first voltage, and a first second terminal coupled to a voltage output terminal. The first NMOS transistor has a second first end coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second end coupled to a low power supply voltage, wherein the first voltage is Higher than the first control voltage and the second voltage is lower than the second control voltage. 1360947 The present invention provides an output buffer having a slew rate boost output stage circuit, including an operational amplifier, a first PMOS transistor, a first NMOS transistor, a first slew rate boost circuit, and a second slew rate boost a circuit, a second PMOS transistor, and a second NMOS transistor. The operational amplifier has a positive input for receiving an input voltage, a negative input for receiving an output voltage, and an output for outputting an output voltage. The first PMOS transistor has a first first end coupled to a high supply voltage, a first control end coupled to one of the first nodes of the operational amplifier, and φ and a first second end coupled to the operational amplifier The output. The first NMOS transistor has a second first end coupled to the output of the operational amplifier, a second control end coupled to the second node of the operational amplifier, and a second second end coupled to the low voltage. The first slew rate boosting circuit is coupled to the first node and outputs a first voltage. The second slew rate boosting circuit is coupled to the second node and outputs a second voltage. The second PMOS transistor has a third first terminal coupled to the high supply voltage, a third control terminal for receiving the first voltage, and a third second terminal coupled to the output of the operational amplifier. The second NMOS transistor has a fourth first terminal coupled to the output of the operational amplifier, a fourth control terminal for receiving the second voltage, and a fourth second terminal coupled to the low supply voltage. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; It is a schematic diagram of an output buffer having a slew rate (slew_rate) boost output stage circuit in accordance with an embodiment of the present invention. The slew rate boost output stage circuit 12 is used to increase the slew rate of the output buffer 1丨. The output buffer n includes an operational amplification state 13, a PMOS transistor pi, and an NM〇s transistor. The amplifier amplifier 13 includes two input terminals and an output terminal, wherein one input terminal receives the input voltage Vin, and the other An input receives the output voltage V spray outputted by the output. The slew rate boosting output stage circuit includes a -th swing rate boosting circuit 14, - a second slew rate boost 15, a PMOS transistor P2, and a _ NM 〇s transistor N2. The first display of the operational amplifier 13 in one embodiment is a node c and a node: state. When the input voltage Vin rises rapidly, the <pressure level on node c and node A will drop rapidly. The PMOS battery B is turned on so that the high voltage VDD charges the output voltage V_ until the output voltage % : the input voltage Vin. When the input voltage Vin drops rapidly, the pressure levels of the node D and the node B will rise rapidly. The blue 0S transistor N2 is thus turned on so that the voltage v_ is discharged until the turn-off voltage ν_ is equal to the input voltage. When the output voltage V_ is equal to the input voltage Vin (ie, the output J $11 is in a - steady state), the first-turn rate boosting circuit 14 controls the voltage level of the node to a high power supply voltage VDD, and the second rotary interface circuit 15 Control the power level of the point to the low power supply voltage vss. The external PMOS transistor p2 and the NM〇s transistor N2 are both completely turned off. The quiescent current does not flow through the pM〇s transistor p2 and the 〇 电 transistor ^ ^ in the conventional circuit without the slew rate boosting wheel output circuit 12 designing,. The system uses PM〇S transistor ρ1 and NMOS transistor N1 to provide the current of 1360947 to quickly charge or discharge the output voltage Vout, so the size and aspect ratio of the PMOS transistor P1 and the NMOS transistor N1 must be increased. (W/L ratio). When the node C or the node D becomes stable, the PMOS transistor P1 and the NMOS transistor N1 still cause static power consumption, so that the performance of the output buffer 11 is lowered. For example, assuming a high supply voltage VDD of 18 volts (V), when the output voltage Vout becomes stable, the voltage level of node C is about 15 volts, and the PMOS transistor P1 is slightly turned on so that quiescent current flows through the PMOS transistor. P1, and the generation of quiescent current results in static φ power consumption. Referring to Fig. 1 of the present invention, as shown, a large amount of current is supplied from the PMOS transistor P2 instead of the PMOS transistor P1 to charge the output voltage Vout. Therefore, the size of the PMOS transistor P1 can be reduced. Similarly, the size of the NMOS transistor N1 can also be reduced. In Fig. 1, the PMOS transistor P2 and the NMOS transistor N2 are both turned off when the output voltage Vout becomes stable. Since the PMOS transistor P1 and the NMOS transistor N1 have a small size, the quiescent current flowing through the PMOS transistor P1 and the NMOS transistor N1 is reduced, and thus the PMOS transistor P1 and the NMOS transistor N1 are reduced. The resulting static power consumption.
第3圖係為本發明實施例之第一迴轉率提升電路14的 示意圖。PMOS電晶體P21具有一源極耦接至高電源電壓 VDD、一閘極以及一汲極耦接至其閘極。PMOS電晶體P22 之源極、汲極與閘極务別耦接至PMOS電晶體P21之汲極、 節點C1與節點C。NMOS電晶體N22之汲極、閘極與源 極分別耦接至節點A、節點C1與低電源電壓VSS。當輸入 電壓Vin上升時，節點C之電壓準位會下降因而將PMOS 7 1360947 電晶體P22導通，並且節點Cl之電壓準位會上升用以將 NMOS電晶體N22導通。當NMOS電晶體N22導通時， 節點A之電壓準位會高於節點C之電壓準位。值得注意的 是，可將PMOS電晶體P2卜PMOS電晶體P23以及NMOS 電晶體N21視為一電流源。 以下將配合第4圖做進一步的說明。第4圖係顯示第3 圖中之節點C、C1以及A的電壓變化。節點C之初始電壓 準位為電壓VI，而PMOS電晶體P22會隨著節點C之電 壓準位的漸漸下降而導通。熟知本領域技藝者應能了解， PMOS電晶體P22之導通程度（conductivity)係由PMOS電 晶體P22之閘極電壓所決定。因此，PMOS電晶體P22也 會漸漸導通，並且節點C1之電壓準位會受到高電源電壓 VDD的影響而上升。NMOS電晶體N22會隨著節點C1之 電壓準位的漸漸上升而導通。熟知本領域技藝者應能了 解，NMOS電晶體N22之導通程度係由NMOS電晶體N22 之閘極電壓所決定。因此，NMOS電晶體N22也會漸漸導 通，並且節點A之電壓準位會受到低電源電壓VSS的影響 而下降。 當節點C之電壓準位開始上升時，流過PMOS電晶體 P22之電流會減少，使得節點C1之電壓準位下降。NMOS 電晶體N22會隨著節點Cl之電壓準位的下降而漸漸關 閉，並且節點A之電壓準位會受到高電源電壓VDD的影 響而上升。在本實施例_，當第一迴轉率提升電路14處於 穩定狀態時，節點C與節點A之電壓準位分別為電壓VI 與電壓V2。此外，電壓V2係高於電壓VI以便確保第1 1360947 圖中之PMOS電晶體P2可被完全關閉用以消除靜態電流。 第5圖係為本發明實施例之第二迴轉率提升電路15的 示意圖。PMOS電晶體P41之源極耦接至高電源電壓 VDD，PMOS電晶體P41之閘極與汲極耦接至節點D1與 PMOS電晶體P42之閘極。NMOS電晶體N43之閘極耦接 至第1圖中之節點D，其汲極耦接至節點D1，其源極耦接 至NMOS電晶體N41之汲極與閘極。NMOS電晶體N41 與N42之源極耦接至低電源電壓VSS。PMOS電晶體P42 φ 之源極與汲極分別耦接至高電源電壓VDD與節點B。 NMOS電晶體N42之汲極與閘極亦耦接至節點B。當輸入 電壓Vin下降時，節點D之電壓準位會上升因而將NMOS 電晶體N43導通，並且節點D1之電壓準位會下降用以將 PMOS電晶體P42導通。當PMOS電晶體P42導通時，節 點B之電壓準位會低於節點D之電壓準位。值得注意的 是，可將PMOS電晶體P41、PMOS電晶體P42以及NMOS 電晶體N41視為一電流源。 鲁 以下將配合第6圖做進一步的說明。第6圖係顯示第5Figure 3 is a schematic diagram of a first slew rate boosting circuit 14 in accordance with an embodiment of the present invention. The PMOS transistor P21 has a source coupled to the high supply voltage VDD, a gate, and a drain coupled to the gate thereof. The source, the drain and the gate of the PMOS transistor P22 are coupled to the drain of the PMOS transistor P21, the node C1 and the node C. The drain, gate and source of the NMOS transistor N22 are coupled to the node A, the node C1 and the low supply voltage VSS, respectively. When the input voltage Vin rises, the voltage level of the node C drops, thereby turning on the PMOS 7 1360947 transistor P22, and the voltage level of the node C1 rises to turn on the NMOS transistor N22. When the NMOS transistor N22 is turned on, the voltage level of the node A is higher than the voltage level of the node C. It is to be noted that the PMOS transistor P2, the PMOS transistor P23, and the NMOS transistor N21 can be regarded as a current source. The following will be further explained in conjunction with Figure 4. Figure 4 shows the voltage changes of nodes C, C1, and A in Figure 3. The initial voltage level of the node C is the voltage VI, and the PMOS transistor P22 is turned on as the voltage level of the node C gradually decreases. It will be appreciated by those skilled in the art that the conductance of the PMOS transistor P22 is determined by the gate voltage of the PMOS transistor P22. Therefore, the PMOS transistor P22 is also gradually turned on, and the voltage level of the node C1 is increased by the influence of the high power supply voltage VDD. The NMOS transistor N22 is turned on as the voltage level of the node C1 gradually rises. It will be understood by those skilled in the art that the degree of conduction of the NMOS transistor N22 is determined by the gate voltage of the NMOS transistor N22. Therefore, the NMOS transistor N22 is also gradually turned on, and the voltage level of the node A is lowered by the low power supply voltage VSS. When the voltage level of the node C starts to rise, the current flowing through the PMOS transistor P22 decreases, causing the voltage level of the node C1 to drop. The NMOS transistor N22 gradually turns off as the voltage level of the node C1 decreases, and the voltage level of the node A rises due to the influence of the high power supply voltage VDD. In the present embodiment, when the first slew rate boosting circuit 14 is in a steady state, the voltage levels of the node C and the node A are voltage VI and voltage V2, respectively. In addition, voltage V2 is higher than voltage VI to ensure that PMOS transistor P2 in Figure 136047 can be completely turned off to eliminate quiescent current. Fig. 5 is a schematic view showing the second slew rate improving circuit 15 of the embodiment of the present invention. The source of the PMOS transistor P41 is coupled to the high power supply voltage VDD, and the gate and the drain of the PMOS transistor P41 are coupled to the gates of the node D1 and the PMOS transistor P42. The gate of the NMOS transistor N43 is coupled to the node D in FIG. 1, the drain is coupled to the node D1, and the source thereof is coupled to the drain and the gate of the NMOS transistor N41. The sources of the NMOS transistors N41 and N42 are coupled to the low supply voltage VSS. The source and the drain of the PMOS transistor P42 φ are respectively coupled to the high power supply voltage VDD and the node B. The drain and gate of the NMOS transistor N42 are also coupled to the node B. When the input voltage Vin drops, the voltage level of the node D rises, thereby turning on the NMOS transistor N43, and the voltage level of the node D1 is lowered to turn on the PMOS transistor P42. When the PMOS transistor P42 is turned on, the voltage level of the node B will be lower than the voltage level of the node D. It is worth noting that the PMOS transistor P41, the PMOS transistor P42, and the NMOS transistor N41 can be regarded as a current source. Lu will be further explained in conjunction with Figure 6. Figure 6 shows the 5th
圖中之節點D、D1以及B的電壓變化。節點D之初始電 壓準位為電壓V3，而NMOS電晶體N43會隨著節點D之 電壓準位的漸漸上升而導通。熟知本領域技藝者應能了 解，NMOS電晶體之導通程度係由NMOS電晶體之閘極電 壓所決定。因此，NMOS電晶體N43也會漸漸導通，並且 節點D1之電壓準位會受到低電源電壓VSS的影響而下 降。PMOS電晶體P42會隨著節點D1之電壓準位的漸漸下 降而導通。熟知本領域技藝者應能了解，NMOS或PMOS 9 1360947 電晶體之導通程度係由NMOS或PMOS電晶體之閘極電壓 所決定。因此，PMOS電晶體P42也會漸漸導通，並且節 點B之電壓準位會受到高電源電壓VDD的影響而上升。 當節點D之電壓準位開始下降時，流過NMOS電晶體 N43之電流會減少，使得節點D1之電壓準位上升。PMOS 電晶體P42會隨著節點D1之電壓準位的上升而漸漸關 閉，由於流過PMOS電晶體P42之電流減少，節點B之電 壓準位因此下降。在本實施例中，當第二迴轉率提升電路 15處於穩定狀態時，節點D與節點B之電壓準位分別為電 壓V3與電壓V4。此外，電壓V4係低於電壓V3以便確保 第1圖中之NMOS電晶體N2可被完全關閉用以消除靜態 電流。 如前文所述，可藉由將驅動電晶體完全關閉來減少靜 態電流所導致之功率消耗。如第1圖所示，PMOS電晶體 P2與NMOS電晶體N2係為驅動電晶體。電晶體之導通程 度係由電晶體之閘極電壓所決定。因此，第一迴轉率提升 電路14與第二迴轉率提升電路15可確保PMOS電晶體P2 與NMOS電晶體N2被完全關閉。The voltage changes of nodes D, D1, and B in the figure. The initial voltage level of the node D is the voltage V3, and the NMOS transistor N43 is turned on as the voltage level of the node D gradually rises. It will be appreciated by those skilled in the art that the degree of conduction of the NMOS transistor is determined by the gate voltage of the NMOS transistor. Therefore, the NMOS transistor N43 is also gradually turned on, and the voltage level of the node D1 is lowered by the low power supply voltage VSS. The PMOS transistor P42 is turned on as the voltage level of the node D1 gradually decreases. Those skilled in the art will appreciate that the degree of conduction of an NMOS or PMOS 9 1360947 transistor is determined by the gate voltage of the NMOS or PMOS transistor. Therefore, the PMOS transistor P42 is also gradually turned on, and the voltage level of the node B is increased by the influence of the high power supply voltage VDD. When the voltage level of the node D begins to decrease, the current flowing through the NMOS transistor N43 decreases, causing the voltage level of the node D1 to rise. The PMOS transistor P42 gradually turns off as the voltage level of the node D1 rises. As the current flowing through the PMOS transistor P42 decreases, the voltage level of the node B decreases. In this embodiment, when the second slew rate boosting circuit 15 is in a steady state, the voltage levels of the node D and the node B are voltage V3 and voltage V4, respectively. Further, the voltage V4 is lower than the voltage V3 to ensure that the NMOS transistor N2 in Fig. 1 can be completely turned off to eliminate the quiescent current. As mentioned earlier, the power consumption due to the static current can be reduced by completely turning off the drive transistor. As shown in Fig. 1, the PMOS transistor P2 and the NMOS transistor N2 are driving transistors. The conductivity of the transistor is determined by the gate voltage of the transistor. Therefore, the first slew rate boosting circuit 14 and the second slew rate boosting circuit 15 can ensure that the PMOS transistor P2 and the NMOS transistor N2 are completely turned off.
第7圖係為本發明實施例之具有迴轉率提升輸出級電 路之輸出緩衝器的電路圖。PMOS電晶體P1之源極、閘極 與汲極分別耦接至高電源電壓VDD、節點C與運算放大器 61之輸出端。NMOS電晶體N1之汲極、閘極與源極分別 耦接至運算放大器61之輸出端、節點D與低電源電壓 VSS。PMOS電晶體P2之源極、閘極與汲極分別耦接至高 電源電壓VDD、節點A與運算放大器61之輸出端。NMOS 1360947 電晶體N2之汲極、閘極與源極分別耦接至運算放大器61 之輸出端、節點B與低電源電壓V S S。 PMOS電晶體P21具有一源極耦接至高電源電壓 VDD、一閘極以及一汲極耦接至其閘極。PMOS電晶體P22 之源極、汲極與閘極分別耦接至PMOS電晶體P21之汲極、 節點C1與節點C。NMOS電晶體N22之汲極、閘極與源 極分別耦接至節點A、節點C1與低電源電壓VSS。當輸入 電壓Vin上升時，節點C之電壓準位會下降因而將PMOS ❿ 電晶體P22導通，並且節點C1之電壓準位會上升用以將 NMOS電晶體N22導通。當NMOS電晶體N22導通時， 節點A之電壓準位會下降。 PMOS電晶體P41之源極耦接至高電源電壓VDD， PMOS電晶體P41之閘極與汲極耦接至節點D1與PMOS 電晶體P42之閘極。NMOS電晶體N43之閘極耦接至第1 圖中之節點D，其汲極耦接至節點Dl·，其源極耦接至NMOS 電晶體N41之汲極與閘極。NMOS電晶體N41與N42之源 • 極耦接至低電源電壓VSS。PMOS電晶體P42之源極與汲 極分別耦接至高電源電壓VDD與節點B。NMOS電晶體 N42之汲極與閘極亦耦接至節點B。當輸入電壓Vin下降 時，節點D之電壓準位會上升因而將NMOS電晶體N43 導通，並且節點D1之電壓準位會下降用以將PMOS電晶 體P42導通。當PMOS電晶體P42導通時，節點B之電壓 準位會上升。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟知技藝者，在不脫離本發明之精神和 1360947 範圍内，當可作些許更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 1360947 【圖式簡單說明】 第1圖係為本發明實施例之具有迴轉率提升輸出級電 路之輸出缓衝器的示意圖； 第2圖顯示運算放大器於一實施例中之節點C與節點 D的狀態； 第3圖係為本發明實施例之第一迴轉率提升電路的示 意圖； 第4圖係顯示第3圖中之節點C、C1以及A的電壓變 化； 第5圖係為本發明實施例之第二迴轉率提升電路的示 意圖； 第6圖係顯示第5圖中之節點D、D1以及B的電壓變 化； 第7圖係為本發明實施例之具有迴轉率提升輸出級電 路之輸出缓衝器的電路圖。 .【主要元件符號說明】 11〜輸出緩衝器； 12〜迴轉率提升輸出級電路； 13〜運算放大器； 14〜第一迴轉率提升電路； 15〜第二迴轉率提升電路；Figure 7 is a circuit diagram of an output buffer having a slew rate boost output stage circuit in accordance with an embodiment of the present invention. The source, gate and drain of the PMOS transistor P1 are coupled to the high supply voltage VDD, the node C and the output of the operational amplifier 61, respectively. The drain, gate and source of the NMOS transistor N1 are coupled to the output of the operational amplifier 61, the node D and the low supply voltage VSS, respectively. The source, gate and drain of the PMOS transistor P2 are respectively coupled to the high supply voltage VDD, the node A and the output of the operational amplifier 61. The drain, gate and source of the NMOS 1360947 transistor N2 are respectively coupled to the output of the operational amplifier 61, the node B and the low supply voltage V S S . The PMOS transistor P21 has a source coupled to the high supply voltage VDD, a gate, and a drain coupled to the gate thereof. The source, the drain and the gate of the PMOS transistor P22 are respectively coupled to the drain of the PMOS transistor P21, the node C1 and the node C. The drain, gate and source of the NMOS transistor N22 are coupled to the node A, the node C1 and the low supply voltage VSS, respectively. When the input voltage Vin rises, the voltage level of the node C drops, thereby turning on the PMOS transistor P22, and the voltage level of the node C1 rises to turn on the NMOS transistor N22. When the NMOS transistor N22 is turned on, the voltage level of the node A drops. The source of the PMOS transistor P41 is coupled to the high power supply voltage VDD, and the gate and the drain of the PMOS transistor P41 are coupled to the gates of the node D1 and the PMOS transistor P42. The gate of the NMOS transistor N43 is coupled to the node D in FIG. 1 , the drain is coupled to the node D1·, and the source is coupled to the drain and the gate of the NMOS transistor N41. The source of the NMOS transistors N41 and N42 is coupled to the low supply voltage VSS. The source and the drain of the PMOS transistor P42 are respectively coupled to the high power supply voltage VDD and the node B. The drain and gate of the NMOS transistor N42 are also coupled to the node B. When the input voltage Vin drops, the voltage level of the node D rises, thereby turning on the NMOS transistor N43, and the voltage level of the node D1 is lowered to turn on the PMOS transistor P42. When the PMOS transistor P42 is turned on, the voltage level of the node B rises. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. 1360947 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of an output buffer having a slew rate boost output stage circuit according to an embodiment of the present invention; FIG. 2 is a diagram showing an operation amplifier of node C and node D in an embodiment. 3 is a schematic diagram of a first slew rate boosting circuit according to an embodiment of the present invention; FIG. 4 is a diagram showing voltage changes of nodes C, C1, and A in FIG. 3; FIG. 5 is an embodiment of the present invention. A schematic diagram of a second slew rate boosting circuit; FIG. 6 is a diagram showing voltage changes of nodes D, D1, and B in FIG. 5; and FIG. 7 is an output of a circuit having a slew rate boosting output stage according to an embodiment of the present invention. The circuit diagram of the punch. [Main component symbol description] 11~ output buffer; 12~ slew rate boost output stage circuit; 13~ operational amplifier; 14~ first slew rate boost circuit; 15~ second slew rate boost circuit;
Vin〜輸入電壓；Vin~ input voltage;
Vout〜輸出電壓； VDD〜向電源電壓， 13 1360947 V S S〜低電源電壓； VI〜V4〜電壓； P卜 P2、P2卜 P22、P23、P41、P42〜PMOS 電晶體； Nl、N2、N21、N22、N41、N42、N43〜NMOS 電晶 A、B、C、Cl、D、D1〜節點。Vout ~ output voltage; VDD ~ to the power supply voltage, 13 1360947 VSS ~ low supply voltage; VI ~ V4 ~ voltage; P Bu P2, P2 Bu P22, P23, P41, P42 ~ PMOS transistor; Nl, N2, N21, N22 , N41, N42, N43 ~ NMOS transistor A, B, C, Cl, D, D1 ~ node.
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