135*8777 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種歸一半導體裝置之成$方法&半導體裝 置；特別是一種用於一半導體裝置之成形方法及半導體裝置。 【先前技術】 隨著電子產品之功能及應用演進及消費者對外形之要求，積體 鲁電路之封裝亦日趨高密度且微小，甚而自二維向三維發展，是故 業界研發出了晶圓級封裝（Wafer LeveI Package，WLp)、三維封 裝、多晶片封裝（Multi-Chip Package)和系統級封裝伽_ & Package)等封裝技術。 而根據應用需求之不同，可分為平面式的多晶月模組 ’Ui-Chip Module)、多晶片封裝(Multi Chip ㈣以及立體 堆豐式封裝（3D staeked卿㈣介其巾立料疊式縣係使數片 晶片以堆疊之方式組合’可更有效率地縮減封裝面積，且能同 時縮減整體尺寸及重量，符合輕祕小之需求，是故漸為業界 所採用。 _ 以習知之晶圓級之立體積體電路或堆疊封裝為例，為了在晶圓 片尺寸封裝（Wafer Level Chip Scale Package, WLCSP)上下達 到電性導通，其製程相當㈣，其流程㈣如第.1圖所示，相關 β至第2H圖所示。製程中’主要係需做兩次 雷射鑽孔，再加上進行一次電鍍。 更詳細而言，於步驟101中，係先於晶粒之基材2〇1(剖面圖係 如第2A圖所示）上雷射鑽孔以形成通孔2〇3(via hole)，此為第一次 5 I35l8777 4鑽孔，其細_第1B_示。接奸 =㈣於基材2。〗之周圍表面，且此介電層2二^ :2。…面圖係如第2C圖所示。接著如 J真:通 步騾105以在填滿介雷呙）以—s 回々不執仃 此為第…大+身^ 射鑽孔， 9Λ 、 以去除填充於通孔如内之部分介電芦 5使通孔2〇3再次貫通。需特別說明的是，第二次鑽孔後 壁仍有部分介電層⑽保留於Μ η 人鑽孔後之内 2ΕΗ所-抽 …上，以作為絕緣之用。最後如第 圖所不’執行步驟1()7以在介電層之通孔2〇3中電鑛，於 2〇3中形成柱狀之導電結構2〇7。於步驟⑽中，柱狀之導電^ 2〇7兩端更電録或印刷上焊錫，形成如第^圖所示之1 至此，便可形成單-具有導電結構2〇7之晶圓。 4 。田進仃步驟1U之立體堆疊時，將數片晶圓疊置，此時每片晶 S :導電結構207兩端之焊錫2()9恰相對應，如第2G圖所示 故取後執仃步驟i! 3，進行炫融焊接便可使各個晶圓電性 第2H圖所示。 疋妖如 然而，此種習知半導體裝置成形方法過程中，需採用兩次雷射 鑽孔’而雷射鑽孔機之價格及_f祕高。另—方面，將介電 層填4孔㈣m外，第二次#射㈣時，需料對位电 以免誤鑽’·而當在通孔内電鍍導電層時，導電層容易不均勾，平 坦度較低。上述各問題，均成為此業界極大之成本及製程負荷。 有L於此’提供一種製程花費較低之半導體裝置之成形方法及 所成A之半導體裝置，乃為此—業界虽待解決的問題。 【發明内容】 6 1358777 本發明之-目的在於提供—種用於一半導體裝置之成形方法， 包含下列步驟：⑷形成-導電凸塊(b卿)於-底材之-表面上· ⑻形成-介電層於導電凸塊之—周圍表面；⑷設置底材於一基 材之-表面上，使具有介電層之導電凸塊適容置於基材之一通孔 中；以及（d)去除底材。 本發明之另-目的在於提供一種半導體裝置包含一基材、_ 半導體積體電路、-導電結構。基材貫設—通孔，通孔具有一第 -縱向尺寸。半導體積體電路設置於基材中。導電結構設置於通 孔中，以與半導體積體電路電性連接。導電結構包含—導電凸塊 以及-介電層。導電凸塊具有—第二縱向尺寸，且第二縱向尺寸 實質上大於第-縱向尺寸。介電層僅包覆於導電⑽之—周圍表 面’且與通孔之一側壁密接。 本發明之再-目的在於提供一種半導體裝置，包含一基材、一 料體積體電路以及-導電結構。基材貫設—通孔，通孔具有一 第縱向尺寸。半導體積體電路設置於基材中。導電結構設置於 通孔中’以與半導體積體電路電性連接。導電結構包含一導電凸 塊以及-介電層。導電凸塊具有一第二縱向尺寸，且第二縱向尺 寸實質上大於第-縱向尺寸。介電層包覆於導電凸塊之—周圍表 面及基材之-表面上，其中包覆於導電凸塊之周圍表面之介電層 係與通孔之一側壁密接。 由於本發明僅需於基材上施行一次雷射鑽孔，是故成本可大幅 降低，亦不會有第二次鑽孔之對位問題。 為讓本發明之上述目的、技術特徵和優點能更明顯易懂，下文 7 1358777 係以較佳實施例配合所附圖式進行詳細說明。 【實施方式】 本發明之第一實施例係為— ^ . 用於一 +導體裝置之成形方法， 其、圖係如第3圖所示，而知_ 關。彳面圖則如第4A圖至第4J圖 所不。此成形方法包含下列步 •百先，執行步驟301以於一基 材401上雷射鑽孔，藉此形135*8777 IX. Description of the Invention: [Technical Field] The present invention relates to a method and a semiconductor device for normalizing a semiconductor device, and more particularly to a method for forming a semiconductor device and a semiconductor device. [Prior Art] With the evolution of the functions and applications of electronic products and the requirements of consumers for the appearance, the packaging of ICB circuits is becoming increasingly dense and small, and even from 2D to 3D, the industry has developed wafers. Packaging technologies such as Wafer LeveI Package (WLp), 3D packaging, Multi-Chip Package, and System-in-Package Gamma Packages. According to the application requirements, it can be divided into a flat-type polycrystalline monthly module 'Ui-Chip Module', a multi-chip package (Multi Chip (four) and a three-dimensional stacking package (3D staeked Qing (four) through its towel stack) The county system combines several wafers in a stacking manner to reduce the package area more efficiently, and can reduce the overall size and weight at the same time, which meets the needs of light and small, and is gradually adopted by the industry. For example, in the case of a circular volume or a stacked package, in order to achieve electrical conduction above and below the Wafer Level Chip Scale Package (WLCSP), the process is equivalent (4), and the flow (4) is as shown in Fig. 1. , related β to 2H figure. In the process, 'mainly need to do two laser drilling, plus one plating. In more detail, in step 101, before the grain substrate 2 〇1 (the cross-sectional view is as shown in Figure 2A) is laser drilled to form a via hole 2〇3 (via hole), which is the first 5 I35l8777 4 drilled hole, which is shown in detail _1B_. Rape = (four) on the surrounding surface of the substrate 2. and the dielectric layer 2 2 ^ : 2 .... 2C is shown. Then, if J is true: pass 骡 105 to fill in the Thunder 呙 以 以 — — — — — — — — — — — — — ... ... ... ... ... ... 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大For example, part of the dielectric reed 5 makes the through hole 2〇3 pass through again. It should be specially noted that some of the dielectric layer (10) remains in the back wall of the second hole after drilling. Pumping on, for use as insulation. Finally, as shown in the figure, step 1 () 7 is performed to form a columnar conductive structure in 2〇3 in the through hole 2〇3 of the dielectric layer. 〇7. In the step (10), the columnar conductive electrodes are further recorded or printed with solder on both ends to form a crystal as shown in Fig. 1, thereby forming a single crystal having a conductive structure of 2〇7. 4. In the case of the 1U three-dimensional stacking of Tian Jin, several wafers are stacked. At this time, each piece of crystal S: solder 2 () 9 at both ends of the conductive structure 207 corresponds to each other, as shown in FIG. 2G. Therefore, after taking the step i! 3, the soldering and soldering can be performed to make each wafer electrically as shown in Fig. 2H. However, in the conventional semiconductor device forming method, two lasers are required. drilling The price of the laser drilling machine and the _f secret height. On the other hand, the dielectric layer is filled with 4 holes (four) m, and the second time # shot (four), the material needs to be aligned to avoid accidental drilling. When the conductive layer is plated in the hole, the conductive layer is easily uneven and the flatness is low. All of the above problems have become a great cost and process load in the industry. The method and the semiconductor device formed by A are the problems to be solved by the industry. SUMMARY OF THE INVENTION The present invention is directed to providing a method for forming a semiconductor device comprising the following steps: (4) forming - a conductive bump (b) on the surface of the substrate - (8) forming a dielectric layer on the peripheral surface of the conductive bump; (4) providing a substrate on the surface of a substrate to have a dielectric layer The conductive bumps are adapted to be placed in one of the through holes of the substrate; and (d) the substrate is removed. Another object of the present invention is to provide a semiconductor device comprising a substrate, a semiconductor integrated circuit, and a conductive structure. The substrate is disposed through a through hole having a first-longitudinal dimension. The semiconductor integrated circuit is disposed in the substrate. The conductive structure is disposed in the through hole to be electrically connected to the semiconductor integrated circuit. The electrically conductive structure comprises - a conductive bump and a dielectric layer. The conductive bumps have a second longitudinal dimension and the second longitudinal dimension is substantially larger than the first-longitudinal dimension. The dielectric layer is only coated on the surrounding surface of the conductive (10) and is in close contact with one of the side walls of the through hole. A further object of the present invention is to provide a semiconductor device comprising a substrate, a bulk body circuit and a conductive structure. The substrate is disposed through a through hole having a longitudinal dimension. The semiconductor integrated circuit is disposed in the substrate. The conductive structure is disposed in the via hole ” to be electrically connected to the semiconductor integrated circuit. The electrically conductive structure comprises a conductive bump and a dielectric layer. The conductive bump has a second longitudinal dimension and the second longitudinal dimension is substantially larger than the first-longitudinal dimension. The dielectric layer is coated on the surface of the conductive bump and the surface of the substrate, wherein the dielectric layer covering the peripheral surface of the conductive bump is in close contact with one of the sidewalls of the through hole. Since the present invention only requires one laser drilling on the substrate, the cost can be greatly reduced, and there is no alignment problem of the second drilling. The above objects, technical features and advantages of the present invention will become more apparent from the following description. [Embodiment] A first embodiment of the present invention is a method for forming a +-conductor device, and the drawing is as shown in Fig. 3, and is known. The facets are as shown in Figures 4A through 4J. The forming method comprises the following steps: • First, step 301 is performed to drill a laser hole on a substrate 401, thereby forming
圖及第佔圖所示，此基材401上;:其剖面圖係如第4A 上部介於通孔403間係具有一半導 體積體電路415。於此實施例中 此丞材401係為一晶圓，但於其 他貫施例中，亦可為一晶粒。 於步驟303中’形成二導電凸塊（bum_於一底材術之一表 2上，其剖面圖係如第4C圖所示，其中導電凸塊4〇5於此或可稱 為導電栓（conductive plugs)，盆报# 士斗一Γ从士 ”形成方式可為電鍵、打金線（Gold _或植金屬針（Metal Pin);而底材4〇7之材料可為聚亞酿胺 (P〇〗y_de ’ PI)。於本實施例中，此等導電凸塊4〇5之橫剖面係為 圓形’而縱剖㈣為-T字形，藉由τ字形上方之橫向部分，便 可利於與半導體積體電路化之電性導通（於隨後圖式表示出）。而 此導 。 =著執行步驟電層彻於各個導電凸塊4〇5 之—周圍表®;更詳細而言，步驟305更包含依序執行⑷、 3〇5(b)及3〇5(〇三步驟。步驟3〇5⑻係塗佈形成一光阻層川（材料 可為聚亞醯胺)於底材4〇7之表面上及導電凸塊4〇5之周圍表面， 第4D圖所示。步驟％5(b)係曝光顯影以固化導電凸塊之巧 圍表面之—部分光阻層411，以形成介電層_作為保護絕緣，如 8 1358777 第4E圖所示，於此可採用化學氣相沉積（Chemical Vapor Deposition, CVD)或熱氧化法(Thermal Oxidation)。步驟 305(c)則係 蝕刻介電層409周圍之光阻層41卜藉此將導電凸塊405周圍之光 阻去除，如第4F圖所示。經由執行步驟305(a)〜305(c)即可於導電 凸塊405之周圍表面，將部分光阻層411固化為介電層409。 接下來執行步驟307,設置底材407於基材401之表面上進行對 位接合’使具有介電層409之各個導電凸塊405適容置於基材4〇1 之各個通孔403中，其中各通孔403具有一第二縱向尺寸，且導 電凸塊405之第一縱向尺寸係大於通孔403之第二縱向尺寸，亦 即導電凸塊405容置於通孔403中後，會有部分突出，如第4(3圖 所示。完成對位接合後，執行步驟309以去除底材407，此時導電 凸塊405就會轉移至基材401上’如第4H圖所示。其中，步驟 309係藉由蝕刻、撕除或磨除等技術以達成底材407之去除。至 此，便可得到内部形成有導電凸塊405之單一晶圓。 隨後，執行步驟311 ’分別設置一導電體413於導電凸塊405之 兩端，如第41圖所示。步驟3 1〗則係藉由印刷或電鍍設置導電體 413，導電體413可為焊錫（solder)或锡球(solder ball)。然後執行步 驟3 1 3 ’將數個經步驟311設置導電體413後之基材401對位堆疊。 最後執行步驟315,熔化導電體4丨3以與另一基材401上之半導體 積體電路415電性連接，如第4J圖所示，此處之熔化係由迴焊 (reflow)達成。 第一實施例所形成之半導體裝置係如第41圖所示。此半導體裝 置包^—基材401、一半導體積體電路415、一導電結構417及二 9 1358777 導電體413，而半導體裝置係為-晶圓（wafer)，以成為晶圓級晶片 尺寸封裝’於其他實施態樣t，亦可為_晶粒㈣。同時參考第 4B圖，基材401貫設一通孔4〇3，通孔4〇3具有_第一縱向尺寸。 半導體積體電路415設置於基材中。導電結構4丨7設置於通 孔403巾，以與半導體積體電路415電性連接。導電結構川包 含一導電凸塊405以及-介電層4〇9。導電凸塊彻係為—金屬凸 塊，且如第-實施例所述’半導體裝置之導電凸塊他係為丁字 形，以利於與半導體積體電路415之電性㈣，於其他實施態樣 令，導電&塊405可為其他得接觸半導體積體電路4〗5之形狀。 導電凸塊彻具有-第二縱向尺寸，且第二縱向尺寸實質上大於 弟—縱向尺寸。介電層彻料—氧化層。舉例而·τ ’此氧靜 之材料可為二氧化石夕（Si〇2)、氧化銅（Cu〇)、二氧化銅（Cu〇2)、^ 化華2〇3)或氧化錫咖〇2)等。介電層4〇9僅包覆於導電凸塊奶 且與通孔403之一側壁密接。二導電體川分別 口又置於導電結構4〗7之_嫂 . λ人導電結構417電性連接。此導 电肢化包卜銲線、—錫球或—金屬凸塊。 於貫際應用時，半導濟梦罢及— 衣置係稭由導電結構417盥導 以和另一半導體裝置電 413 裝置係與半導體裝置實質上星 另丰蜍胆 晶圓與一晶粒。、…、有-相同構造，但兩者可分別為一 本發明之第二實施例同樣一 … 法，其流程圓係如第5圖所示，於·^導體裝置之成形方 6】圖所示。此成形方法包含下、’而相關剖面圖則如第6A圖至第 下列步驟：首先，執行步驟5〇1以於 10 1358777 一基材_上雷射鑽孔，藉此形成2個通孔_，其剖面圖係如第 圖及第6B圖所不，此基材6〇1上部介於通孔咖㈤係且有一 半導體積體電路615。於此實施例中，此基材_系為一晶圓但 於其他實施例中，亦可為一晶粒。 於乂驟5G3中’形成二導電凸塊6()5於―底材⑽7之—表面上， 料面圖係如第6C圖所示，其中導電凸塊奶於此或可稱為導電 技，其形成方式可為電錢、打金線或植金屬針；而底材術之材 料可為聚亞酿胺。於本實施例中，此等導電巴塊6〇5之橫剖面係 為圓形’而縱剖面則為—T字形，藉由τ字形上方之橫向部分， 便可利於與半導體積體電路615《電性導 出)。而此導電凸塊605具有一第一縱向尺寸。 Μ表不 接著執行步驟505,亦即形成一介電層_於各個導電凸塊6〇5 之-周圍表面’如第6D圖所示。然而，與第—實施例不同的是， 本^施例之介電層_係形成於底材607之表面上及導電凸塊6〇5 之一表面上，此步驟所採用之方式係為旋轉塗佈。 接下來執行步驟507，設置底材6〇7於基材6〇1之表面上進行對 位接合，使具有介電層_之各個導電凸塊6〇5適容置於基材咖 之各偏通孔603 t，其中各通孔6G3具有—第二縱向尺寸， 電凸塊605之第-縱向尺寸係大於通孔6()3之第二縱向尺寸 即導電&塊6〇5容置於通孔6〇3中後’會有部分突出，如第 所示。 園 步驟509則係去除導電凸塊6G5之表面中之—底面之介” 6〇9，亦即去除導電凸塊⑽之下表面（亦即τ字形下方縱向部分 1358777 之底面）之介電層_，如第6F圖所示，本實施例之去除方式係採 取磨除，於其他實施態樣中，亦可使用其他去除方式。 執行步驟5U以去除底材607，此時導電凸塊6〇5就會轉移至基 材_上’如第6G圖所示。其中，步驟511係藉由敍刻、撕除二 f除等技術料成底材術之絲。至此，便可得勒部形成有 導電凸塊605之單一晶圓。 隨後，執行步驟5】3,分別設置一導電體613於導電凸塊6〇5 之兩端，如第6H圖所示。步驟515則係藉由印刷或電鍵設置導電 體613，導電體613可為痒錫或錫球。然後執行步驟517，將數個 經步驟設置導電體⑴後之基材⑹對位堆疊，如第Η圖所 不。最後執行步驟519,炫化導電體613以與另一基材_上之半 導體積體電路615電性連接，此處之溶化係由迴焊達成’此時介 電層609也會同時被固化（cured)，如第6J圖所示。 第二實施_形成之半導體裝置“第6H圖所示。此半導體裝 置包含一基材60卜一半導體積體電路615、一導電結構617 = 二導電體6Π，而半導體裝置係為—晶圓，以形成晶圓級晶片尺寸 封裝’於其他實施態樣中’亦可為一晶粒。同時參考第則，基 材6〇1貫設-通孔603 ’通孔6〇3具有一第一縱向尺寸。半導體積 體電路6】5言史置於基材60】中。導電結構617設置於通孔㈤二: 以與半導體積體電路615電性連接。導電結構617包含一導電晶 塊605以及一介電層609。導電凸塊6〇5係為—金屬凸塊，且^ -實施例所述’半導«置之導電凸塊咖係為丁㈣，以利於 與半導體積體電路615之電性導通，於其他實施態樣中，導電凸 12 I3S8777 塊605可為其他得接觸半導體 且右Ha〜 、題電路615之形狀。導電凸塊605 具有弟一縱向尺寸，且第-敏a 八+ 弟—緃向尺寸實質上大於第一縱向尺 寸。介電層009係為一氧化層。舉 广 门尺 - 4彳卜- 丨而5，此氧化層之材料可為 一乳化矽（Si02)、氧化銅（Cu〇)、 々# / —乳化銅（Cu〇2) '氧化鋁（Al2〇3) 或乳化錫（Sn〇2)等。介電層6〇9包 另其鉍* 旻於導电凸塊605之一周圍表面 ^ 之—表面上，#中包覆於導電凸塊605之周圍表面之 ^層_係與通孔_之—側壁密接。二導電體613分別設置 二導二構日6Π之二端，以與導電結構617電性連接。此導電又體置 匕3 —銲線、一錫球或一金屬凸塊。 於實際應用時，半導體裝置係藉由導電結構6Π與導電體613 體裝置電性連接’如第6J圖所示，其中另-半導體 =係與半導體裝置實質上具有-相同構造，但兩者可分別為-晶圓與一晶粒。 於上述二實關t，軸每—基材僅鑽設2個通孔，且相應之 W凸塊亦僅形成2個，但習知此項技術者應可輕易推及盆他 ❿ 施數量。 糟由本發明之結構，製作過程中僅需進行一次雷射鑽孔，製作 費用較低’沒有介電層填孔問題’亦無第二次雷射鑽孔對位的問 題’不需在通孔内電鍍導電層，簡化製程。亦無内的導電層平坦 度的問題 上述之實施例僅用來例舉本發明之實施態樣，以及闊釋本發明 之，術特徵’亚非用來限制本發明之保護範嗜。任何熟悉此技術 者可輪易完成之改變或均等性之安排均屬於本發明所主張之範 13 圍’本發明之權利保護範圍應以申請專利範圍為準。 【圖式簡單說明】 第1圖係為習知半導體裝置之成形流程圖； 第2A圖至第2H圖係為習知半導體裝置成形示意圖； 第3圖係為本發明第_眘 ^貫她例之半導體裝置成形流程圖； 第4A圖至第4J圖传a太级—— 马本發明弟一貫施例之半導體裝置成形示 意圖； 第5圖係為本發明第二實施例之半導體裝置成形流程圖；以及 第6A圖至第6;圖係為本發明第二實施例之半導體裝置成形示 意圖。 【主要元件符號說明】 201 ： 基材 203 ： 通孔 205 ： 介電層 207 ： 導電結構 209 ： 焊錫 401 : 基材 403 ： 通孔 405 ： 導電凸塊 407 ： 底材 409 ： 介電層 411 ： 光阻層 413 ： 導電體 415 ： :半導體積體電路 417 : 導電結構 601 ： :基材 603 ： 通孔 605 ： :導電凸塊 607 ： '底材 609 ： •介電層 613 ： :導電體 615 :半導體積體電路 617 ： :導電結構 14The substrate 401 is shown in the figure and the second figure; the cross-sectional view is such that the upper portion of the fourth portion has a half-conductor body circuit 415 between the via holes 403. In this embodiment, the coffin 401 is a wafer, but in other embodiments, it may be a die. In step 303, 'two conductive bumps are formed (bum_ on one of the substrates), and the cross-sectional view thereof is as shown in FIG. 4C, wherein the conductive bumps 4〇5 may be referred to as conductive plugs. (conductive plugs), pots reported #士斗一Γ士" can be formed by electric keys, gold wire (Gold _ or metal needle (Metal Pin); and the material of the substrate 4〇7 can be poly-bristamine (P〇〗 y_de 'PI). In this embodiment, the conductive bumps 4〇5 have a circular cross section and the longitudinal section (4) is a T-shaped shape, and the lateral portion above the τ-shaped shape is used. It can facilitate the electrical conduction with the semiconductor integrated circuit (shown in the following figure). And this step = the implementation of the step electrical layer is completely in the vicinity of the respective conductive bumps 4〇5®; in more detail Step 305 further comprises sequentially performing (4), 3〇5(b), and 3〇5 (〇3 steps. Step 3〇5(8) is coating to form a photoresist layer (the material may be polyammonium) on the substrate. The surface of the 4〇7 and the surrounding surface of the conductive bump 4〇5 are shown in Fig. 4D. Step %5(b) is exposure development to cure the partial photoresist layer 411 of the surface of the conductive bump, Forming a dielectric layer _ as a protective insulation, as shown in Fig. 4E of 8 1358777, where chemical vapor deposition (CVD) or thermal oxidation (Thermal Oxidation) can be used. Step 305 (c) is etching. The photoresist layer 41 around the dielectric layer 409 is thereby removed from the photoresist around the conductive bumps 405, as shown in FIG. 4F. The conductive bumps 405 can be performed by performing steps 305(a) to 305(c). A portion of the photoresist layer 411 is cured to a dielectric layer 409. Next, step 307 is performed to provide a substrate 407 for performing a para-bonding on the surface of the substrate 401 to cause each of the conductive bumps having the dielectric layer 409. 405 is disposed in each of the through holes 403 of the substrate 4〇1, wherein each of the through holes 403 has a second longitudinal dimension, and the first longitudinal dimension of the conductive bumps 405 is greater than the second longitudinal dimension of the through holes 403. That is, after the conductive bump 405 is received in the through hole 403, there is a partial protrusion, as shown in FIG. 4 (3). After the alignment bonding is completed, step 309 is performed to remove the substrate 407, and the conductive bump 405 is at this time. Will be transferred to the substrate 401 ' as shown in Figure 4H. Among them, step 309 is by etching, tearing Or removing the technology to achieve the removal of the substrate 407. Thus, a single wafer having the conductive bumps 405 formed therein can be obtained. Subsequently, step 311' is performed to respectively provide a conductor 413 at both ends of the conductive bumps 405. As shown in Fig. 41, step 31 is to provide a conductor 413 by printing or electroplating, and the conductor 413 may be a solder or a solder ball. Then, step 3 1 3 ' is performed to stack a plurality of substrates 401 after the electrical conductors 413 are disposed through step 311. Finally, in step 315, the conductor 4丨3 is melted to be electrically connected to the semiconductor integrated circuit 415 on the other substrate 401. As shown in Fig. 4J, the melting is here achieved by reflow. The semiconductor device formed in the first embodiment is as shown in Fig. 41. The semiconductor device comprises a substrate 401, a semiconductor integrated circuit 415, a conductive structure 417 and two 9 1358777 electrical conductors 413, and the semiconductor device is a wafer to be a wafer level wafer size package. In other implementations, t can also be _ die (four). Referring also to Fig. 4B, the substrate 401 is provided with a through hole 4〇3 having a first longitudinal dimension. The semiconductor integrated circuit 415 is disposed in the substrate. The conductive structure 4丨7 is disposed on the through hole 403 to be electrically connected to the semiconductor integrated circuit 415. The conductive structure includes a conductive bump 405 and a dielectric layer 4〇9. The conductive bumps are exactly metal bumps, and the conductive bumps of the semiconductor device are T-shaped as described in the first embodiment to facilitate electrical compatibility with the semiconductor integrated circuit 415. In other implementations. The conductive & block 405 can be in the shape of another contact semiconductor integrated circuit 4 . The conductive bumps have a second longitudinal dimension and the second longitudinal dimension is substantially larger than the longitudinal-longitudinal dimension. The dielectric layer is cleaned—the oxide layer. For example, τ 'this oxygen static material can be dioxide (Si〇2), copper oxide (Cu〇), copper dioxide (Cu〇2), ^ Huahua 2〇3) or tin oxide curry 2) Wait. The dielectric layer 4〇9 is only coated on the conductive bump milk and is in close contact with one of the sidewalls of the through hole 403. The two conductors are respectively placed in the conductive structure 4 _ 7 _ 嫂 λ human conductive structure 417 is electrically connected. The conductive limb is coated with a soldering wire, a solder ball or a metal bump. In the case of continuous application, the semi-conducting dream--the clothing is made of conductive structure 417 and electrically connected to another semiconductor device. The device and the semiconductor device are substantially identical to the wafer and a die. The same structure is used in the second embodiment of the present invention, and the flow circle is as shown in Fig. 5, and the forming means of the conductor device is as shown in Fig. 5 Show. The forming method includes the following, and the relevant cross-sectional view is as shown in FIG. 6A to the following steps: First, step 5〇1 is performed to 10 1358777 a substrate_upper laser drilling, thereby forming 2 through holes _ The cross-sectional view is as shown in the figure and FIG. 6B. The upper portion of the substrate 6〇1 is interposed between the through-holes (5) and has a semiconductor integrated circuit 615. In this embodiment, the substrate is a wafer, but in other embodiments, it may be a die. In step 5G3, 'the two conductive bumps 6 () 5 are formed on the surface of the substrate (10) 7 , and the plan view is as shown in FIG. 6C , wherein the conductive bumps are or may be referred to as conductive technologies. It can be formed by electric money, gold wire or metal needle; and the material of the substrate can be poly-branched amine. In this embodiment, the cross-sections of the conductive blocks 6〇5 are circular and the vertical cross-section is a T-shaped shape, and the lateral portion above the τ-shaped shape can facilitate the integration with the semiconductor integrated circuit 615. Electrical export). The conductive bump 605 has a first longitudinal dimension. The step 505 is not performed, that is, a dielectric layer is formed - the peripheral surface of each of the conductive bumps 6?5 is as shown in Fig. 6D. However, unlike the first embodiment, the dielectric layer of the present embodiment is formed on the surface of the substrate 607 and on one surface of the conductive bumps 〇5, and the method used in this step is rotation. Coating. Next, in step 507, the substrate 6〇7 is disposed on the surface of the substrate 6〇1 to perform the alignment bonding, so that the respective conductive bumps 6〇5 having the dielectric layer are disposed on the substrate. The through hole 603 t, wherein each of the through holes 6G3 has a second longitudinal dimension, and the first longitudinal dimension of the electrical bump 605 is larger than the second longitudinal dimension of the through hole 6 () 3, that is, the conductive & After the through hole 6〇3, there will be a partial protrusion, as shown in the figure. The step 509 of removing the dielectric layer 6 〇 9 in the surface of the conductive bump 6G5, that is, removing the dielectric layer on the lower surface of the conductive bump (10) (that is, the bottom surface of the vertical portion 1358777 below the τ shape) As shown in FIG. 6F, the removal method of the embodiment is performed by grinding, and in other embodiments, other removal methods may be used. Step 5U is performed to remove the substrate 607, and the conductive bumps 6〇5 at this time. It will be transferred to the substrate_upper as shown in Fig. 6G. Among them, step 511 is made into a material of the substrate by means of sculpt, tearing off the second f, etc. A single wafer of conductive bumps 605. Subsequently, step 5]3 is performed to respectively provide a conductive body 613 at both ends of the conductive bumps 6〇5, as shown in Fig. 6H. Step 515 is by printing or a key. The electrical conductor 613 is disposed, and the electrical conductor 613 can be itch tin or tin ball. Then, step 517 is performed to stack the plurality of substrates (6) after the step of setting the electrical conductor (1), as shown in the figure. Finally, step 519 is performed. The illuminating conductor 613 is electrically connected to the semiconductor integrated circuit 615 on the other substrate. The system reached a melting reflow 'In this case the dielectric layer 609 will also be cured (cured), as shown in FIG. 6J first semiconductor device "_ a second embodiment of the first form shown in FIG. 6H. The semiconductor device comprises a substrate 60, a semiconductor integrated circuit 615, a conductive structure 617 = a two-conductor 6 Π, and the semiconductor device is a wafer to form a wafer-level wafer size package, in other embodiments. 'Can also be a grain. Referring also to the second, the substrate 6〇1 is provided - the through hole 603 'the through hole 6〇3 has a first longitudinal dimension. The semiconductor integrated circuit 6 is placed in the substrate 60]. The conductive structure 617 is disposed on the through hole (5) 2 to be electrically connected to the semiconductor integrated circuit 615. Conductive structure 617 includes a conductive die 605 and a dielectric layer 609. The conductive bumps 6〇5 are metal bumps, and the conductive traces of the semi-conductive tabs are diced to the electrical integration with the semiconductor integrated circuit 615. In an embodiment, the conductive bumps 12 I3S8777 block 605 can be in the shape of other semiconductors that are in contact with the right Ha~ and the circuit 615. The conductive bump 605 has a longitudinal dimension, and the first-sensitive a-eight-dimension-direction dimension is substantially larger than the first longitudinal dimension. The dielectric layer 009 is an oxide layer.广广门尺 - 4彳卜 - 丨 and 5, the material of this oxide layer can be an emulsified bismuth (SiO 2 ), copper oxide (Cu 〇), 々 # / - emulsified copper (Cu 〇 2) 'alumina (Al2 〇 3) or emulsified tin (Sn〇2). The dielectric layer 6〇9 is further disposed on the surface of the surface of one of the conductive bumps 605, and the layer covering the peripheral surface of the conductive bump 605 is a layer and a via hole. - The side walls are in close contact. The two conductors 613 are respectively disposed at two ends of the two-conducting two-construction day 6 to be electrically connected to the conductive structure 617. This conductive body is also placed on the 匕3—welding wire, a solder ball or a metal bump. In practical applications, the semiconductor device is electrically connected to the body of the conductor 613 by the conductive structure 6', as shown in FIG. 6J, wherein the other semiconductor=the semiconductor device has substantially the same structure, but both They are - wafer and a die. In the above two real-time t, the shaft only drills 2 through holes per substrate, and the corresponding W bumps only form 2, but those skilled in the art should be able to easily push the number of pots. According to the structure of the present invention, only one laser drilling is required in the manufacturing process, the production cost is low 'no dielectric layer filling problem' and there is no problem of the second laser drilling alignment 'no need in the through hole The conductive layer is internally plated to simplify the process. The problem of the flatness of the conductive layer is also not described. The above embodiments are merely illustrative of the embodiments of the present invention, and the present invention is widely used to limit the protection of the present invention. Any change or equality that can be easily accomplished by those skilled in the art is intended to be within the scope of the invention. The scope of the invention should be determined by the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flow chart of forming a conventional semiconductor device; FIGS. 2A to 2H are schematic views showing a conventional semiconductor device; FIG. 3 is a third example of the present invention. A semiconductor device forming flow chart; 4A to 4J are a class of a semiconductor device; FIG. 5 is a schematic view of a semiconductor device forming process according to a second embodiment of the present invention; And FIGS. 6A to 6; FIG. 6 is a schematic view showing the formation of the semiconductor device according to the second embodiment of the present invention. [Main component symbol description] 201 : Substrate 203 : Via 205 : Dielectric layer 207 : Conductive structure 209 : Solder 401 : Substrate 403 : Via 405 : Conductive bump 407 : Substrate 409 : Dielectric layer 411 : Photoresist layer 413 : Conductor 415 : : Semiconductor integrated circuit 417 : Conductive structure 601 : : Substrate 603 : Through hole 605 : : Conductive bump 607 : 'Substrate 609 : • Dielectric layer 613 : : Conductor 615 : Semiconductor integrated circuit 617 : : Conductive structure 14