TWI358593B - Pixel array substrate and manufacturing method the - Google Patents

Description

1358593

达达编号号: TW3684PA IX. Description of the Invention: [Technical Field] The present invention relates to a pixel array substrate and a method of fabricating the same, and more particularly to a pixel array substrate having a varying thickness of an insulating layer and Its manufacturing method. [Prior Art] The insulating layer of the pixel array substrate is used to isolate two metal layers, such as a region where the gate and the drain are separated, the gate and the source, and the scan line and the data line are interleaved. In order to reduce the threshold voltage and reduce the driving cost, the conventional halogen array substrate has a thin insulating layer. However, if the thickness of the insulating layer is too thin, the parasitic capacitance effect between the interleaved scan line and the data line, between the gate and the drain, and between the gate and the source may increase, resulting in RC delay. In turn, the signal delay is distorted to reduce the quality of the pixel array substrate. SUMMARY OF THE INVENTION In view of the above, the present invention relates to a halogen array substrate and a method of fabricating the same, which increases the thickness of an insulating layer in a region where a scan line and a data line are interleaved, and reduces the thickness of the insulating layer of the storage capacitor to reduce the resistance and capacitance. Delay and increase the aperture ratio. According to an aspect of the invention, a halogen array substrate is provided, comprising a substrate, a pixel array, and a plurality of storage capacitors. The substrate has a display area. The halogen array is formed by interlacing a plurality of parallel scanning lines separated by an insulating layer and a plurality of parallel data lines in the display area. These storage capacitors are respectively ^58593

Three ^! No.: TW3084PA ' Set in the pixel array. Each storage capacitor includes a common electrode line and a conductive layer. The common electrode line is disposed on the substrate. The conductive layer is disposed over the common 'electrode line and separated from the common electrode line by an insulating layer. The thickness of the insulating layer between each scanning line and each data line is greater than the thickness of the insulating layer of each storage capacitor. According to another aspect of the present invention, a method of fabricating a pixel array substrate is provided, comprising the following steps. First, a substrate is provided having a display area and a wiring area. Furthermore, a plurality of scanning lines, a plurality of first scanning lines, and a plurality of common electrode lines are formed. These scanning lines are formed on the display area of the substrate. The first scan lines are formed by a portion of the scan lines extending to the wiring area. The common electrode lines are formed on the display area of the substrate and are respectively between the scan lines. Then, an insulating layer is formed on the substrate and covers a portion of the scan lines, the first scan lines located in the wiring region, and the common electrode lines, and the insulating layers have unequal thicknesses. Next, a semiconductor layer is formed on the insulating layer and corresponds to the first scan lines. Furthermore, the shape is formed into a plurality of data lines, a plurality of conductive layers and a plurality of second scanning lines. The data lines are formed in the display area and are vertically interlaced with the scan lines and separated by an insulating layer. The conductive layers are formed on a portion of the insulating layer and correspond to the respective common electrode lines to form a storage capacitor. The second feed lines are formed on a portion of the first scan lines and are separated from the first scan lines by an insulating layer. Then, a protective layer is formed, and a portion of the protective layer is etched to expose a portion of the surface of the scan lines and a portion of the second scan lines to form a plurality of via holes. Then, a plurality of first halogen electrodes are formed on the via holes to electrically connect the second scan lines and the scan lines. Its 1358593

Ξ达号-· TW3684PA Second Emperor* Each sweep line and each data link A;:: degrees.忿々 ΑΧ::, greater than storage is obviously easy, as detailed below. For example, the following is a better implementation. (10):: Two mentions as this (four), shrink. The use of the description does not dictate the scope of the present invention. The second embodiment shows that the present invention is not limited to unnecessary elements. Piece, to clear the green ^ @ refer to the first to third figures, the first figure 螬 'show according to the top view of the | 1 昼 阵列 阵列 阵列 阵列 阵列 阵列 阵列 帛 图 图 图 图 图 图 图 » » » » » » » » The cross-sectional view along the figure, and the third figure show the iB_m diagram in the first figure. Referring to FIG. 1 of the cross section θ of I Ba, the halogen array substrate 100 includes a substrate 11 〇, a drawing, a column, and a plurality of storage capacitors (storage capacitor ' Cst} 1:) material l 〗 Rw. The base is, for example, transparent glass and has a display area El. The halogen array is an array in which a plurality of halogens C such as P1) are arranged, and the pixel P1 is formed by the parallel lines 111 and 112 and the parallel data lines 1U and 1H, and is not in the El. Please refer to Fig. 1 and Fig. 3 at the same time. The interlaced lines of each sweeping line (such as 1) and each data line (such as 113) are separated by an insulating layer 130. The storage capacitor 120 is disposed on the pixel array.

The thickness of the insulating layer 130 between the TW3684PA 02 and the source 153 is increased to reduce the parasitic capacitance between the gate 151 and the drain 152 and the source 153. Furthermore, the threshold voltage (Vth) is the minimum voltage for driving the thin film transistor 150, and the drain 152 and the source 153 are induced on the channel layer 154 through the insulating layer 130 by the voltage of the gate 151. Since the thickness of the insulating layer 130 between the channel layer 154 and the gate rib 151 is reduced, the threshold voltage can be lowered by #, thereby achieving the effect of reducing the driving cost. Furthermore, the thickness of the insulating layer 130 between the gate 151 and the drain 152 and the source 153 is greater than the thickness of the insulating layer 130 of the storage capacitor 120. In addition, as shown in FIG. 1 and FIG. 3, the pixel array substrate 1 further includes a plurality of second halogen electrodes (eg, 140) respectively disposed in a pixel of the pixel array (eg, P1) and disposed on The substrate 11 is over the substrate 11 and separated from the substrate 11 by an insulating layer 130. The pixel electrode 140 is preferably indium tin oxide (IT0). The second pixel electrodes 14 are electrically connected to the drain electrodes 152 and the conductive layers 122, respectively. Preferably, the thickness of the insulating layer 130 between the scan line in φ and the data line 1丨3 is greater than the thickness of the insulating layer 13 between the second halogen electrode 140 and the substrate 11〇. Since the thickness of the insulating layer 13 between the second pixel electrode 140 and the substrate 11 is reduced, the efficiency of light penetration through the pixel P1 is improved, thereby increasing the light utilization rate. Further, the insulating layer 130 is made of, for example, a material such as siHcon nitride (SiN), siiic 〇 〇 xynitride (SiON), nitride, oxynitride or vapor. In the present embodiment, the pixel array substrate 100 further includes a protective layer 160 for the channel layer 154, the second scan line 112a, the scan line 111, and the data line 113 with dust or moisture 11 1358593

Sanda number: TW3684PA isolated. In the present embodiment, the thickness of the insulating layer 130 is substantially based on a modulation of 360 nm. Therefore, the thickness of the insulating layer 130 between the scan line 111 and the data line 113, the thickness of the insulating layer 130 of the wiring region E2, and the thickness of the insulating layer 130 between the gate 151 and the drain 152 and the source 153 are substantially greater than 360. Nm. The thickness of the insulating layer 130 of the storage capacitor 120, the thickness of the insulating layer 130 between the pixel electrode 140 and the substrate 110, and the thickness of the insulating layer 130 between the channel layer 154 and the gate 151 are substantially less than 360 nm °. The flowchart illustrates a method of manufacturing the halogen array substrate 100. Please refer to FIG. 4A, which is a flow chart showing a method of manufacturing a halogen array substrate. Please also refer to the component numbers in Figures 1 to 3. First, as shown in step S301 of Fig. 4A, a substrate 110 is provided, and the substrate 110 has a display area E1 and a wiring area E2, and the substrate 110 is, for example, transparent glass. Further, as shown in step S302, the scanning lines 111 and 112, the first scanning line 111a, and the common electrode line 121 are formed. The scanning lines 111 and 112 are formed on the display area E1 of the substrate 110, and the scanning lines 111 and 112 are parallel to each other. The first scanning line Ilia is formed by the scanning line 111 extending to the wiring area E2. The common electrode line 121 is formed on the display area E1 of the substrate 110 and interposed between the scanning lines 111 and 112. Then, as shown in step S303, the insulating layer 130 is formed on the substrate 110 and covers a portion of the scan lines 111 and 112, the first scan line 111a and the common electrode line 121 in the wiring region E2, and the insulating layer 130 is not equal. The thickness. 12 1358593

Sanda number: TW3684PA Next, as shown in step S304, a semiconductor layer 155 is formed on the insulating layer 130 and corresponds to the first scan line Ilia. Further, as shown in step S305, a plurality of data lines 113 and 114, a conductive layer 122, and a second scan line 112a are formed. The data lines 113 and 114 are formed in the display area E1 and are vertically interlaced with the scanning lines 111 and 112 and separated by an insulating layer 130. The conductive layer 122 is formed correspondingly on the common electrode line 121 to form the storage capacitor 120, and the conductive layer 122 is separated from the common electrode line 121 by the insulating layer 130. The second scan line 112a is formed over a portion of the first scan line Ilia and is separated from the first scan line 111a by an insulating layer 130. Next, as shown in step S306, the protective layer 160 is formed, and a portion of the protective layer 160 is etched to expose the surface of the partial scan line 112 and a portion of the surface of the second scan line 112a, thereby forming the first via hole 141a. The protective layer 160 is used to insulate dust or moisture. Furthermore, as shown in step S307, the first halogen electrode 141 is formed on the first via hole 141a to electrically connect the second scan line 112a and the scan line 112. The insulating layer 130 of different thicknesses can be obtained by the above-described pixel array substrate manufacturing method. The thickness of the insulating layer 130 between the scan line 111 and the data line 113 is greater than the thickness of the insulating layer 130 of the storage capacitor 120. The thickness of the insulating layer 130 of the wiring region E2 is greater than the thickness of the insulating layer 130 of the storage capacitor 120. Please refer to FIG. 4B, which shows a detailed flowchart of the method for fabricating the pixel array substrate of FIG. 4A. Please also refer to the components of Figures 1 to 3 at the same time. 13 1358593

Sanda number · TW3684PA number. Step S401 of Fig. 4B is the same as step S301 of Fig. 4A, that is, the substrate 110 is provided, and the substrate 110 has the display area E1 and the wiring area E2. Next, in step S402 of FIG. 4B, in addition to the step S302 of FIG. 4A, the gate 151 is preferably formed simultaneously in the display area E1 of the substrate 110, and the gate 151 is electrically connected to the scan line. 111. Further, in step S403 of Fig. 4B, in addition to the step S303 of Fig. 4A, it is preferable to simultaneously form the insulating layer 130 on the gate electrode 151. Next, in step S404 of Fig. 4B, in addition to the step S304 of Fig. 4A, the channel layer 154 is preferably formed simultaneously on the insulating layer 130 and corresponds to the idler 151. Further, in step S405 of Fig. 4B, in addition to the step S305 of Fig. 4A, it is preferable to further form the source 153 and the drain 152 at the same time. The source 153 and the drain 152 are insulated from each other on the channel layer 154, thereby forming a plurality of thin film transistors 150. The source 153 is electrically connected to the data line 113. In addition, in step S406 of FIG. 4B, in addition to the step S306 of FIG. 4A, a portion of the protective layer 160 is preferably simultaneously etched to expose the surface of the portion of the drain 152, thereby forming the second via 140a. . In addition, in step S407 of FIG. 4B, in addition to the step S307 of FIG. 4A, a plurality of second halogen electrodes 140 are preferably simultaneously formed on the display area E1 of the substrate 110, and formed on the second conduction. The hole 140a is covered with a conductive layer 122 to electrically connect the drain 152 and the conductive layer 122. The second halogen electrode 140 is separated from the substrate 110 by an insulating layer 130. 1358593

Erda No.: TW3684PA The above-mentioned pixel array substrate manufacturing method has the same thickness of the insulating layer 13 (). The thickness of the insulating layer 130 between the scan line 111 and the data line 113 is greater than the thickness of the insulating layer 130 between the second pixel electrode 14A and the substrate 110 in the pixel P1. The thickness of the insulating layer 130 between the gate electrode i5l and the gate 152 and the source electrode 153 is greater than the thickness of the insulating layer 130 between the channel layer 154 and the electrode 151. In addition, the thickness of the insulating layer 130 between the gate 151 and the drain 152 and the source 153 is greater than the thickness of the insulating layer 130 of the storage capacitor 12A. In the present embodiment, the insulating layer 130 is etched to adjust the thickness. Referring to Fig. 5, a flow chart for forming an insulating layer according to the first embodiment of the present invention is shown. Please also refer to the component numbers in Figures 1 to 3. First, as shown in step S501, the thickness of the insulating layer 130 insulating layer 130 which is formed to have substantially the same thickness is, for example, 360 nm. Next, as shown in step S502, a portion of the insulating layer 130 is etched, for example, an insulating layer between the etch storage capacitor 12A, the second pixel electrode 140 and the substrate 11A, and between the channel layer 154 and the gate 151. 130, after etching, the thickness of the insulating layer 13 is reduced, for example, substantially less than the original thickness of 36 〇 nm; and the remaining unetched insulating layer is thicker, for example, located in the wiring area E2, the scanning line 1U and the poor Between the feed lines 113 and between the gate 151 and the drain 152 and the source 153' has a thicker insulating layer 13A. Although in the present embodiment, the insulating layer is formed in a different manner to achieve different thicknesses, the insulating layer may be formed to have different thicknesses by forming a plurality of insulating layers or the like. 1358593

Three mil: TW3684PA Second Embodiment This embodiment discloses a method of modulating the thickness of an insulating layer by forming another insulating layer. Referring to Figures 6 and 7, Figure 6 is a cross-sectional view of a wiring area in accordance with a second embodiment of the present invention, and Figure 7 is a cross-sectional view showing a display area in accordance with a second embodiment of the present invention. This embodiment is different from the first embodiment in the insulating layer 230, and the rest of the same points will not be repeated. The insulating layer 230 includes a first insulating layer 230a and a second insulating layer 230b. In this embodiment, the first insulating layer 230a is disposed on the substrate 210 and covers the scan line 211, the gate 251, the common electrode line 221, and the first scan line 21la, and the second insulating layer 230b is formed on the substrate Between the scan line 211 and the data line 213, between the gate 251 and the drain 252, between the gate 251 and the source 253, and between the first scan line 211a and the second scan line 212a, and disposed in the first insulation On layer 230a. Referring to Figure 8, there is shown a flow chart for forming an insulating layer in accordance with a second embodiment of the present invention. Please also refer to the component numbers in Figures 6 and 7. First, as shown in step S801, a first insulating layer 230a having substantially the same thickness is formed, and the thickness of the first insulating layer 230a is, for example, 360 nm. Then, as shown in step S802, the second insulating layer 230b is formed on a portion of the first insulating layer 230a, for example, between the scan line 211 and the data line 213, between the gate 251 and the drain 252, The first insulating layer 230a is between the gate 251 and the source 253 and between the first scan line 21 la and the second scan line 212a. By forming a double-layer insulating layer, between the scan line 211 and the data line 213, between the gate 251 and the drain 252, between the gate 251 and the source 253, and between the first scan line 21 la and the second Scanning 16 ^^8593

The thickness of the insulating layer 230 between the TW3684PA lines 212a is substantially greater than 360 nm. The portion having only the first insulating layer 230a, for example, the storage capacitor 220, the second halogen electrode 240 and the substrate 210, and the channel layer 254 and the gate 251 have a thin insulating layer 230. In this embodiment, the materials of the first insulating layer 230a and the second insulating layer 230b are different to achieve a better insulating effect. However, the first insulating layer 3a and the first insulating layer 230b may be the same material. Further, the modulation of the thickness of the insulating layer may be achieved by combining the above etching, forming a plurality of insulating layers or the like, and is not limited to one of them. The halogen array substrate and the manufacturing method thereof disclosed in the above embodiments of the present invention are insulating layers having different thicknesses, and only some of the advantages are described below: First, the first scan line and the second scan line of the wiring area are overlapped. Separated by a thicker insulating layer to reduce the width of the wiring area. In addition, increasing the thickness of the insulating layer between the first scan line and the second scan line can reduce the parasitic capacitance between the third trace and the second scan line and reduce the resistance and capacitance second, the display area scan line and the (four) line Between the (four) edge layer has a degree of 'how can reduce the delay between the scan line and the data line when the signal is generated, thereby reducing the low capacitance of the scan line and the data line storage capacitor has a thin insulating layer, so The area of the storage capacitor can be relatively lowered, so that the area where the light is not penetrated in the middle and the middle is reduced, and the aperture ratio is increased to achieve high brightness and low power consumption. 17 1358593

Sanda number: TW3684PA Fourth, the insulating layer between the channel layer and the gate of the thin film transistor has a thin thickness to lower the threshold voltage, thereby reducing the driving cost. Fifth, the insulating layer between the gate and the drain and the source of the thin film transistor has a thick thickness to reduce the parasitic capacitance between the gate and the drain and the source. Sixth, the insulating layer between the pixel electrode and the substrate has a thin thickness to increase the efficiency of light penetration through the halogen, thereby increasing the light utilization rate. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 1358593 三达号: TW3684PA [Simple diagram of the drawing] Fig. 1 is a plan view showing the pixel array substrate of the first embodiment of the present invention; and Fig. 2 is a diagram showing the scraping surface along the 1Α·1Α' in Fig. 1 FIG. 3 is a cross-sectional view along the line 1 1·1β in the f 1 diagram; FIG. 1 is a flow chart showing a method of manufacturing the pixel array substrate;

Figure 4 shows the details of the manufacturing method of the halogen array substrate in Fig. 4. (4) According to the date of this issue, the fourth layer of the (4) insulating layer is ^E. |Sj, Fig. 6 FIG. 7 is a cross-sectional view showing a cross-sectional embodiment of a cross-sectional embodiment of a wiring area according to a second embodiment of the present invention. FIG. 7 is a second view of the present invention; and FIG. 8 is a view of the present invention. Second flow chart. [Description of main component symbols] 100: pixel array substrate 110, 210: substrates 111, 112, 211, 212: scanning lines 111a, 211a: first scanning lines 112a, 212a: second scanning lines 113, 114, 213: Data line 1358893

Sanda number: TW3684PA 120, 220: storage capacitors 121, 221: common electrode lines 122, 222: conductive layers 130, 230: insulating layers 140, 141, 240, 241: halogen electrodes 140a, 141a, 240a, 241a: conducting Hole 150: thin film transistor 151, 251: gate 152, 252: drain 153, 253: source 154, 254: channel layer 155, 255: semiconductor layer 160, 260: protective layer 230a: first insulating layer 230b: Second insulating layer E1 · Display area E2: wiring area P1: Alizarin 20

Claims (1)

1358593 Sanda number: TW3684PA X. Patent application scope: 1. A halogen matrix substrate comprising: a substrate having a display area; a halogen array comprising a plurality of parallel scan lines separated by an insulating layer and a plurality of parallel data lines are alternately formed in the display area; and a plurality of storage capacitors are respectively disposed in the pixel array, each of the storage capacitors comprising: a common electrode line disposed on the substrate; and a a conductive layer disposed on the common electrode line and separated from the common electrode line by the insulating layer; wherein the thickness of the insulating layer between each of the scan lines and each of the data lines is greater than each of the conductive layers The thickness of the insulating layer of the storage capacitor. 2. The halogen array substrate according to claim 1, wherein the thickness of the insulating layer between each of the scan lines and each of the data lines is substantially greater than 360 nm, and each of the storage capacitors The thickness of the insulating layer is substantially less than 360 nm. 3. The halogen array substrate according to claim 1, wherein the substrate has a wiring area outside the display area, and the halogen array substrate further comprises: a plurality of first scanning lines, which are set On the substrate of the wiring area, the scanning lines are extended from a portion of the display area; and the plurality of second scanning lines are disposed on a portion of the first scanning lines, and The first scan line is separated by the insulating layer; a semiconductor layer is formed on the insulating layer and formed on the 21st 358593 three-face number: TW3684PA scan line and the portions of the first scan lines interlaced; The protective layer is disposed on a portion of the second scan lines, and the portion of the scan lines does not have the protective layer to expose a portion of the surface of the scan lines ' thereby forming a plurality of via holes (c〇ntacth〇ie); And the plurality of pixel electrodes are formed on the via holes to electrically connect the second scan lines and the scan lines; wherein the thickness of the insulating layer of the wiring region is greater than each of the storage valleys Insulation thickness . 4. The halogen array substrate according to claim 3, wherein the thickness of the insulating layer of the wiring region is substantially greater than 36 〇 nm, and the thickness of the insulating layer of each of the storage capacitors is substantially less than 36. 〇njn. 5. The pixel array substrate of claim 1, wherein the pixel array substrate further comprises: a plurality of pixel electrodes respectively disposed in the pixel array and disposed on the substrate The substrate is separated by the insulating layer; wherein the thickness of the insulating layer between each of the scan lines and each of the data lines is greater than the thickness of the insulating layer between each of the pixel electrodes and the substrate. 6. The pixel array substrate of claim 5, wherein the thickness of the insulating layer between each of the scan lines and each of the data lines is substantially greater than 360 nm' and each of the halogen electrodes and the The thickness of the insulating layer between the substrates is substantially less than 36 〇 nm. 7. The halogen array substrate of claim 1, further comprising a plurality of thin germanium transistors respectively disposed in the pixel array, each 22 1358593 three-number: TW3684PA - the thin film transistors include a gate is disposed on the substrate; a channel layer is disposed on the gate and separated from the gate by the insulating layer; and a drain and a source are insulated from each other And being disposed on the channel layer; wherein the thickness of the insulating layer between the gate and the drain and the source is greater than the thickness of the insulating layer between the channel layer and the gate. 8. The halogen array substrate according to claim 7, wherein the gate layer and the thickness of the insulating layer between the gate and the source are substantially greater than 360 nm, and the channel layer and the gate are The thickness of the insulating layer between is substantially less than 360 nm. 9. The halogen array substrate of claim 7, wherein the thickness of the gate between the gate and the drain and the source is greater than the thickness of the insulating layer of each of the storage capacitors. 10. The halogen array substrate of claim 1, further comprising another insulating layer on each of the scan lines and the insulating layer between the data lines. 11. A method for fabricating a pixel array substrate, comprising: (a) providing a substrate having a display region and a wiring region; (b) forming a plurality of scanning lines, a plurality of first scanning lines, and a plurality of common electrode lines The scan lines are formed on the display area of the substrate, and the first scan lines are extended from the scan lines to the wiring area to form the common electrode lines formed on the base The portion of the material is in between and between the scan lines; 23 1358593 Μϋ3: TW3684PA (C) forms an insulating layer on the substrate and covers portions of the scan lines, located in the wiring The first scan lines and the common electrode lines, and the insulating layers have unequal thicknesses; (d) forming a semiconductor layer on the insulating layer and corresponding to the first scan lines; Forming a plurality of data lines, a plurality of conductive layers, and a plurality of second scan lines, wherein the data lines are formed in the display area, and are vertically interlaced with the scan lines and separated by the insulating layer, each of the conductive lines a layer is formed on a portion of the insulating layer and Each of the common electrode lines is formed to form a storage capacitor, and the second scan lines are formed on a portion of the first scan lines and separated from the first scan lines by the insulation; (f) forming a protective layer, and etching a portion of the protective layer to expose a portion of the surface of the scan lines and a portion of the surfaces of the second scan lines, thereby forming a plurality of via holes; and (g) forming a plurality of first turns The conductive electrodes are electrically connected to the second scan lines and the scan lines; wherein the thickness of the insulating layer between each of the scan lines and each of the data lines is greater than the storage The thickness of the insulating layer of the capacitor, and the thickness of the insulating layer of the wiring region is greater than the thickness of the insulating layer of the storage capacitor. The method for manufacturing a halogen array substrate according to claim 11, wherein the method further comprises: simultaneously forming the plurality of second pixel electrodes on the substrate when the first halogen electrodes are formed And is separated from the substrate by the insulating layer; 24 1358593 ί: TW3684PA wherein: the thickness of the insulating layer between each of the scanning lines and each of the data lines is greater than the second element in each material The thickness of the insulating layer between the electrode and the substrate. The method for manufacturing a pixel array substrate according to claim 5, further comprising: forming a plurality of gates simultaneously in the display region of the substrate when forming the scan lines; In the case of the semiconductor layer, a plurality of channel layers are simultaneously formed on the insulating layer and respectively correspond to the gate electrodes; and the data is mixed with the plurality of sources, and the plurality of sources and the plurality of jade's (four) poles and the Forming a plurality of phase domains on the channel turns, thereby forming a plurality of thin film transistors; wherein each of the gates and the insulating layer between each of the gates and each of the sources The thickness of the insulating layer between each material layer and each of the material layers. U. 专 专 专 专 专 销 专 , , , , , , , 专 专 专 专 专 专 专 专 专 专 专 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 15. The pixel array and substrate manufacturing method of claim 11, wherein the step of forming the insulating layer further comprises: forming the insulating layer of substantially the same thickness on the substrate and covering: And (4) drawing the line, the first scan lines of the riding area and the common electrode lines; and remaining the insulating layer on the common electrode lines. The method for manufacturing a halogen array substrate according to claim 11, wherein the step of forming the insulating layer further comprises: forming a first insulating layer of substantially the same thickness; a plurality of the scan lines on the substrate, the first scan lines and the common electrode lines in the wiring area, and the first insulation forming a second insulating layer on the scan lines of the portion And on the first insulating layer on the first scan lines of the wiring region. 17. The method of fabricating a halogen array substrate according to claim 16, wherein the material of the first insulating layer and the second insulating layer are different. 26