TWI483401B - Thin film transistor and display panel - Google Patents

Description

Thin film transistor and display panel

The present invention relates to a semiconductor element and a panel including the same, and more particularly to a thin film transistor and a display panel including the thin film transistor.

With the advancement of process technology, various types of display applications continue to evolve. In response to the light, thin, short, small, and portable requirements of display applications, next-generation display applications are trending toward curling and portability. At present, the development of flexible display such as flexible electro-phoretic display (flexible EPD) and electronic paper has been paid attention to and researched by the industry. In particular, the design of a thin film transistor that is widely used in a display, its structural design or material selection directly affects the performance of the product.

Generally, the thin film transistor has at least a gate, a source, a drain, and a channel layer, wherein the conductivity of the gate layer can be changed by controlling the voltage of the gate to form a conduction between the source and the drain. (open) or insulated (closed) state. In addition, an ohmic contact layer having an N-type doping or a P-type doping is usually formed on the channel layer to reduce the contact resistance between the channel layer and the source, or between the channel layer and the drain.

However, in a flexible display, when the thin film transistor is repeatedly bent, stress is accumulated in the channel layer and the deep traps of the channel layer are increased, so that the electrical characteristics of the thin film transistor are deteriorated (such as criticality). Voltage drift or turn-off current increases) and even lose performance. Therefore, conventional thin film transistors have problems of poor component characteristics and poor stability in flexible display applications.

The present invention provides a thin film transistor having good electrical characteristics and stability.

The present invention further provides a display panel having good display quality.

The invention provides a thin film transistor disposed on a substrate, including a channel layer, a source and a drain, a buffer layer, a gate and a gate insulating layer. The channel layer includes a plurality of channel units arranged in a first direction. The source and the drain are electrically connected to the channel units respectively to define the channel length direction of each channel unit. The buffer layer is located between the channel elements, and the Young's modulus of the buffer layer is smaller than the Young's modulus of the channel unit. The gate is located above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

In an embodiment of the invention, the source is located on a first side of each channel unit, and the drain is located on a second side of each channel unit, and the first side and the second side are opposite sides, such that each The channel length direction of the channel unit is substantially perpendicular to the first direction.

In an embodiment of the invention, the source includes a plurality of first electrodes, the first electrodes are arranged along the first direction and electrically connected to each other, the drains comprise a plurality of second electrodes, and the second electrodes are along the first Arranged in one direction and electrically connected to each other, and each channel unit is located between the corresponding first electrode and the second electrode.

In an embodiment of the present invention, the buffer layer is disposed at least on a third side and a fourth side of each channel unit, and the third side and the fourth side are opposite sides, and the third side and the fourth side are Parallel to the channel length direction of each channel unit.

In one embodiment of the invention, the gate is located below the channel unit and the source and drain are above the channel unit.

In an embodiment of the invention, the buffer layer covers the source, the drain, the portion of the channel layer, and a portion of the gate insulating layer, and the buffer layer is in contact with the channel unit.

In an embodiment of the invention, the source and the drain are located below the channel unit, the gate is located above the channel unit, and the buffer layer is located above the gate and filled between the channel units.

In an embodiment of the invention, an ohmic contact layer is further disposed between the channel layer and the source, and between the channel layer and the drain.

In an embodiment of the invention, a dielectric layer is further disposed, wherein the source, the dielectric layer, the drain, the channel unit, the gate insulating layer, the gate, and the buffer layer are sequentially stacked on the substrate, wherein each channel unit The sidewalls extend to the source and the drain such that the channel length direction of each channel unit is substantially perpendicular to the substrate.

In an embodiment of the invention, the method further includes a first ohmic contact layer and a second ohmic contact layer, wherein the first ohmic contact layer is disposed between the source and the dielectric layer, and the second ohmic contact layer is disposed on the second ohmic contact layer Between the bungee and the dielectric layer.

In an embodiment of the invention, the Young's modulus of the buffer layer ranges from 0.01 GPa to 50 GPa.

In an embodiment of the invention, the material of the buffer layer comprises benzocyclobutene (BCB).

In an embodiment of the invention, the Young's modulus of the gate is in the range of 0.01 GPa to 50 GPa.

In an embodiment of the invention, the material of the gate includes a metal.

In an embodiment of the invention, the Young's coefficient of the channel unit is in the range of 100 GPa to 500 GPa.

In an embodiment of the invention, the material of the channel unit comprises amorphous germanium, polycrystalline germanium, and oxide.

In an embodiment of the invention, the buffer layer has a thermal expansion coefficient smaller than a thermal expansion coefficient of the channel unit.

The invention further provides a display panel comprising an array substrate, a display medium and an electrode layer. The array substrate includes a plurality of arrays of thin film transistors as previously described. The display medium is disposed between the array substrate and the electrode layer.

In an embodiment of the invention, the display medium comprises a liquid crystal layer, an electrophoretic display film, and an organic light emitting layer.

Based on the above, in the thin film transistor of the present invention, the channel layer includes a plurality of channel units, the buffer layer is located between the channel units, and the Young's modulus of the buffer layer is smaller than the Young's modulus of the channel unit. In this way, when the thin film transistor is bent, the buffer layer located around the channel unit can release the stress accumulated in the channel layer due to the bending, so that the thin film transistor has good electrical characteristics and stability. Therefore, the display panel having the thin film transistor can have good display quality after repeated bending.

The above described features and advantages of the present invention will be more apparent from the following description.

1A is a top plan view of a thin film transistor according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line II' of FIG. 1A, and FIG. 1C is a cross-sectional view taken along line II-II' of FIG. 1A. schematic diagram. In the embodiment, the thin film transistor 100 is electrically connected to the pixel line 100, the data line DL, and the pixel electrode PE, respectively, and is omitted in FIG. 1A. The representation of the pixel electrode PE. Referring to FIG. 1A to FIG. 1C , the thin film transistor 100 of the present embodiment is disposed on a substrate 102 . The thin film transistor 100 includes a channel layer 110 , a source 120 and a drain 130 , and a buffer layer 140 . A gate 150 and a gate insulating layer 160. The gate 150 is electrically connected to the scan line SL, the source 120 is electrically connected to the data line DL, and the drain 130 is electrically connected to the pixel electrode PE via the conductive plug CV. In the present embodiment, the substrate 102 is, for example, adapted to flex in a first direction D1. The substrate 102 is, for example, a flexible substrate such as a plastic substrate or another substrate.

In the present embodiment, the thin film transistor 100 is, for example, a bottom gate thin film transistor. The gate 150 is disposed, for example, on the substrate 102 and under the channel layer 110. The gate insulating layer 160 is disposed, for example, on the substrate 102 to cover the gate 150. The material of the gate 150 is, for example, molybdenum. The material of the gate insulating layer 160 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, niobium carbide or tantalum carbonium oxide.

The channel layer 110 includes a plurality of channel units 112 that are aligned along a first direction D1. In the present embodiment, the channel layer 110 is, for example, disposed on the gate insulating layer 160 above the gate 150. In other words, the channel unit 112 is arranged along the gate insulating layer 160 above the gate 150 along the first direction D1 to form the island-like channel layer 110. The Young's modulus of the channel unit 112 ranges, for example, from 100 GPa to 500 GPa, and the material thereof includes, for example, amorphous germanium, polycrystalline germanium, oxide, and an organic material.

The source 120 and the drain 130 are electrically connected to the channel units 112, respectively, to define a channel length direction D2 of each channel unit 112. In the present embodiment, the source 120 is located, for example, on a first side 112a of each channel unit 112, and the drain 130 is located, for example, on a second side 112b of each channel unit 112, a first side 112a and a second side 112b. The opposite sides are such that the channel length direction D2 of each channel unit 112 is substantially perpendicular to the first direction D1.

In the present embodiment, the source 120 includes, for example, a plurality of first electrodes 122. The first electrodes 122 are aligned along the first direction D1 and electrically connected to each other, and the drain 130 includes, for example, a plurality of second electrodes 132. The second electrodes 132 are arranged, for example, along the first direction D1 and electrically connected to each other, and each channel unit 112 is located between the corresponding first electrode 122 and the second electrode 132. In other words, in the present embodiment, the first electrode 122 and the second electrode 132 are, for example, located on opposite sides of the corresponding channel unit 112 such that the channel length direction D2 of each channel unit 112 is substantially perpendicular to the first direction D1. The first electrodes 122 are electrically connected to each other by, for example, the data lines DL, and the second electrodes 132 are electrically connected to each other by, for example, the capacitor electrodes 174. The capacitor electrode 174, the gate insulating layer 160, and the capacitor electrode 172 constitute a metal-on-insulator-metal (MIM) type storage capacitor, wherein the capacitor electrode 174 is, for example, connected to a common line (not shown). Electrical connection. In the present embodiment, the material of the source 120 and the drain 130 is, for example, a metal, a conductive polymer, an indium tin oxide, and a nanoparticle ink. Among them, the metal includes, for example, titanium, aluminum, molybdenum, copper, gold, and the like. The conductive polymer includes, for example, PEDOT:PSS (Poly(3,4-ethylenedioxythiophene)poly(styrenesulfonate). In an embodiment (not shown), an ohmic contact layer may be further disposed between the first electrode 122 of the source 120 and the channel unit 112, and the second electrode 132 of the drain 130 may be further connected to the channel unit 112. An ohmic contact layer is provided.

The buffer layer 140 is located between the channel units 112, and the Young's modulus of the buffer layer 140 is smaller than the Young's modulus of the channel unit 112. In the present embodiment, the buffer layer 140 covers, for example, the source 120, the drain 130, the partial channel layer 110, and the partial gate insulating layer 160, and the buffer layer 140 is filled between the channel units 112 and located in each channel unit 112, for example. On both sides. In this embodiment, the buffer layer 140 is disposed at least on a third side 112c and a fourth side 112d of each channel unit 112 and is in contact with each channel unit 112, wherein the third side 112c is opposite to the fourth side 112d. On both sides, the third side 112c and the fourth side 112d are parallel to the channel length direction D2 of each channel unit 112. The Young's modulus of the buffer layer 140 ranges, for example, from 0.01 GPa to 50 GPa. In one embodiment, the material of the buffer layer 140 includes, for example, benzocyclobutene (BCB), and the Young's modulus of the buffer layer 140 is, for example, 3 GPa. It is worth mentioning that, in another embodiment, the thermal expansion coefficient of the buffer layer 140 is, for example, smaller than the thermal expansion coefficient of the channel unit 112, wherein the material of the buffer layer 140 includes, for example, benzocyclobutene (BCB), the buffer layer 140. The coefficient of thermal expansion is, for example, between 35 and 60 ppm, and the material of the channel unit 112 includes, for example, amorphous germanium, and the coefficient of thermal expansion of the channel unit 112 is, for example, less than 10 ppm. As a result, when the temperature rises, the buffer layer 140 can apply a compressive stress to the channel unit 112 to compensate for the increase in carrier mobility due to the temperature rise, so that the thin film transistor 100 has stable electrical characteristics.

In particular, in the present embodiment, the source 120 and the drain 130 include, for example, a plurality of electrically connected electrodes 122, 132, respectively, and have the finger structure shown in FIG. 1A, and one of the sources 120. The electrode 122 and one electrode 132 of the drain 130 respectively cover a channel unit 112 (as shown in FIG. 1B). However, in another embodiment, source 120 and drain 130 may have other configurations as well. For example, as shown in FIG. 2A and FIG. 2B, FIG. 2B is a cross-sectional view taken along line II' of FIG. 2A, and FIG. 2C is a cross-sectional view taken along line II-II' of FIG. 2A. In the crystal 100, the source 120 and the drain 130 do not have a finger structure and are each a single block structure, and any one of the source 120 and the drain 130 covers, for example, a plurality of channel units 112. Since the components of the thin film transistor 100 shown in FIG. 2A and FIG. 2B are substantially the same as those of the thin film transistor 100 shown in FIGS. 1A to 1C, reference may be made to the foregoing and will not be described herein.

In the present embodiment, the buffer layer 140 is located on both sides of each channel unit 112, and the Young's modulus of the buffer layer 140 is smaller than the Young's modulus of the channel unit 112. Therefore, when the thin film transistor 100 is bent with the substrate 102, the buffer layer 140 having a smaller Young's modulus will have a larger strain, and thus the stress accumulated in each channel unit 112 can be released. It is possible to avoid the problem that the thin film transistor 100 is deteriorated in electrical characteristics such as a threshold voltage drift or an increase in off current due to bending. In other words, the thin film transistor 100 still has good electrical characteristics after repeated bending.

On the other hand, in the present embodiment, the channel length direction D2 of the channel unit 112 of the thin film transistor 100 is designed to be substantially perpendicular to the bending direction of the substrate 102 (ie, the first direction D1), and the channel unit can be greatly reduced. In the direction of the current, the stress applied to the bending is even caused by the stress caused by the bending, and the stress caused by the bending is hardly accumulated in the channel length direction D2 of the channel unit 112. Therefore, the thin film transistor can maintain good and stable electrical characteristics after repeated bending, and thus has high reliability. Therefore, the thin film transistor is suitable for use in a flexible display panel (such as an electrophoretic display panel, a liquid crystal display panel, and an organic light emitting display panel) to improve the component characteristics and reliability of the flexible display panel.

3A is a top plan view of a thin film transistor according to an embodiment of the present invention, FIG. 3B is a cross-sectional view taken along line II' of FIG. 3A, and FIG. 3C is a cross section taken along line II-II' of FIG. 3A. schematic diagram. In the present embodiment, the thin film transistor 100 is exemplified in the pixel structure. Therefore, the thin film transistor 100 is electrically connected to the scan line SL, the data line DL, and the pixel electrode PE, respectively, and is omitted in FIG. 3A. The representation of the pixel electrode PE. Referring to FIG. 3A to FIG. 3C simultaneously, the thin film transistor 100 of the present embodiment is, for example, a top gate thin film transistor disposed on a substrate 102. The thin film transistor 100 includes a source 120 and a drain 130, a channel layer 110, a gate insulating layer 160, a gate 150, and a buffer layer 140. In the present embodiment, the substrate 102 is, for example, adapted to flex in a first direction D1. The substrate 102 is, for example, a flexible substrate such as a plastic substrate or another substrate.

In the present embodiment, the source 120 and the drain 130 are disposed on the substrate 102 and below the channel layer 110, for example. The source 120 includes, for example, a plurality of first electrodes 122, and the first electrodes 122 are arranged, for example, along the first direction D1 and electrically connected to each other by the data line DL. The drain electrode 130 includes, for example, a plurality of second electrodes 132, and the second electrodes 132 are arranged, for example, along the first direction D1, and the second electrodes 132 are electrically connected to each other by, for example, the capacitor electrodes 174. In the present embodiment, the capacitor electrode 174, the gate insulating layer 160, and the capacitor electrode 172 constitute a metal-on-insulator-metal (MIM) type storage capacitor.

The channel layer 110 includes a plurality of channel units 112 that are aligned along a first direction D1. In the present embodiment, the channel layer 110 is located, for example, above the source 120 and the drain 130 and between the source 120 and the drain 130. In detail, each channel unit 112 is located on the corresponding first electrode 122 and second electrode 132, and the first electrode 122 of the source 120 and the second electrode 132 of the drain 130 are electrically connected to the channel unit 112, respectively. Connected to define the channel length direction D2 of each channel unit 112. In this embodiment, the first electrode 122 of the source 120 and the second electrode 132 of the drain 130 are respectively located on the first side 112a and the second side 112b of the corresponding channel unit 112, and the first side 112a and the second side The side 112b is opposite sides such that the channel length direction D2 of each channel unit 112 is, for example, substantially perpendicular to the first direction D1. The Young's modulus of the channel unit 112 ranges, for example, from 100 GPa to 500 GPa, and the material thereof includes, for example, amorphous germanium, polycrystalline germanium, oxide, and an organic material.

The gate insulating layer 160 is disposed on the substrate 102 to cover the source 120, the drain 130, and the channel layer 110, for example. In the present embodiment, the gate insulating layer 160 is, for example, a patterned gate insulating layer that covers the channel unit 112 and exposes a gap between the channel units 112. The material of the gate insulating layer 160 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, niobium carbide or tantalum carbonium oxide.

The gate 150 is, for example, disposed on the gate insulating layer 160 above the channel layer 110. As shown in FIG. 3B, in the present embodiment, the gate 150 is filled, for example, between the channel units 112. The Young's modulus of the gate is, for example, in the range of 0.01 GPa to 50 GPa, and the material of the gate 150 is, for example, a metal such as molybdenum, aluminum, titanium, copper or gold.

The buffer layer 140 is located between the channel units 112, and the Young's modulus of the buffer layer 140 is smaller than the Young's modulus of the channel unit 112. In the present embodiment, the buffer layer 140 is disposed on the gate 150, for example, to cover the gate 150 and the gate insulating layer 160, and the buffer layer 140 is, for example, filled in between the channel units 112 and located in the third of each channel unit 112. Side 112c and fourth side 112d. In other words, the buffer layer 140 is, for example, disposed at least on the third side 112c and the fourth side 112d of each channel unit 112, wherein the third side 112c and the fourth side 112d are opposite sides, and the third side 112c and the fourth side 112d Parallel to the channel length direction D2 of each channel unit 112. The Young's modulus of the buffer layer 140 ranges, for example, from 0.01 GPa to 50 GPa. In one embodiment, the material of the buffer layer 140 includes, for example, benzocyclobutene (BCB), and the Young's modulus of the buffer layer 140 is, for example, 3 GPa.

In the present embodiment, the buffer layer 140 is located on both sides of each channel unit 112, and the Young's modulus of the buffer layer 140 is smaller than the Young's modulus of the channel unit 112. Therefore, when the thin film transistor 100 is bent with the substrate 102, the buffer layer 140 having a smaller Young's modulus will have a larger strain, and thus the stress accumulated in each channel unit 112 can be released. It is possible to avoid the problem that the thin film transistor 100 is deteriorated in electrical characteristics such as a threshold voltage drift or an increase in off current due to bending. In other words, the thin film transistor 100 still has good electrical characteristics after repeated bending.

On the other hand, in the present embodiment, the channel length direction D2 of the channel unit 112 of the thin film transistor 100 is designed to be substantially perpendicular to the bending direction of the substrate 102 (ie, the first direction D1), and the channel unit can be greatly reduced. In the direction of the current, the stress applied to the bending is even caused by the stress caused by the bending, and the stress caused by the bending is hardly accumulated in the channel length direction D2 of the channel unit 112. Therefore, the thin film transistor can maintain good and stable electrical characteristics after repeated bending, and thus has high reliability. Therefore, the thin film transistor is suitable for use in a flexible display panel (such as an electrophoretic display panel, a liquid crystal display panel, and an organic light emitting display panel, etc.) to improve the component characteristics and reliability of the flexible display panel.

4A is a top plan view of a thin film transistor according to an embodiment of the present invention, FIG. 4B is a cross-sectional view taken along line II' of FIG. 4A, and FIG. 4C is a cross section taken along line II-II' of FIG. 4A. schematic diagram. In the present embodiment, the thin film transistor 100 is used as an example in the pixel structure, and thus the thin film transistor 100 is electrically connected to the scan line SL, the data line DL, and the pixel electrode PE, respectively, wherein FIG. 4A is omitted. The representation of the pixel electrode PE. Referring to FIG. 4A to FIG. 4C simultaneously, the thin film transistor 100 of the present embodiment is, for example, a vertical thin film transistor disposed on a substrate 102. The thin film transistor 100 includes a source 120, a patterned dielectric layer 125, a drain 130, a channel layer 110, a gate insulating layer 160, a gate 150, and a buffer layer stacked on the substrate 102. 140. In the present embodiment, the thin film transistor 100 further includes a first ohmic contact layer 176 and a second ohmic contact layer 178, wherein the first ohmic contact layer 176 is disposed between the source 120 and the patterned dielectric layer 125. The second ohmic contact layer 178 is disposed between the drain 130 and the patterned dielectric layer 125. In the present embodiment, the substrate 102 is, for example, adapted to flex in a first direction D1. The substrate 102 is, for example, a flexible substrate such as a plastic substrate or another substrate.

In the present embodiment, the source 120 is disposed on the substrate 102, for example, and the drain 130 is disposed above the source 120. The drain 130 includes, for example, a plurality of electrodes 132 arranged in the first direction D1 and electrically connected to each other by the conductive plug CV and the pixel electrode PE. A first ohmic contact layer 176, a patterned dielectric layer 125, and a second ohmic contact layer 178 are disposed between the source 120 and the electrode 132 of the drain 130.

The channel layer 110 includes a plurality of channel units 112 that are aligned along a first direction D1. The source 120 and the drain 130 are electrically connected to the channel units 112, respectively, to define a channel length direction D2 of each channel unit 112. In this embodiment, the channel unit 112 is disposed on the electrode 132 of the drain 130 and extends to the sidewall 132a of the electrode 132 of the drain 130 and the sidewall 120a of the source 120 to respectively be opposite to the drain 130 and the source 120. The contact is such that the channel length direction D2 of each channel unit 112 is, for example, substantially perpendicular to the substrate 102.

The gate insulating layer 160 is, for example, a patterned gate insulating layer disposed on the channel unit 112 to cover the channel unit 112. The gate 150 includes, for example, a plurality of electrodes 152 disposed on the gate insulating layer 160 above the corresponding channel unit 112, and the electrodes 152 are electrically connected to each other. The material of the gate insulating layer 160 is, for example, hafnium oxide, tantalum nitride, hafnium oxynitride, niobium carbide or tantalum carbonium oxide. The material of the gate 150 is, for example, molybdenum.

The buffer layer 140 is located between the channel units 112, and the Young's modulus of the buffer layer 140 is smaller than the Young's modulus of the channel unit 112. In the present embodiment, the buffer layer 140 is disposed on the gate 150 to cover the gate 150, the gate insulating layer 160, the drain 130, the source 120, and the substrate 102, and the buffer layer 140 is filled in the channel unit 112, for example. There are located on opposite sides 112c, 112d of each channel unit 112 (as shown in FIG. 4B). The Young's modulus of the buffer layer 140 ranges, for example, from 0.01 GPa to 50 GPa. In one embodiment, the material of the buffer layer 140 includes, for example, benzocyclobutene (BCB), and the Young's modulus of the buffer layer 140 is, for example, 3 GPa.

In the present embodiment, the buffer layer 140 is located on both sides of each channel unit 112, and the Young's modulus of the buffer layer 140 is smaller than the Young's modulus of the channel unit 112. Therefore, when the thin film transistor 100 is bent with the substrate 102, the buffer layer 140 having a smaller Young's modulus will have a larger strain, and thus the stress accumulated in each channel unit 112 can be released. It is possible to avoid the problem that the thin film transistor 100 is deteriorated in electrical characteristics such as a threshold voltage drift or an increase in off current due to bending. In other words, the thin film transistor 100 still has good electrical characteristics after repeated bending.

In particular, although the thin film transistor illustrated in FIGS. 1A to 4C is taken as an example in the above embodiment, the present invention is not limited thereto. In other words, the present invention is also applicable to other configurations. In thin film transistors.

FIG. 5 is a cross-sectional view of a display panel according to an embodiment of the present invention. Referring to FIG. 5 , in the embodiment, the display panel 200 includes an array substrate 210 , a display medium 220 , and an electrode layer 230 . The array substrate 210 includes the thin film transistors 100 (not shown in FIG. 5) as described in the above embodiments, and the thin film transistors 100 are arranged in an array in the array substrate. In this embodiment, the display panel 200 is, for example, adapted to be bent in a first direction D1 (not shown, please refer to the above embodiment), wherein the first direction D1 is, for example, perpendicular to the secondary channel of the thin film transistor 100. The channel length direction D2 of the unit 112 (not shown, please refer to the above embodiment). In the embodiment, the display panel 200 is, for example, a flexible liquid crystal display panel, a flexible electrophoretic display panel, and a flexible organic light emitting display panel.

More specifically, the display panel 200 includes a plurality of different types in accordance with different display modes, film layers, and display media. When the display medium 220 is a liquid crystal layer, the display panel 200 may be a liquid crystal display panel. When the display medium 220 is an electrophoretic display film, the display panel 200 may be an electrophoretic display panel. If the display medium 220 is an organic light emitting layer, the display panel 200 is an organic light emitting display panel (eg, a phosphorescent photoelectric excitation light display panel, a fluorescent photoelectric excitation light display panel, or a combination thereof).

In this embodiment, since the array substrate of the display panel includes the thin film transistor described in the above embodiments, the buffer layer of the thin film transistor can release the stress accumulated in the channel layer due to the bending, so that the thin film transistor is Good and stable electrical characteristics and better reliability can be maintained after repeated bending. Therefore, the display panel of the present embodiment has good electrical characteristics, stability, and reliability, and is suitable for application to a flexible display panel to greatly improve component characteristics and reliability of the flexible display panel.

In summary, in the thin film transistor of the present invention, the buffer layer is disposed at least on both sides of each channel unit, and the Young's modulus of the buffer layer is smaller than the Young's modulus of the channel unit. Therefore, when the thin film transistor is bent along with the substrate, the buffer layer having a smaller Young's modulus will have a larger strain, thereby releasing stress accumulated in each channel unit to avoid thin film electricity. The problem that the crystal has a characteristic such as a critical voltage drift or an increase in the off current due to bending is deteriorated. In other words, the thin film transistor still has good electrical characteristics after repeated bending.

On the other hand, the channel length direction of the channel unit of the thin film transistor is designed to be substantially perpendicular to the bending direction of the substrate, which can greatly reduce the stress that the channel unit is subjected to bending in the current direction, and even the bending station. The induced stress hardly accumulates in the channel length direction of the channel unit. Therefore, the thin film transistor can maintain good and stable electrical characteristics after repeated bending, and thus has high reliability. Therefore, the thin film transistor is suitable for use in a flexible display panel (such as an electrophoretic display panel, a liquid crystal display panel, and an organic light emitting display panel, etc.) to improve the component characteristics and reliability of the flexible display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Thin film transistor

102. . . Substrate

110. . . Channel layer

112. . . Channel unit

112a, 112b, 112c, 112d. . . side

120. . . Source

122, 132, 152. . . electrode

120a, 132a. . . Side wall

125. . . Dielectric layer

130. . . Bungee

140. . . The buffer layer

150. . . Gate

160. . . Brake insulation

172, 174. . . Capacitor electrode

176, 178. . . Ohmic contact layer

200. . . Display panel

210. . . Array substrate

220. . . Display medium

230. . . Electrode layer

CV. . . Conductive plug

D1, D2. . . direction

DL. . . Data line

PE. . . Pixel electrode

SL. . . Scanning line

1A is a top plan view of a thin film transistor according to a first embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line II' of FIG. 1A, and FIG. 1C is taken along line II-II' of FIG. 1A. Schematic diagram of the section.

2A is a top plan view of a thin film transistor according to a first embodiment of the present invention, FIG. 2B is a cross-sectional view taken along line II' of FIG. 2A, and FIG. 2C is a line along line II-II' of FIG. 2A. Schematic diagram of the section.

3A is a cross-sectional view of a thin film transistor according to an embodiment of the present invention, FIG. 3B is a cross-sectional view taken along line II' of FIG. 3A, and FIG. 3C is a cross-sectional view taken along line II-II' of FIG. 3A. .

4A is a cross-sectional view of a thin film transistor according to an embodiment of the present invention, FIG. 4B is a cross-sectional view taken along line II' of FIG. 4A, and FIG. 4C is a cross-sectional view taken along line II-II' of FIG. 4A. .

FIG. 5 is a cross-sectional view of a display panel according to an embodiment of the present invention.

102. . . Substrate

110. . . Channel layer

112. . . Channel unit

112c, 112d. . . side

132. . . electrode

140. . . The buffer layer

150. . . Gate

160. . . Brake insulation

PE. . . Pixel electrode

Claims (32)

A thin film transistor disposed on a substrate, the thin film transistor comprising: a channel layer comprising a plurality of channel units, the channel units being arranged along a first direction to be adjacent to the two adjacent channel units Defining a recess; a source and a drain are electrically connected to each of the channel units to define a channel length direction of each channel unit; a buffer layer is located between the channel units, and The Young's modulus of the buffer layer is smaller than the Young's modulus of each of the channel elements, at least a portion of the buffer layer completely fills the recess; a gate is located above or below the channel layer and overlaps with the channel elements; And a gate insulating layer disposed between the gate and the channel layer. The thin film transistor of claim 1, wherein the source is located on a first side of each of the channel units, and the drain is located on a second side of each of the channel units, the first side and the The second side is opposite sides such that the channel length direction of each of the channel units is substantially perpendicular to the first direction, wherein the source line does not overlap the recess. The thin film transistor according to claim 2, wherein the source electrode comprises a plurality of first electrodes, the first electrodes are arranged along the first direction and electrically connected to each other, and the drain electrode comprises a plurality of a second electrode, the second electrodes are arranged along the first direction and electrically connected to each other, and each of the channel units is located between the corresponding first electrode and the second electrode, and the buffer layer is connected to the channels Unit contact. The thin film transistor according to claim 2, wherein the buffer layer is disposed at least on a third side and a fourth side of each of the channel units, and the third side and the fourth side are opposite sides. And the third side and the fourth side are parallel to the channel length direction of each of the channel units. The thin film transistor of claim 1, wherein the gate is located below the channel unit, and the source and the drain are located above the channel unit. The thin film transistor according to claim 5, wherein the buffer layer covers the source, the drain, a portion of the channel layer and a portion of the gate insulating layer, and the buffer layer is in contact with the channel units. The thin film transistor according to claim 1, wherein the source and the drain are located under the channel unit, the gate is located above the channel unit, and the buffer layer is located above the gate and filled Between these channel units. The thin film transistor according to claim 1, further comprising an ohmic contact layer between the channel layer and the source, and between the channel layer and the drain. The thin film transistor of claim 1, further comprising a dielectric layer, wherein the source, the dielectric layer, the drain, the channel unit, the gate insulating layer, the gate, and the The buffer layer is sequentially stacked on the substrate, wherein each of the channel units extends to the source and the sidewall of the drain such that the channel length direction of each of the channel units is substantially perpendicular to the substrate. The thin film transistor according to claim 9, further comprising a first ohmic contact layer and a second ohmic contact layer, wherein the first ohmic layer The contact layer is disposed between the source and the dielectric layer, and the second ohmic contact layer is disposed between the drain and the dielectric layer. The thin film transistor according to claim 1, wherein the buffer layer has a Young's modulus ranging from 0.01 GPa to 50 GPa. The thin film transistor according to claim 1, wherein the material of the buffer layer comprises benzocyclobutene (BCB). The thin film transistor according to claim 1, wherein the gate has a Young's modulus ranging from 0.01 GPa to 50 GPa. The thin film transistor of claim 1, wherein the material of the gate comprises a metal. The thin film transistor according to claim 1, wherein a Young's modulus of each of the channel units ranges from 100 GPa to 500 GPa. The thin film transistor according to claim 1, wherein the material of each of the channel units comprises amorphous germanium, polycrystalline germanium, and oxide. The thin film transistor according to claim 1, wherein the buffer layer has a thermal expansion coefficient smaller than a thermal expansion coefficient of each of the channel units. A thin film transistor is disposed on a substrate, the thin film transistor includes: a channel layer including a plurality of channel units, the channel units are arranged along a first direction; a source and a drain, respectively The channel unit is electrically connected to define a channel length direction of each channel unit; a buffer layer is located between the channel units, and a Young's modulus of the buffer layer is smaller than a Young's modulus of each channel unit; a gate located above the channel layer and heavy with the channel elements And a gate insulating layer disposed between the gate and the channel layer, the gate insulating layer comprising a plurality of gate insulating patterns, each gate insulating pattern covering an upper surface and a sidewall of each channel unit, to A recess is defined between the adjacent gate insulating patterns, wherein at least a portion of the buffer layer completely fills the recess. The thin film transistor of claim 18, wherein the source is located on a first side of each of the channel units, and the drain is located on a second side of each of the channel units, the first side and the The second side is opposite sides such that the channel length direction of each of the channel units is substantially perpendicular to the first direction, wherein the source line does not overlap the recess. The thin film transistor of claim 19, wherein the source electrode comprises a plurality of first electrodes, the first electrodes are arranged along the first direction and electrically connected to each other, the drain electrode comprising a plurality of And a second electrode, the second electrodes are arranged along the first direction and electrically connected to each other, and each of the channel units is located between the corresponding first electrode and the second electrode. The thin film transistor according to claim 19, wherein the buffer layer is disposed at least on a third side and a fourth side of each of the channel units, and the third side and the fourth side are opposite sides. And the third side and the fourth side are parallel to the channel length direction of each of the channel units. The thin film transistor according to claim 18, wherein the source and the drain are located under the channel unit, the gate is located above the channel unit, and the buffer layer is located above the gate and filled Between these channel units. Such as the thin film transistor described in claim 18, An ohmic contact layer is disposed between the channel layer and the source and between the channel layer and the drain. The thin film transistor according to claim 18, wherein the buffer layer has a Young's modulus ranging from 0.01 GPa to 50 GPa. The thin film transistor according to claim 18, wherein the material of the buffer layer comprises benzocyclobutene (BCB). The thin film transistor according to claim 18, wherein the gate has a Young's modulus ranging from 0.01 GPa to 50 GPa. The thin film transistor of claim 18, wherein the material of the gate comprises a metal. The thin film transistor according to claim 18, wherein a Young's modulus of each of the channel units ranges from 100 GPa to 500 GPa. The thin film transistor according to claim 18, wherein the material of each of the channel units comprises amorphous germanium, polycrystalline germanium, and oxide. The thin film transistor according to claim 18, wherein the buffer layer has a thermal expansion coefficient smaller than a thermal expansion coefficient of each of the channel units. A display panel comprising: an array substrate, wherein the array substrate comprises a plurality of arrays of thin film transistors according to claim 1 or claim 18; a plurality of scan lines; a plurality of data lines, wherein The thin film electro-crystal system is electrically connected to the corresponding scan lines and the data lines respectively; a display medium; and an electrode layer, wherein the display medium is disposed between the array substrate and the electrode layer. The display panel of claim 31, wherein the display medium comprises a liquid crystal layer, an electrophoretic display film, and an organic light emitting layer.