1357130 UMCD-2006-0322 21899twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種互補式金氧半導體元件的製造方法。 疋 【先前技術】 隨著通訊等電子設備發展技術的發展，電晶體的運作 速度愈趨快速。然而，因為受限於電子與電洞在矽通道中 的移動速度，電晶體的應用範圍亦受到限制。 利用通道中機械應力(Mechanical-stress)的控制來改變 電子與電洞在通道中的移動速度，是一種可以克服元件= 小之後所產生之限制的方法。 ’ 習知已有提出利用石夕化鍺(SiGe)蠢晶等材料做為電晶 體源極/汲極區的主要組成之技術。其做法是將基底中預定 形成源極/没極區的部分移除，之後，再利用選擇區域磊晶 技術，回填矽化鍺。以矽化鍺做為源極/汲極區的主要組 成，與矽的材料特性相比較，由於鍺具有較小的電子有效 質量（Electron effective mass)及電洞有效質量（H〇le effective mass) ’因此以矽化鍺形成源極/没極區可增加電 子和電洞的遷移率(Mobility)，進而提升元件的效能。 另一種方法是在電晶體的源極/汲極區的離子植入製 程之後’在進行快速熱回火之前，先在基底上先覆蓋—層 可以提供應力給閘極導電層的應力轉移結構 (Stress-transfer-scheme)，再將應力轉移結構移除，以藉由 應力轉移結構對閘極導電層所產生的應力記憶效應來提升 5 1357130 UMCD-2006-0322 21899twf.doc/n 元件離子的效能(Ion perforrnance)。 )然而，若ώ矽化鍺做為源極/汲極區的主要組成，是楚 力轉移結構技術’元件的離子效能卻無法有效提升。 這是因為應力轉移結構應用在傳統的電晶體元件時， 是在源極/汲極接觸區的離子植入製—程之後，隨即沈積應力 轉移結構。由於源極/汲極接觸區的離子植入製程的能量非 常尚，足以將閘極導電層的多晶矽非晶格化成非晶矽，而 φ 非曰曰矽對於應力轉移結構的應力記憶效應非常好，因此， 在應力轉移結構移除之後，藉由非晶石夕的應力記憶得以提 升元件離子的效能。 然而，以矽化鍺做為源極/汲極區的主要組成時，由於 矽化鍺磊晶製程的溫度高達攝氏7〇〇度至9〇〇度，時間長 達3至4小時，其所產生的熱預算(Thermalbudget)過高^ 因而使得閘極導電層再結晶⑽謂―)成多晶秒。由於 η型通道金氧半電晶體(NM〇s)的源極/汲極接觸區的離子 a人製程*切化聽晶製程之祕行，因此，在形成應 力轉移結構之前，僅會再進行能量較低的源極/汲極延伸區 之離子植入製程。但是，源極/汲極延伸區之離子植入製程 的能量並無法完全將閘極導電層非一晶格化成非晶石夕 此，應力轉移結構對閘極導奄層所能產生記憶應力非常 小，以致無法有效提升元件的離子的效能。 【發明内容】 、明的目的就是在提供一種半導體元件的製造方 法’故切化鍺製㈣熱預算過高所造成之影響， 6 1357130 UMCD-2006-0322 21899twf.doc/n 使閘極導電層可以發揮應力轉移結構對其產生之應力記憶 效應，進而提升元件之離子效能。 、 本發明的又一目的是提供一種互補式金氧半導體元件 的製造方法，以避免矽化鍺磊晶製程的熱預算過高所造成 之影響，使閘極導電層可以發揮應力轉移結構對其產生之 應力5己效應，進而提升元件之離子效能。 本發明提供一種互補式金氧半導體元件的製造方法。首 先，提供一基底，此基底包括一第一區與一第二區。於第—區 的基底中形成-第-導電型金氧半場效電晶體，其包括二 閘，結構與-半導魏合物為主要㈣U描及極區。 於弟二區的基底t形成-第二導賴金氧半場效電晶體， 括二第二閘極結構與—第二源極級極區。之後，在形成第— 電型金氧半場效電晶體之後，進行—預非晶格化離子 植入衣錢第二_第二驗結構之 化。然後，在進行預非晶格化料植入製程之後上=各 =-應力轉移結構。接著，進行快速熱 := 除應力轉移結構。 衣枉乏设，移 造方Ϊΐ'本所述’上述互補式金氧半導體元件的製 場效電晶體的形成方體財—導電型金氧半 分卿成城底上同時 開極結構分別包括十閘極結構與第二 壁。接著，於第二區盘第二=第二開極導電層與—第-間隙 中分別形成-第二導電型源極:極:=== 1357130 UMCD-2006-0322 2J899twf.doc/n 區之第二導電型源極/沒極接觸區之基底，並於其中氷 Ϊ極半導體化合物，以做為第-導電型源極/ 及極接觸區。之後，移除第—區與第二區之第—間_ 爾層周圍的基底中形成-第-導i型雜; / I _£，於弟—區之閘極導電層周圍的基底中形 一 極/汲極延伸區。之後，分別在第—區與第H 極層的側壁形成一第二間隙壁。 依照本發明實施漸述，上駐赋 =卜第-導電型為㈣，第二導電型為：體 化合物層包括矽化鍺。 主且牛V體 依照本發明實施綱述，上述 造方法中，第-導電型為n型，第一 體轉的製 化合物層包括碳化石夕。 第一¥電型為P型，且半導體 =本發明實施靖述，上述簡式金 造方法中，預非晶格化離子植入製 命篮凡件的衣 石申、碳、銻及其組合顺成之族‘原子選自於鍺、 依照本發明實施例所述，上述互補 造方法中，第二源極/汲極區包括 兀件的製 區與一第二導_細_接_，極/祕延伸 植入製程找量小於帛二雜 7料格化離子 能量。 黏及極接觸區之離子植入製程之 依照本發明實施例所述，上駐 造方法中，第二源極/汲極區包括—第二莫體元件的製 區與-第二導電型源極/祕接_， 8 1357130 UMCD-2006-0322 2I899twf.doc/n 植^製程之能量大於第二祕/汲極延伸區之軒植入製程之 能量。 、生太ϊΐ本Γ月實施例所述’上述互補式金氧半導體元件的製 源極/祕區包括—第二導電型祕"及極延伸 雜_接麻，且進行預非日日日格化離子 匕^、程之此塁"於第一源極/汲極延伸區之離子植入製程之 忐罝與第二源極/沒極接觸區之離子植入製 4依照树明實關魏，上紅補式錢的製 k方法中’獅晶格化離子植人製程所使狀原子為錯，且預 非晶格化離子植入製程之能量為5至20KeV。 依照本發明實施麵述’上敍補式錢轉體元件的势 造方法中’應力轉移結構之材冑包括氧化石夕或氮化石夕。九 /本發明提種半導體元件的製造綠，此方法是在基底 中形成-金氧半場效電晶體，其包括―閘極結構與—源^没 極區。之後’進行-預非晶格化離子植入製程，以使開極結構 之-閘極導電層非晶格化。然後，於基底上形成—應力轉移結 構。其後’進行-快速熱回火製程。之後，移除應力轉移結構: 依照本發明實施例所述，上述半導體元件的製造方法中， 預非晶格化離子植入製程所使用之原子選自於鍺、砷、碳、 及其組合所組成之族群。 灭 依照本發明實施例所述，上述半導體元件的製造方法中， 源極/汲極區包括一源極/沒極延伸區與一源極/汲極接觸區，且 進行預非晶格化離子植入製程之能量小於源極/汲極接觸 離子植入製程之能量。 < 9 UMCD-2006-0322 21899twf.doc/n 依照本發明實施例所述，上述半導體元件的製造方 Ϊ極括一源極/沒極延伸區與一源極/汲極接觸ΐ，且 =丁預非Μ娜顿人餘找量纽細 離子植入製程之能量。 、狎£之 依照本發明實施例所述，上述半導體元件的製造 =預ί f化離子植人製程之能量介於祕延伸二 源極級極接_之離子植人餘之能量之間。 - 依照本發明實施例所述，上述半導體元 ==化離子植人餘所使狀原子紐，且難晶格^ 子植入衣程之能量為5至2〇KeV 〇 ^照本發明實施例所述，上述半導體元件的製造方法中， 應力轉移結構之材質包純切或氮化石夕。 依，本發明實施例所述，上辭導體元件的製造方法中， 二^氧半％效電晶體的方法是先在基底上形成閘極結構，其 =閘介電層、—閘極導電層與_第__間隙壁。然後，於基 =形成源極/、及極接觸區。其後，移除第一間隙壁 ，再於 ψ W層周圍的基底中形成—祕/祕延伸區。之後，在 閘極導電層的側壁形成—第二間隙壁。 曰明藉由非晶格化離子植入製程，可避免矽化鍺磊 的熱預算過高所造成之影響，使閘極導電層可以發 =力轉％構其產生之應力記憶效應，進而提升 之離子效能 為讓本發明之上述和其他目的、特徵和優點能更明顯 下文待舉較佳實施例，並配合所附圖式，作詳細說 1357130 UMCD-2006-0322 21899twf.doc/n 明如下。 【實施方式】 圖1是繪示本發明實施例之一種半導體元件之製造方 法流程圖。 請參照圖1，本發明之實施例是先在基底上形成金& 半電晶體，步驟10。當金氧半電晶體製作完成後，進行= 速熱回火製程之前，先進行一預非晶格化離子植义 (Pre-amorphous implantation，PAI)製程，步驟 12，使閘極 導電層非晶格化成非晶矽，以發揮後續沈積之應力轉移結 構對其所產生之應力記憶效應，進而提升元件之離子效 能。預非晶格化離子植入製程所使用之原子選自於鍺、石申>、 碳、銻及其組合驗成之族群。進行預非晶格化離子植入 製程之能量纽雜/祕延㈣與雜/祕接觸區之離 ^入製程之能量之間。然後，在基底上形成應力轉移層， v驟Η，以使應力轉移至閘極導電層。其後，進行快速敎 =火W程’步驟16 ’以使源極你極區的摻雜化。之後， 再將應，力轉移結構移除，步驟18。 本^在進行祕/祕區快 火製程之前，先進 二了預非晶格化離子植人製程，可4使得閘極導電歸晶 :化’而形成應力記憶特倾佳的』晶矽，因此，“力 構絲讀，應力_結構狀祕導喊 仍可記憶於閘極導電層中，以發揮提升離子=之 以下特舉互補式金氧半導體元件之製造流程來說明 π 1357130 UMCD-2006-0322 21899twf.doc/n 之。 卜圖2A至圖2F是依照本發明實施例所繪示之互補式金 氧半導體元件之製造方法的流程剖面示意圖。 首先，凊參照圖2A，提供—基底〗〇〇，此基底1〇〇例 如是單晶矽基底。在基底100中形成隔離結構1〇2，以定 義出主動區104與105。隔離結構1〇2之材質例如是絕緣 材料，例如是氧化矽。隔離結構1〇2的形成方法例如是以 • 在基底10〇令形成溝渠，然後，在基底100上沈積一層絕 緣材料，再以化學機械研磨法移除多餘的絕緣材料。 接著於主動區域104與105内的基底1〇〇上形成閘極 結構110。閘極結構110例如是由閘極介電層1〇6、閉極導 電層108、頂蓋層109與間隙壁112所組成。閘極結構11〇 的形成方法例如是先在基底100上形成一層介電材料層 (未繪示）。介電材料層的材質例如是氧化矽，其形成方法 例如是熱氧化法。然後，在介電材料層上形成一層導體材 Φ 料層（未繪不），以覆蓋住整個基底100。導體材料層的材質 例如是多晶珍或_雜多晶;^，形成方法例如是化學氣相沈 積法。之後，在導體材料層上形成一層頂蓋材料層（未繪 不材質例如是氧化矽或是氮化矽，形成的方法例如是 2學氣相沈積法。接著，進行微影製程與蝕刻製程，以圖 ;、化頂蓋材料層、導體材料層與介電材料層，形成頂蓋層 〇9、導電層108與閘極介電層106。之後，再於頂蓋層1〇9、 閘極導電層108的側壁形成間隙壁112，其材質例^是氧 化矽或氮化矽。之後，進行離子植入製程，在主動區ι〇5 12 1357130 UMCD-2006-0322 21899twf.d〇c/n 與主動區104 t形錢極/⑨極接觸區118 — 中，主動區H)5中預定形成 接齡m之摻雜為η型。在另_實施例中， 中預定形成Ρ型金氧半雷曰髀£ 105 1 m捩雜盔；丨 電日日體（M0S) ’源極/汲極接觸區 $雜為P型。n型摻雜例如是磷 是蝴。在—實例中，_及極接觸區118之“=: 之能量為10至30KeV。 〈雖千植入衣 • 爲罢fi，請參照圖2β，接著’於主動區105上覆苗一 覆蓋-層罩幕材料層在基底_上 上會），然後，再於頂蓋材料層上 f (未繪示)，並以其為蝕刻罩幕，使頂蓋 材料層圖案化，再將圖牵彳卜氺厗土 、 =〇Λ 例如是氧化矽’形成方法例如是高溫熱 乳化=mgh temperature oxide p職ss，ht〇 啊㈣。 移除主動區104之源極/沒極接觸區118之基底 • ΓΠΤ1114,114之中預定形成半導體化合 =’ ^為源極/汲極接觸區。凹槽m的形成方法可以利 用非等向性敍刻製程。 繼之’請繼續參照圖2Β，進行選擇區縣晶製程 (,二 area epitaxy _ ίί 化合物磊晶層並在半導體化合物磊晶層中形成 杉雜，以形成源極/沒極接觸區Η6。 ㈣在一實施例中，主動區105中預定形成η型金氧半電 日日體，源極/汲極接觸區118之摻雜為主動區刚中 13 1357130 UMCD-2006-0322 21899twf.doc/n 預定形成p型金氧半電晶體，源極/汲極接觸區a丨6之半導 體化合物磊晶層例如是矽化鍺層，其摻雜為p型。矽化鍺 的形成方法可以在化學氣相沈積反應室中通入含矽氣體源 例如疋石夕曱院(SiH4)或是二氯石夕甲烧((¾2¾)或是其混合 物、含鍺氣體源如鍺烷(GeH4)、氯化氫(Ηα)以及摻雜 源如硼烷(ΒΗ3)做為反應氣體源，在攝氏7〇〇至9〇〇度的溫 度下，沈積3至4小時。 又狐1357130 UMCD-2006-0322 21899twf.doc/n IX. DESCRIPTION OF THE INVENTION: 1. Field of the Invention This invention relates to a method of fabricating an integrated circuit, and more particularly to the manufacture of a complementary MOS device. method.疋 [Prior Art] With the development of electronic devices such as communication, the operation speed of transistors has become faster. However, because of the limited speed of movement of electrons and holes in the helium channel, the range of applications of the transistor is also limited. The use of mechanical-stress control in the channel to change the speed at which electrons and holes move in the channel is a way to overcome the limitations imposed by the component = small. It has been proposed to use materials such as SiGe sputum (SiGe) stupid crystal as the main component of the electric crystal source/drain region. The method is to remove the portion of the substrate that is intended to form the source/no-polar region, and then use the selective region epitaxial technique to backfill the germanium oxide. Taking bismuth telluride as the main component of the source/drain region, compared with the material properties of bismuth, 锗 has a smaller electron effective mass and H〇le effective mass. Therefore, the formation of source/no-polar regions by bismuth telluride increases the mobility of electrons and holes, thereby improving the performance of components. Another method is to first cover the substrate before the rapid thermal tempering after the ion implantation process of the source/drain region of the transistor. The layer can provide stress to the stress transfer structure of the gate conductive layer ( Stress-transfer-scheme), which removes the stress-transfer structure to enhance the performance of the element ions by the stress memory effect of the stress-transfer structure on the gate conductive layer. 1 1357130 UMCD-2006-0322 21899twf.doc/n (Ion perforrnance). However, if ώ矽 锗 is used as the main component of the source/drain region, the ion performance of the component transfer technology cannot be effectively improved. This is because when the stress transfer structure is applied to a conventional transistor component, the stress transfer structure is deposited immediately after the ion implantation process in the source/drain contact region. Since the energy of the ion implantation process in the source/drain contact region is very good, it is enough to amorphousize the polycrystalline germanium of the gate conductive layer into amorphous germanium, and the stress memory effect of φ non-germanium on the stress transfer structure is very good. Therefore, after the stress transfer structure is removed, the performance of the element ions is enhanced by the stress memory of the amorphous rock. However, when bismuth telluride is used as the main component of the source/drain region, since the temperature of the bismuth telluride epitaxial process is as high as 7 to 9 degrees Celsius and the time is as long as 3 to 4 hours, the resulting The thermal budget (Thermalbudget) is too high^ thus causes the gate conductive layer to recrystallize (10) into a polycrystalline second. Due to the ion-a-manufacturing process of the source/drain contact region of the n-channel gold-oxygen semi-transistor (NM〇s), the secret of the crystal-clearing process is so long that only the stress-transfer structure is formed. Ion implantation process for lower energy source/drain extensions. However, the energy of the ion implantation process of the source/drain extension region cannot completely crystallize the gate conductive layer into amorphous, and the stress transfer structure can generate memory stress on the gate conduction layer. Small enough to effectively improve the performance of the ion of the component. SUMMARY OF THE INVENTION The purpose of the invention is to provide a method for fabricating a semiconductor device, which is caused by the fact that the thermal budget is too high, and the thermal conductivity is too high. 6 1357130 UMCD-2006-0322 21899twf.doc/n The stress memory effect of the stress transfer structure can be exerted to enhance the ion performance of the component. Another object of the present invention is to provide a method for fabricating a complementary MOS device to avoid the influence of excessive thermal budget of the bismuth telluride epitaxial process, so that the gate conductive layer can exert a stress transfer structure to generate it. The stress 5 has an effect, which in turn increases the ion performance of the component. The present invention provides a method of fabricating a complementary MOS device. First, a substrate is provided, the substrate including a first region and a second region. A -first-conducting type gold-oxygen half-field effect transistor is formed in the base of the first region, and includes a second gate, and the structure and the semi-conductive derivative are the main (four) U- and polar regions. The base t of the second district of Yudi forms a second-lead voltaic oxygen half-field effect transistor, including two second gate structures and a second source-level polar region. Thereafter, after the formation of the first electro-type gold oxide half field effect transistor, the pre-amorphous ion implantation ion implantation is performed. Then, after performing the pre-amorphous seeding implantation process, the upper = each = stress transfer structure. Next, perform a rapid heat: = remove the stress transfer structure. The 枉 枉 , , 移 移 移 移 移 移 移 Ϊΐ Ϊΐ Ϊΐ Ϊΐ Ϊΐ Ϊΐ Ϊΐ Ϊΐ Ϊΐ Ϊΐ 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补 互补With the second wall. Then, in the second panel second = second open conductive layer and the - first gap respectively formed - second conductive type source: pole: === 1357130 UMCD-2006-0322 2J899twf.doc / n district A substrate of the second conductivity type source/deion contact region, and an ice-thorbium semiconductor compound therein as a first-conductivity type source/pole contact region. Thereafter, a -th-type i-type impurity is formed in the substrate around the first-to-internal layer of the first region and the second region; /I_£, the base shape around the gate conductive layer of the di-region One pole / bungee extension. Thereafter, a second spacer is formed on the sidewalls of the first region and the second electrode layer, respectively. According to an embodiment of the present invention, the upper resident type is the first conductive type (four), and the second conductive type is: the bulk compound layer includes germanium telluride. The main bovine V body is in accordance with an embodiment of the present invention. In the above method, the first conductivity type is n-type, and the first-body-transformed compound layer includes carbon carbide. The first electric type is a P type, and the semiconductor = the implementation of the present invention, in the above simple gold manufacturing method, the pre-amorphous ionized ion implantation method of the life basket of the stone, carbon, bismuth and combinations thereof In the above complementary method, the second source/drain region includes a region of the component and a second derivative. The polar/secret extension implant process finds less than the amount of argon-doped material. According to an embodiment of the present invention, in the method of the present invention, the second source/drain region includes a region of the second moiré component and a source of the second conductivity type.极/秘接_, 8 1357130 UMCD-2006-0322 2I899twf.doc/n The energy of the planting process is greater than the energy of the second secret/bungee extension zone. According to the embodiment of the present invention, the source/secret region of the above-mentioned complementary MOS device includes the second conductive type secret and the extremely extended miscellaneous entanglement, and the pre-non-day day is carried out. The ion implantation process of the first source/drain extension region and the ion implantation process of the second source/dit electrode contact region Guan Wei, in the method of making red money, the 'lion crystallized ion implantation process' makes the atomic error, and the energy of the pre-amorphized ion implantation process is 5 to 20 KeV. In accordance with the present invention, the material of the stress transfer structure includes a oxidized stone or a nitrite. Nine/The present invention provides for the fabrication of a green component of a semiconductor device in which a gold-oxygen half field effect transistor is formed in the substrate, which includes a "gate structure" and a source region. Thereafter, a pre-amorphous ion implantation process is performed to make the gate conductive layer of the open structure amorphous. Then, a stress transfer structure is formed on the substrate. Subsequent to the - rapid thermal tempering process. Thereafter, the stress transfer structure is removed: In the method for fabricating the above semiconductor device, the atom used in the pre-amorphization ion implantation process is selected from the group consisting of germanium, arsenic, carbon, and combinations thereof. The group of people. According to the embodiment of the present invention, in the method for fabricating a semiconductor device, the source/drain region includes a source/drain extension region and a source/drain contact region, and pre-amorphized ions are performed. The energy of the implant process is less than the energy of the source/drain contact ion implantation process. < 9 UMCD-2006-0322 21899 twf.doc/n According to an embodiment of the invention, the manufacturing method of the above-mentioned semiconductor device includes a source/drain extension region and a source/drain contact ΐ, and = Ding is not the energy of the Nadun people to find the amount of new ion implantation process. According to the embodiment of the invention, the manufacturing of the above-mentioned semiconductor component is between the energy of the ion implantation process and the energy of the ion source. According to the embodiment of the present invention, the semiconductor element==chemical ion implants the atomic atom, and the energy of the difficult crystal lattice implant process is 5 to 2〇KeV. In the above method for manufacturing a semiconductor device, the material of the stress transfer structure is purely cut or nitrided. According to an embodiment of the present invention, in the method for fabricating a conductor element, the method of forming a gate oxide layer is to form a gate structure on the substrate, which is a gate dielectric layer and a gate conductive layer. With _ __ clearance wall. Then, at base = form source/ and contact regions. Thereafter, the first spacer is removed, and a secret/secret extension is formed in the substrate around the ψW layer. Thereafter, a second spacer is formed on the sidewall of the gate conductive layer. Through the amorphous lattice ion implantation process, it can avoid the influence of the high thermal budget of the 矽化锗磊, so that the gate conductive layer can transmit the stress memory effect generated by the force conversion, and then enhance it. The above and other objects, features, and advantages of the present invention will become more apparent from the preferred embodiments of the invention appended <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; [Embodiment] FIG. 1 is a flow chart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, an embodiment of the present invention first forms a gold & semi-transistor on a substrate, step 10. After the gold-oxygen semi-transistor is completed, a pre-amorphous implantation (PAI) process is performed before the = rapid thermal tempering process, and step 12 is performed to make the gate conductive layer amorphous. It is formed into an amorphous yttrium to exert the stress memory effect of the subsequent stress-transfer structure, thereby enhancing the ion performance of the element. The atoms used in the pre-amorphous ion implantation process are selected from the group consisting of yttrium, shishen>, carbon, lanthanum and combinations thereof. The energy of the pre-amorphous ion implantation process is between (4) and the energy of the impurity/secret contact zone. Then, a stress transfer layer is formed on the substrate, so that the stress is transferred to the gate conductive layer. Thereafter, a fast 火 = fire W step is performed to perform the doping of the source region of the source. After that, the force transfer structure is removed, step 18. Before the secret/secret area fast-fire process, the advanced two pre-amorphized ionization implanting process can make the gate conductive and crystallized: and form a crystal memory with good stress and memory. "Structural wire reading, stress _ structural secret shouting can still be memorized in the gate conductive layer, in order to play the lifting ion = the following special complementary MOS device manufacturing process to illustrate π 1357130 UMCD-2006- FIG. 2A to FIG. 2F are schematic cross-sectional views showing a method of fabricating a complementary MOS device according to an embodiment of the invention. First, referring to FIG. 2A, a substrate is provided. The substrate 1 is, for example, a single crystal germanium substrate. An isolation structure 1 2 is formed in the substrate 100 to define active regions 104 and 105. The material of the isolation structure 1 2 is, for example, an insulating material such as hafnium oxide. The isolation structure 1 is formed, for example, by forming a trench on the substrate 10, then depositing a layer of insulating material on the substrate 100, and then removing excess insulating material by chemical mechanical polishing. With 105 A gate structure 110 is formed on the substrate 1 . The gate structure 110 is composed of, for example, a gate dielectric layer 1 , 6 , a gate conductive layer 108 , a cap layer 109 , and a spacer 112 . The method for forming the germanium is, for example, first forming a layer of dielectric material (not shown) on the substrate 100. The material of the dielectric material layer is, for example, tantalum oxide, and the forming method is, for example, thermal oxidation. Then, in the dielectric material layer A layer of conductive material Φ (not shown) is formed thereon to cover the entire substrate 100. The material of the conductive material layer is, for example, polycrystalline or heteropolycrystalline, and the formation method is, for example, chemical vapor deposition. Forming a layer of a capping material on the layer of the conductive material (the unpainted material is, for example, tantalum oxide or tantalum nitride, and the method of formation is, for example, a 2-vapor deposition method. Next, a lithography process and an etching process are performed to The top cover material layer, the conductive material layer and the dielectric material layer form a cap layer 〇9, a conductive layer 108 and a gate dielectric layer 106. Thereafter, the cap layer 1〇9 and the gate electrode are electrically conductive. The sidewall of the layer 108 forms a spacer 112, the material of which is oxidized Or tantalum nitride. After that, an ion implantation process is performed, in the active region ι〇5 12 1357130 UMCD-2006-0322 21899twf.d〇c/n and the active region 104 t-shaped pole/9-pole contact region 118 — In the active region H)5, the doping of the predetermined age m is η-type. In another embodiment, the Ρ-type MOS-type 氧 金 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 M0S) 'The source/drain contact area is P type. The n type doping is, for example, phosphorus is a butterfly. In the example, the energy of "=:" of the _ and the contact region 118 is 10 to 30 KeV. <While thousands of implants ・ For the sake of fi, please refer to Figure 2β, then 'cover on the active area 105 - cover layer of material layer on the substrate _ up), and then on the top cover material layer f (not shown), and use it as an etching mask to pattern the top cover material layer, and then draw the picture, 〇Λ 〇Λ 〇Λ, for example, yttrium oxide 'forming method, for example, high temperature thermal emulsification = Mgh temperature oxide p ss, ht 〇 ah (four). The substrate of the source/depolar contact region 118 of the active region 104 is removed. • The semiconductor compound =' ^ is a source/drain contact region among the ΓΠΤ1114,114. The method of forming the groove m can utilize an anisotropic engraving process. Following the 'please continue to refer to Figure 2Β, select the zone crystallographic process (the second area epitaxy _ ίί compound epitaxial layer and form stellate in the epitaxial layer of the semiconductor compound to form the source/no-polar contact region Η6. In one embodiment, the n-type MOS semi-electric solar field is predetermined to be formed in the active region 105, and the doping of the source/drain contact region 118 is the active region just 13 1357130 UMCD-2006-0322 21899twf.doc/n It is intended to form a p-type MOS transistor, and the epitaxial layer of the semiconductor compound of the source/drain contact region a 丨 6 is, for example, a bismuth telluride layer, which is doped with p-type. The formation of bismuth telluride can be performed in chemical vapor deposition. The reaction chamber is filled with a helium-containing gas source such as 疋石夕曱院 (SiH4) or chlorite ((3⁄423⁄4) or a mixture thereof, a helium-containing gas source such as decane (GeH4), hydrogen chloride (Ηα) And a doping source such as borane (ΒΗ3) is used as a reaction gas source, and is deposited for 3 to 4 hours at a temperature of 7 to 9 degrees Celsius.
在另一實施例中，主動區1〇5中預定形成卩型金氧半 電晶體(PMOS)，源極/汲極接觸區118之摻雜為ρ型·主 動區104中預定形成η型金氧半電晶體(NM〇s)，源極/汲 極接觸區116之半導體化合物蠢晶層例如是石炭化石夕戶，盆 捧雜為η型。In another embodiment, a germanium-type MOS transistor is formed in the active region 〇5, and the doping of the source/drain contact region 118 is a p-type active region 104 in which an n-type gold is formed. The oxygen semi-transistor (NM〇s), the semiconductor compound stray layer of the source/drain contact region 116 is, for example, a fossilized fossil, and the pottery is n-type.
之後’请參照2C，移除罩幕層113,並移除主動區1〇4 與105上之_壁112。其後，再分卿成光阻罩幕並進 行離子植人製程以及口袋_子植人製程，以分別在主動 區104與105的基底100中形成源極/汲極延伸區與口 衣型植入區134以及源極/汲極延伸區122與口袋型植入區 136。源極/没極延伸㉟12〇與源極/汲極接觸⑧ιΐ6構成源 極/汲極區130 ;源極級極延伸區122與源極/没極接觸區 118構成源極/汲極區132。在一實施例中，主動區奶中 預疋形成η型金氧半電晶體’源極/汲極延伸區之摻雜 為η型;主動區刚中預定形成ρ型金氧半電晶體，‘/ 錄延伸區120之摻雜為μ。在另—實施财，主動區 105中預定形成ρ型金氧半電晶體，源極/沒極延伸區⑵ 1357130 21899twf.doc/n UMCD-2006-0322 之杉雜為p型，主動區1〇4中預定形成n型金氧半電晶體， 源極/汲極延伸區120之摻雜為n型。 其後，請參照圖2D，分別在主動區1〇4與105之頂蓋 層與閘極導電層1〇8的側壁上形成間隙壁124。之後π 進仃一預非晶格化離子植入製程126，以使閘極結構11〇 之閘極導電層108非晶格化。預非晶格化離子植入製程126 所使用之原子選自於鍺、坤、碳、銻及其組合所組成之族 群。進仃預非晶格化離子植入製程126之能量介於源極/ 延伸區丨22與源極/汲極接觸區118之離子植入製程之 =里之間。在一實例中，源極/汲極延伸區122之離子植入 赘=之能量為2至4KeV，源極/汲極接觸區118之離子植 入製程之能量10至30KeV，預非晶格化離子植入製程所 使用之原子為鍺’能量為5至2〇Kev。 然後，請參照圖2E，在進行預非晶格化離子植入製程 126之後，於主動區1〇5上形成一應力轉移結構 (streSS-transfe卜scheme)128，以在閘極導電層⑽中產生應 力。應力轉移結構128的形成的方法可以在基底1〇〇上形 成層應力轉移結構材料層，然後，在基底1〇〇的主動區 W5上形成圖案化光阻層，再以圖案化光阻層為蝕刻罩 幕:蝕刻應力轉移結構材料層，留下主動區1〇5上的應力 轉移結構128，之後，再將圖案化光阻層移除之。應力轉 移結構材料層例如是—氮切層或是―氧㈣層，形成的 =去可以採用化學氣相沈積法。之後，再進行快速熱回火 衣矛王(RTA process)’以活化源極/汲極區13〇與132之摻雜。 15 1357130 UMCD-2006-0322 21899twf.doc/n 其後，請參照圖2F，移除應力轉移結構128。移除應 力轉移結構128的方法可以採用等向性蝕刻法，例如是濕 式蝕刻法。當應力轉移結構128之材質為氧化矽時，可以 以氫氟酸或是緩衝氧化蝕刻液田〇£)做為蝕刻液來去除 之。當應力轉移結構128之材質為氮化矽時，可以熱磷酸 做為钱刻液來去除之。Thereafter, please refer to 2C, removing the mask layer 113, and removing the wall 112 on the active areas 1〇4 and 105. Thereafter, the photoresist is formed into a photoresist mask and an ion implantation process and a pocket implant process are performed to form a source/drain extension and a mouth-coat implant in the substrate 100 of the active regions 104 and 105, respectively. Incoming region 134 and source/drain extension 122 and pocket implant region 136. The source/dimpole extension 3512〇 and the source/drain contact 8ιΐ6 constitute a source/drain region 130; the source-level electrode extension region 122 and the source/drain contact region 118 constitute a source/drain region 132. In one embodiment, the doping of the n-type MOS transistor in the active region milk is performed as a n-type doping of the source/drain extension region; a p-type MOS transistor is predetermined in the active region, / The doping of the extension region 120 is μ. In another implementation, the active region 105 is scheduled to form a p-type MOS transistor, and the source/no-polar extension region (2) 1357130 21899twf.doc/n UMCD-2006-0322 is a p-type, active region 1〇 An n-type MOS transistor is predetermined to be formed in 4, and the source/drain extension region 120 is doped n-type. Thereafter, referring to Fig. 2D, spacers 124 are formed on the sidewalls of the top cover layer and the gate conductive layer 1A8 of the active regions 1 and 4, respectively. Thereafter, a pre-amorphized ion implantation process 126 is performed to amorphize the gate conductive layer 108 of the gate structure 11A. The atoms used in the pre-amorphized ion implantation process 126 are selected from the group consisting of ruthenium, ketone, carbon, ruthenium, and combinations thereof. The energy of the pre-amorphized ion implantation process 126 is between the source/extension region 丨22 and the source/drain contact region 118 of the ion implantation process. In one example, the ion implantation potential of the source/drain extension region 122 is 2 to 4 KeV, and the energy of the ion implantation process of the source/drain contact region 118 is 10 to 30 KeV, pre-amorphized. The atom used in the ion implantation process is 锗' energy of 5 to 2 〇 Kev. Then, referring to FIG. 2E, after the pre-amorphization ion implantation process 126 is performed, a stress transfer structure (streSS-transfe) 128 is formed on the active region 1〇5 to be in the gate conductive layer (10). Stress is generated. The method of forming the stress transfer structure 128 may form a layer stress transfer structure material layer on the substrate 1 , and then form a patterned photoresist layer on the active region W5 of the substrate 1 , and then pattern the photoresist layer Etching the mask: etching the layer of stress transfer structure material leaving the stress transfer structure 128 on the active region 1〇5, after which the patterned photoresist layer is removed. The layer of stress-transfer structural material is, for example, a nitrogen-cut layer or an "oxygen (tetra) layer, which can be formed by chemical vapor deposition. Thereafter, a rapid thermal tempering (RTA process) is performed to activate the doping of the source/drain regions 13A and 132. 15 1357130 UMCD-2006-0322 21899twf.doc/n Thereafter, referring to FIG. 2F, the stress transfer structure 128 is removed. The method of removing the stress transfer structure 128 may employ an isotropic etching method such as a wet etching method. When the material of the stress transfer structure 128 is yttrium oxide, it can be removed by using hydrofluoric acid or buffered etch etchant as an etchant. When the material of the stress transfer structure 128 is tantalum nitride, hot phosphoric acid can be used as a money engraving to remove it.
本發明在進行快速熱回火製程之前，先進行了預非t =匕=植人製程，可贿得因衫晶製程熱預算過高; 雜導電料晶格化，而形絲力奸特性扮 ^非晶石夕’因此’應力轉移結構對於閘極導電 ^ 應力，在應力轉移結構移除之後，仍 θ 生 中，以發揮提升離子效能之功效。4於閘極導電， 【圖式簡單說明】 圖1是繪示本發明實施例之—種 法流程圖。 巧體①件之製造:The invention carries out the pre-non-t=匕=planting process before the rapid thermal tempering process, and the bribe can be bribed due to the high thermal budget of the shirt crystal process; the heterogeneous conductive material is latticed, and the shape of the wire is ^Amorphous Shixi's 'stress transfer structure' for the gate conduction stress, after the stress transfer structure is removed, is still in the θ, in order to play the role of improving ion efficiency. 4 is electrically conductive at the gate, [Schematic Description of the Drawings] Fig. 1 is a flow chart showing the method of the embodiment of the present invention. The manufacture of a clever body:
…圖2Α至圖2F是依照本發明實施卜 氧半導體元件之製造方法的流程剖面八土4不之互補式彳 【主要元件符號說明】 不思、圖= 10〜18 :步驟 100 ‘基底 102 .隔離結構 104、105 :主動區 106 :閘介電層 108 .閘極導電層 16 1357130 UMCD-2006-0322 21899twf.doc/n 109 :頂蓋層 110 :閘極結構 112、124 :間隙壁 113 :罩幕層 114 :凹槽Fig. 2A to Fig. 2F are flow diagrams of a method for fabricating an oxygen semiconductor device according to the present invention. The cross-section of the earth is not complementary. [Main element symbol description] No. Fig. 10:18: Step 100 'Base 102. Isolation structure 104, 105: active region 106: gate dielectric layer 108. gate conductive layer 16 1357130 UMCD-2006-0322 21899twf.doc/n 109: cap layer 110: gate structure 112, 124: spacer 113: Mask layer 114: groove
116、118 :源極/汲極接觸區 120、122 :源極/汲極延伸區 126 :預非晶格化離子植入製程 130、132 :源極/汲極區 134、136 : 口袋型植入區 17116, 118: source/drain contact regions 120, 122: source/drain extension 126: pre-amorphized ion implantation process 130, 132: source/drain regions 134, 136: pocket implant Entry area 17