TWI357077B - A pulse width converged method to control voltage - Google Patents

Description

Γ357077 16179twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to controlling a threshold voltage (Vt) by using a pulse width during operation of a plurality of non-volatile multi-level memory cells. The method of distribution, and in particular, relates to a non-volatile multi-order memory unit having two bits per memory cell storage layer. [Prior Art] A non-volatile multi-level memory cell refers to a semiconductor memory type that can still store information without providing power to the memory. Some examples of non-volatile S-resonance units include Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), which can erase read-only reading. Electable Erasable Programmable read-Only

Memory, EEPR〇M). Usually non-volatile memory cell data can be programmed, read and/or erased, and the stylized data can be stored for long periods of time before being erased. Nitrix read only memory (NBit) is a type of data storage using charge trapping. The structure of a NB it unit is like a gold-oxygen half-field effect transistor (metaI_〇xide_si〗 i_ 朽咖淑tmns stor, MOSFET), but the (10) core layer is composed of muse (〇xide-nitride_oxide, oxide _ nitride-oxide layer replaced (SOWOS). The nitrided (tetra) material of the dielectric layer on C)N has the property of capturing charge (electron) in the unit, and the knowledge of the electric charge. The charge localization is that the electric charge does not need to be laterally moved by the fossilized layer. The charge of the nitrided material of the material can be 4 135707? 16179 twf.doc/e, so the charge is independent of the other charges. This element can be contrasted with the "floating gate of *", where the floating gate is guided. . However, the charge is freely and laterally distributed over the entire floating gate, and the charge is transferred by the oxide layer. Stylization of the charge trapping layer in the in-service t-cell (injecting charge) can be performed by various hot carrier injection methods such as channel hot electron injecti〇 (CHE), source-injection (_rce side) Injecti0n ' SSI) or channel initial secondary electron (channei _ mitiated secondary electron (CHISEL) to achieve. Both of these methods involve injecting electrons into the tantalum nitride layer. The localized charge trapping technique allows for two separate charge locations per cell, so the result is twice the memory density per cell. A typical erasure of the NBit unit is achieved by band-t〇-band hot hole tunneling (BTBHHT). The capture operation is implemented either forward or reverse. Reading the NBit unit does not affect the data in the unit. The NB i t unit can be repeatedly programmed, read and erased via known applied electrical techniques. Luyi PHINES memory cell is another type of operation in which charge is stored in non-volatile memory. The structure is also an n-channel MOSFET (S0N0S) with a germanium dielectric layer. . A PHINES memory unit can also use the two physical bits stored to increase the memory density. For PHINES memory cells, techniques such as Fowler-Nordheim (FN) tunneling and inter-band thermal tunneling (BTBHHT) are typically used for erase and stylization operations, respectively. Using FN to erase a PHINES memory unit can maintain self-convergence behavior while maintaining self-convergence without creating 16179twf.doc/e. By using _ technology to reduce the operation: low "n: NEs memory unit program The application of smearing and wiping is quite ideal. / The scorpion is often a complex design of a large number of storage notes. (4) The critical 1 pressure (vt) of the unit is proportional to the amount of charge remaining in the storage layer. When the charge changes, the threshold voltage is ίΐί :: Voltage defines the weight of the multi-level memory wire state corresponding to the programmed state stored in the dragon unit; ===::; The voltage range of T:r corresponds to, =:== = = The specificity of the _ level of the interesting unit = storage, the multiple ranges of the threshold voltage should be borrowed from each other: . Medium: make == quasi: 7 in - clear method. Define the separation from the maternal-level In the unit, the neutrality is too electric ^In addition to the electric / ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Doc/e distribution without generating a wrong pulse width method is used to distinguish different critical powers In order to control the distribution of these threshold voltages, the memory cells are programmed. The prior art method of controlling the critical distribution is more complicated than the present invention. US Patent Publication 帛 632 〇 786 (Changetal^^ / 6219276 ( Parke^ 舆w has a need to use multiple programming霄

j reaches the method of the nucleus of the nucleus, which increases the design complexity, among which the programming is mixed. In addition, a method of using a pulse wave to control the threshold voltage distribution is taught. In particular, the narrower the threshold voltage distribution is used to control the threshold voltage distribution. The invention uses the pulse width rather than the pulse number to control the critical voltage distribution. In addition, U.S. Patent No. 6,396,741 (Bloom et al.) discloses a method for stabilizing non-volatile memory cells by stepping the drain voltage into steps. This approach increases the complexity of the design to control the programming voltage because the voltage is not a fixed value during stylized operation. U.S. Patent No. 6,172,909 (Haddad et al.) discloses a method for making the threshold voltage distribution curve closer in a memory cell. Haddad indicates a software program step method in which the soft step method is used after an erase operation to avoid over-wiping the problem, thus controlling the critical voltage distribution. In addition, Haddad does not control the threshold voltage distribution of each memory cell by varying the programmed pulse width applied to each memory cell. On the contrary, the present invention utilizes the change of the 16 16179 twf.doc / e body unit _ material _ sudden, unexpectedly, the technical means does not consider the _ single two =:; erase the problem 'where the problem is for the memory unit The life cycle has an adverse effect. go with. In particular, 'a plurality of non-volatile multi-level layers. Non-volatile memory two = ^ memory layer level material (Multi_Level Cel1, MIX) ϋ bit charge 'is loaded in the buffer to confirm the programming state - dip, clamp pulse visibility. Two two-dimensional non-volatile memory singles = preferred embodiment for nitriding read-only memory (10) and hot hole injection nitrogen, sub-storage and sputum (pr〇gramming by h〇th〇le injection Nitrogen electron storage, can be stored: two non-volatile memory cells with a charge and a charge have a typical structure 匕 = semi-body base - source region, a drain region, a gate , a first, a charge storage layer and a second oxide layer. The invention provides a first operation (bias) voltage of the solid state at the drain and a fixed second operation < (bias) voltage (four) pole. The operating voltage is a 16179 twf.d〇c/e stylization and erasing operation according to the method of the present invention. This method further includes loading multi-level = memorizing early tc (MLC) data to the buffer, light ML ( : Program programming = and select the pulse width to complete the unit, the operation is stylized or erased. The pulse width of the present invention is used to control the critical power of multiple non-volatile = memory unit Distribution, thus allowing the operation to be accepted. The inventor uses the -set operation (bias), For the above mentioned =, the prior art in which the operation of (four) poles and immersions (and 'in the prior art 曰 'flat circuit power; 1, stylized voltages)) is changed. The 〃 pulse width is also It is used to control the speed of the multi-level memory unit (MLc): the stylized speed of the press. Therefore, the present invention has a constant value for the voltage during operation. Therefore, it is not necessary to control the stylization with complicated circuits to operate. - Simple Wei design can be done to improve the overall efficiency of the invention. Wave width is also used to control another aspect of the invention for controlling the Pro, "hard knife cloth, where a smaller pulse width (eg The short duration f is in the stylized multi-order memory unit (MLC), the intermediate state, and the multi-level memory ^ (MLC) is the state between the lowest state and the highest state. For example, ' The middle state of a two-bit memory is 01 disk 1 (). Therefore, the 'tighter critical voltage distribution can achieve each operation of the multi-level memory cell (MLC). In addition, the control voltage distribution can improve over-stylization. Problems related to over-wiping operations, therefore This method can be made more efficient without applying additional pressure to the memory unit. 1357077 16179twf.doc/e In addition, this method uses a fixed operation power to program and erase multiple multi-level memories. In general, it is simpler to set up the material, and the operation of the US Patent Publication Nos. 6219276 and 632_ is therefore required to be completed, and a more complicated and less efficient design is required. U.S. Patent No. 6,396,741 discloses a Use cloth '' and b; and pole wire (four) non-volatile memory unit threshold voltage points easy to understand his eyes s ": lion rules are more obvious as follows. (four) example 'Asian cooperation, close, say in detail [implementation A pulse width convergence method is used to operate multiple control critical electrical age fabrics. In particular, the invention can also be used in the method of the invention. Moreover, the present invention relates to the operation of a multi-level memory cell unit, wherein the cells are non-swept and erased, and the cells store the charge cells in the stored charge layer (in other words, Data bit). The invention is based on the fact that the itch is changed without changing the operating voltage: =, the critical electric current is controlled during the memory unit is an erasing operation, wherein the stylization is a t-style operation Technology and erasing is a technique for writing data from memory two. The bungee and gate of the memory material are respectively fixed by solid = 2 = 10 1357077 ί6 ΐ 79 twf.doc / e eDonkey. The storage of non-volatile multi-level memory cells misplaces two bits in the layer to define the MLC data, which can be loaded into a coding state and pulse width. This buffer is used to store data in a single field of memory. For example, memory

Llt/Cash 1111111 is used to store in the memory unit. According to the best example of the month, the memory data is first loaded into the buffer and then the visit begins to program the data into the memory unit. The ° memory unit can be programmed to contain more than one electrical level. For example, a second-order memory has a -th, second, and state corresponding to four different programming levels. Each of the voltage levels of the flat domain corresponds to the bits in the binary form, such as 00, 01 10 and 1 , and the number of the strips represents the 3 = _ memory unit. The charge storage layers in the charge are separate and independent: for example, a non-volatile second-order memory cell 5 0V J corresponds to a binary state 〇〇, 〇1,1〇, 11 is about 5.0V, 4 .〇v, 3.0V, 2.0V programming level. The multi-order s-resonance unit of the eight-day-in-white is also in the body unit of the present invention having more than four states (in other words, edited; quasi-state). . In the case of cattle, the 'third-order memory unit has eight f λ —rV packets S from _ to the left, and the gates of the memory cells are first programmed to the left and then the right or the corresponding First, the right bit 7C is followed by the left bit. 11 Γ35Τ0Τ7 -----------------------------------_ 16179twf.doc/e . This pulse width is for operation Controlling the critical voltage distribution during non-volatile multi-level memory cells. In a preferred embodiment of the invention, the pulse width is about 5 nanoseconds (eg, unprogrammed,) to 50 nanoseconds for an NBit unit and is for a PHINES unit. It’s about! Nanoseconds (for example, "unprogrammed,") to between 10 nanoseconds, where for the lowest critical power, §, this method does not program (eg, "unprogrammed") memory cells. In addition, a small _ pulse wave of a stylized pulse wave of a stylized memory cell is defined, wherein the minimum pulse width of the stylized pulse wave is approximated by a software program technique. In terms of operation of a PHINES unit, The erase state is defined at 00, which is a high threshold voltage state so that stylization is not necessary, however, a pulse width of about Ins can be used for stylized operations. The pulse X* degree convergence method is added for multiple The operating efficiency of non-volatile multi-level memory cells - thus increasing the overall operating speed. Moreover, the pulse width. Controls the critical voltage distribution for a specific programming time, where a longer pulse wave develops nine degrees. A larger critical electric house distribution and a shorter pulse width develop a smaller threshold voltage distribution. ^ When there is a memory cell whose programming level has a threshold voltage distribution that is not too large or too small, Next comparison The high level or the next lower programming level can be interpreted as an erroneous representation. In order to prevent such an error from being caused by multiple stages of the read operation, the present invention is programmed/erased. The pulse width is used during stroke to control the threshold voltage distribution, thus providing/better charge margin. This charge margin is the voltage differential between the threshold voltage distributions and is maintained at a minimum in accordance with the method of the present invention. 12 1357077 16179 twf.doc/e' A preferred embodiment of the present invention relates to the operation of a plurality of NBit non-volatile, multi-level memory cells. Figure 1 shows the separation of an NBit cell, wherein the NBlt cell is erased. The state is at a low threshold voltage. The NBit unit includes a semiconductor p-type substrate. The substrate has a first side, a second side and an upper surface. One portion of the substrate has a source region and a drain region. 'Two ^ is n-type, the nuclear pole region is adjacent to the first side, and the source region is adjacent to the second side. Both regions are located below the upper surface of the substrate. The base is below the upper surface - part of the Including one The source region and the drain region are 2 channels. The NBit unit includes a first oxide layer and a charge storage layer and a second oxide layer, wherein the charge storage layer has a first end to store the first charge, the element and the second end To store the second charge bit. The electric f bit of the charge storage layer defines a multi-level memory cell (MLC) data, which is loaded in a slow, hetero-programmed state and sets the pulse width to complete the buffer. • 1 confirmation is based on the state of each memory - the corresponding pulse width. For the Nbit of the low threshold voltage level, the smaller pulse width is defined as the private operation, the program The algorithm is controlled by the memory component. Figure 2 and Figure 3 show the stylized operation of the -NBit memory unit, in which NBit is programmed by using channel hot electron (CHE) to complete a two-terminal program read at one end. In particular, Figure 2 illustrates a first end-pass operation of a memory cell in which the first charge bit is stored in a second pass of the charge storage layer. The privatization operation stores charge cells by conducting charge cells from a first side of the substrate to a second end of the charge storage layer via a conductive path. 13 1357077 16179twf.doc/e • Similarly, Figure 3 illustrates a second end programming operation of the NBit memory cell, wherein the second charge bit is stored at the first end of the charge storage layer by the charge bit The element is conducted from the second side of the substrate to the first end of the stored charge layer via a conductive path. The first and second sides of the substrate are the source and drain regions and the charge from these regions is conducted and stored at either end of the charge storage layer of the NBit non-volatile multi-level memory cell. Figures 4 and 5 further demonstrate the operation of the tp〇r and CHE2NBit φ memory cells, where multi-level memory cell (MLC) data is loaded into the buffer and validated to determine the programming state and programming level. The programming state selects the pulse width to be used, where the programming level is the threshold voltage. Figure 4 illustrates the relationship between programming levels defined as programming states. The programming level is from a low threshold voltage to a high threshold voltage for programming the KNBit unit. Moreover, the convergence of the threshold voltage distribution during unit operation is controlled by the method of the present invention. The present invention utilizes channel hot electron (CHE) technology to provide a flow chart for the two-end programming and one-end reading technique of the NBlt multi-level memory unit. The programming voltage is biased at a fixed voltage level to facilitate stylization. The typical operating voltage for the NBit of the present invention is set to a gate of about 10 VDC and a drain of about 55 VDC. The red data is then loaded into the buffer and acknowledged to determine the programmed state and the pulse width for programming to complete the operation. The programming level and pulse width allow control of different voltage distributions for non-volatile multi-level memory cells at the same-programmed time. In particular, the pulse width is adjusted to control the convergence of the threshold voltage distribution during the ramping time. Therefore, due to the pulse 14

I55707T 16179twf.doc/e Visibility - only changes the parameters that control the critical pre-technical design.兀 季 季 义 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Multi-order sympathy, stylized time, pulse width, and threshold voltage distribution are not shown. For NBit non-volatile multi-order TP, the stylized operation is experimentally: the two usages need to be fixed during operation. Operating voltage (for example, Vg = 10^ Γ ^ 5 · Γ ° ° The curve of Figure 7 shows different pulse widths _ such as μ home microseconds (black dots) and 50 nanoseconds (white dots)) The effect on the formation. In addition, other pulse widths that are the same will result in different critical electric dust distributions (not shown). The second preferred embodiment relates to a plurality of twisting operations: the operation of the memory unit. Figure 8 shows the erased state of a pH-touch non-volatile singularity recall 7G, in which the cut NE ^ state is located at - high critical. The PHI-pumped substrate has a first side, a second side and an upper surface. The base of the substrate has a source region and a _& pole, both of which are shaped, wherein the drain region is adjacent to the first side, the source region is adjacent to the second side, and the base red upper surface is recorded in both regions. Below. The portion of the wire bottom below the upper surface includes a channel between the source region and the drain region. The PHINES unit includes a first-oxide layer and a -f-load storage layer and a second oxygen 15 135707? 16179 twf.doc/e layer. The charge storage layer has a first end to store a first charge level and a second end to a second (fourth) position. The f-bit of the charge storage layer defines a multi-order g'Jt unit (MLC) data that is carried in the buffer and sets the pulse width. Figure 9 and Figure 10 show the stylized operation of the PHINES memory unit, in which PHINES recalls the single-domain (4) (4) hot (BTBHHT) to complete - a two-end program - Tp 〇 R (Tp 〇 R) is =. The other is that Figure 9 demonstrates the operation of the PHINES multi-level memory cell, where the charge bit (hole) is programmed (e.g., stored) at the second end of the stored charge layer. The program operates to store charge by conducting a hole through the conductive path from the first end of the substrate to the second end of the charge storage layer. Similarly, FIG. 10 illustrates a first 操作 operation of a PHINES multi-level memory cell in which a charge bit is conducted from a second end of the substrate to a first end of the charge storage layer by passing a hole through the conductive path. It is stored at the first end of the charge storage layer. The first and second ends of the substrate are the drain and source regions and the charge from these regions is conducted to and stored at any end of the charge storage layer of the non-volatile P& Figure 11 and Figure 12 show the stylization operation of a PHINES memory unit using 1]?11 and BTBHHT, in which multi-level memory unit (MLC) data is used by the PHINES memory unit by using the inter-band thermal tunneling mechanism (BTBHHT). Completing a two-terminal program is programmed by one end read (Tp〇R), which is loaded into the buffer to confirm the programming state and programming level. 16 16179twf.doc/e := Take the pulse width used, where the programming level is the critical connection.关Programming state between the programming level of the ΡΗΙΝΕ ΡΗΙΝΕ / / / — — — — — 低 低 低 低 低 低 低 低 低 低 低 低 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ) == ΡΓΓΡΗΙΝΕ δ multi-level memory unit two-end stylized pressure standard ^ Cheng technology * flow chart. Programming Wit - Fixed electrical touch operation. This documentary es es code fsvoi ed m2 g 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 被 es es es es es es es es es es es Multi-level memory list

Control of different threshold voltage distributions. Special: I is to adjust the degree to control the critical electric house in the same stylized time. Therefore 'because the pulse width is a threshold voltage allowable - a simpler design than the prior art. I ~ Figure 13 and Figure 14 respectively demonstrate the theoretical threshold voltage distribution of the PHINES memory cell. Figure 13 illustrates a pulse width convergence method to control the voltage as a cloth' and shows the effect of a similarly programmed time pulse width on a critical voltage component for a pHINEs non-volatile multi-level memory cell. Figure 14 illustrates the critical electric house 17 16179twf.d〇c/e $= experimentally derived for the PHINES non-volatile multi-level memory cell TPOR-BTBHHT stylization operation. This method requires maintaining a fixed operating voltage during operation (eg, g^io^ and Vd=5 5V). The curves in the figure show the effect of different pulse widths / on the critical voltage distribution. In addition, other pulse widths will result in different threshold voltage distributions under the same stylized operation (not continued). Compared with the prior art method, the pulse width convergence method is used to control the critical point. It provides a more efficient technique, and the less complicated way to perform the forwarding multi-order cell unit stylization and erasing operations. Pulse wave See f method to improve the stylization and smear of non-volatile multi-level memory cells. Furthermore, the pulse width method avoids the problem of over-stylization and over-erase by controlling the threshold voltage margin, thus increasing the data reliability in the memory cell life cycle. It is to be understood that those skilled in the art will be able to make modifications and refinements within 5 pm without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims. Field [Simple description of the diagram] Figure 1 shows the erased state of a two-element non-volatile memory cell at a low threshold voltage. Figure 2 shows a two-bit non-volatile NBit memory unit bit stylized operation. Figure 3 shows a two-bit non-volatile NBit memory bit stylized operation. '"Leyi heart fluff face- Gu Blt programming quasi-(four) boundary voltage distribution and its corresponding code % sorrow. Figure 5 is a flow chart showing the implementation of the two-end stylized one-end read (TPOR) operation of NB丨t using the method of the present invention. 18

Claims (1)

1357077 __ 98-3-31 - X. Application for patent scope: Xiannian! A-day repair (more) is justification 1 . A method of operating a plurality of non-volatile multi-level memory cells, the memory cells having at least a first, second, third, and fourth programming levels, each programming level corresponding to a different one a binary state and having a threshold voltage distribution, the method comprising: (a) maintaining a gate of each memory cell at a fixed operating voltage; (b) changing the pulse width applied to one of the programmed pulse waves of each memory cell to control the threshold voltage distribution of each memory cell. 2. The method of claim 1, wherein the multi-level memory unit is a two-bit memory unit and the four programming levels correspond to binary states 00, 01, 10 and U. ~, as in the method of claim 2, wherein the first, second, third and fourth programming levels are approximately 50 V, 4 〇 v, 2.0 V, respectively. . UVU^ 4. The method of claim 1, wherein the non-volatile memory unit is an NBit unit.乂 5. If the method described in item 4 of the patent application is applied, the ratio is between 5 nanometers and 5G milliseconds. " Pulse width parameter. 6. As described in the scope of the patent application, the order memory unit is a PHINES unit. ...4 Volatile) 7. The method described in claim 6 of the patent application is about 1 nanometer (K) nanoseconds. , , and the width of the middle clutter—8. The money described in item i of the patent scope is obtained by using the two-end stylized-end reading* (TPOR) a formula. In the method described in item 8, a technique selected from the group consisting of channel hot electron (CHE) and inter-band thermoelectric hole penetration = ΤΡ〇 ί ^ (ΒΤΒΗΗΤ) is preferred. 10. In the method of claim 1, the method is - stylized operation. The operator is referred to the method of claim i, wherein one of the methods of operation is an erase operation. U. The method of claim i, wherein the pulse width is in a state intermediate the private multi-level memory unit. 13. The method of claim i, wherein a longer pulse forms a larger threshold voltage distribution - a shorter pulse width is formed - a smaller threshold voltage distribution. —— 〇 21 1357077 v 'year 9r month i〇’1曰7 repair (more) positive 97-10-17 V. Chinese Abstract: A method of making multiple non-volatile multi-level memory cells. The memory cell has at least first, second, third and fourth programming levels. Each programming level corresponds to a different binary state and has a threshold voltage distribution. The operating voltage of each memory cell is maintained constant and the pulse width of the programmed pulse applied to each memory cell is varied to control the threshold voltage distribution of each memory cell. The method of operating on a plural of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels corresponds to a different Binary state and has a voltage threshold distribution. A constant operating voltage is maintained on the memory cells and the voltage threshold distribution of the memory cell is controlled by varying a pulse width of a programming pulse applied to each memory cell. Figure: (1) The representative representative of the case is: Figure (5). (2) Brief description of the symbol of the representative figure: PW: Pulse width VIII. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: None 3