TWI355796B - Operational amplifiers capable of reducing random - Google Patents

Description

1355796 IX. Description of the Invention: [Technical Field] The present invention relates to a method of arranging an operational amplifier, and more particularly to a layout method for improving the error voltage of an operational amplifier. [Prior Art] With the advancement of the integrated circuit process technology, the size of the transistor component is continuously reduced, the amount of impurity impurities in the process is uneven, or (4), the offset of the mask, etc. is applied to the transistor component. The impact is also increasing, leading to a reduction in yield. For the transmission amplifier, the drift of the semiconductor process will cause the transistor in the differential circuit to produce a mismatch (catch), resulting in the generation of the operational amplifier error voltage (rand〇m offset voltage). Fig. 1 'Fig. 1 is a schematic circuit diagram of a conventional operational amplifier 1 。. In general, the conventional operational amplifier 1A has a two-stage circuit structure composed of an input ® stage circuit 11 and an output stage circuit 12. The input stage circuit u is mainly used to increase the gain of the operation (Gain), which includes an N-type differential input pair no, a P-type differential input pair 120, and active loads 13〇, 14〇. Wherein, the N-type differential input pair 110 and the active load 140 are respectively composed of n-type MOS transistors Nb and N3, N4 which are matched with each other; and! The differential input pair ι2〇 and the active load 13〇 are respectively composed of matched P-type MOS transistors P1, P2 & P3, p4. The output stage circuit 12 is mainly used to boost the operational capability of the operational amplifier to drive a capacitive or resistive load connected to the subsequent stage. The details of the conventional operational amplifier 10 1355796 operating principle is well known in the industry, and will not be described here. As mentioned above, the process ignorance causes the transistors in the differential circuit to be mismatched, resulting in the generation of an operational amplifier error voltage. Therefore, for the operational amplifier 10, the components that mainly affect the error voltage are roughly the differential input pair 110 12 〇 and the active loads 13 〇, 14 〇 and the like. However, in the conventional technique, when the operational amplifier 10 is biased, the transistor elements corresponding to the same differential half circuit are generally placed on the same side, for example, when a _type MOS transistor is used for layout. The transistors m, N3 and the transistors N2 and N4 are placed on the same side, respectively, and when the P-type MOS transistor is laid out, the transistors ρι 'Μ and the transistors P2 and P4 are placed respectively. The same side, as shown in Figure 2. In this case, when the semiconductor process is uneven in the same concentration in the same direction, for example, in the X-axis direction in FIG. 2, the differential amplifier is easily caused by the threshold voltage (Thresh〇ld v〇ltage, Vout), etc. A mismatch in the characteristics of the transistor causes an error voltage to be generated. Therefore, the conventional technique must consider the symmetry and consistency of the position of the transistor when laying out the operational amplifier, so that the matching of the transistors in the differential circuit is the same as that of the process factor, and is reduced. The error voltage of the op amp. In general, the conventional technology divides two transistors of the same size into a plurality of transistors in a proportional manner by a common centroid layout, and arranges them in a staggered manner to make the transistors Completely symmetrical in space to achieve precise matching characteristics. 1355796 However, if a conventional common centroid layout method is used, at least two of the number of fingers per fuse (Fingernumber) are required, which will increase the area of circuit layout 0. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to an operational amplifier and related layout method that can improve an error voltage. The present invention discloses an operational amplifier capable of improving an error voltage, comprising a substrate, a --slave pair and a second matched transistor pair. The first matching electrode pair includes a -first transistor and a second transistor. The first transistor and the second transistor are operated in parallel on the wire plate. The pair of matching transistor pairs includes a third transistor and a fourth transistor. The third transistor and the fourth transistor respectively form a diagonal position of the first transistor and the second transistor on the substrate. The first transistor and the third transistor correspond to a second half of the operational amplifier, and the second transistor and the fourth transistor correspond to a second differential of the operational amplifier. Half circuit. This (4) thief to improve the layout of the error voltage of the arbitrage. The operational amplifier includes a -first matching transistor pair and a second matching electrical pair. The first matching transistor pair includes a first transistor and a second transistor, and the second matching transistor pair includes a third transistor and a fourth transistor. The first transistor and the third transistor correspond to one of the first differential half circuits of the operational amplifier, and the second transistor and the fourth transistor correspond to one of the second differential half circuits of the operational amplifier . The layout method includes forming a substrate; forming the first transistor and the second transistor in parallel on the substrate; and forming the third transistor and the fourth transistor on the substrate - the position of the transistor and one of the diagonals of the second transistor. [Embodiment] Please refer to the third embodiment, and FIG. 3 is a schematic diagram of a layout flow 30 for improving an operational amplifier's random offset voltage (Random Offset Voltage). In general, the operational amplifier includes at least a first matching transistor pair and a second matching transistor pair. The first matching transistor pair includes a first transistor and a second transistor that match each other, and the second matching transistor pair includes a third transistor and a fourth transistor that match each other. The first transistor and the third transistor system correspond to one of the first differential half circuits of the implement amplifier, and the second transistor and the fourth transistor correspond to one of the second differential half circuits of the operational amplifier. The layout process 3〇 includes the following steps: Step 300: Start. Step 310: Form a substrate. Step 320: Form a first transistor and a second transistor on the substrate in parallel. Step 330: Form a third transistor and a fourth transistor respectively at positions opposite to one of the first transistor and the second transistor on the substrate. Step 340: End. 1355796: The present invention first determines the position of the first matching transistor pair when laying out the S-amplifier according to the layout flow 30'. Next, the present invention arranges the second matching X-electrode pair, the second transistor, and the fourth transistor to be disposed at opposite corners of the electric body elements corresponding to the same differential half-turn. As a result, in the operational amplifier of the present invention, the 'per-differential half circuit will be affected by the process drift of the degree of marriage, and the operation of the amplification of the messy cake is avoided. In addition, she is in Wei _f^(c_〇n

The layout of CentroKi) is not divided by the present invention. Therefore, the number of gate fingers per finger (Finger_ber) is still equal to one without increasing the area of the circuit. The ferrule-first matching transistor pair and the second matching transistor pair can be the operational amplifier-differential input pair and the wire load. In this case, if the first transistor, the second transistor, the third transistor, and the fourth transistor are all N-type MOS transistors, the differential input of the differential input-type operational amplifier is -N type differential transmission • Active and load the active load of the _p differential input pair of the operational amplifier. Conversely, 'right first-transistor, second transistor, third transistor and fourth electro-crystal system 153⁄4 MOS transistor, the above differential input can be one of the operational amplifiers P-type differential input pair The active load can be the active load of one of the differential input pairs of the operational amplifier. For example, please refer to FIG. 1 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of the circuit layout 40 of the operational amplifier of the present invention. It is assumed that the above-mentioned first matching transistor pair and the second matching transistor pair are respectively used to form an N-type differential input pair ^55796 in the first figure: ^Cs, Ν2&_(4) negative N4, due to electricity The crystals N1, N3, the body pair N3, the moving half circuit, the electric _time l2, the N4 _ mirror are in the same differential tower layout 8 , the present invention will set the transistors N3, N4 respectively (on the substrate) The diagonals of the crystals N1 and N2, the bribes are poorly affected by the process drift _ loudness _, called the error voltage of the low operational amplifier. Her 'P-type MOS semiconductors are arranged in the same way, and the layout pattern is shown in Fig. 4, and will not be described here.

Specifically, if the dimensional error of the transistor component is negligible, the operational amplifier's error voltage Vos can be expressed by:

Ay v°s= —+ Ayth>PX_P2 · gm n ^ Δ ν,ΚΝ,_ΝΛ · g„liNJ + A . ^ 茗"_+茗丨g„um +g(I1/5, , where △〆 ",, (4) 4, △%_" and △ 匕 condition 4 represent the threshold voltage difference between the transistors ni and N2, the transistors N3 and N4, the transistors pi and P2, and the transistors ι > 3 and p4, respectively ^ And %4; and U, 〜ΡΙ, 仏(10), and g(10) represent the transduction values of the transistors N1, pl, N3, and p3, respectively. If the N-type MOS transistor is separated from the p-type MOS transistor To consider, the above formula can be further expressed as:

△ K -gm„ ^ AFW2 -g.,,, +AK ,xr S,n^' +Sm,Pl gm,m +gr〇S,N + Vn^ D "/,中'?'# and The households respectively represent the error voltages contributed by the ^-type MOS transistor and the 卩-type MOS transistor. (S) 10 1355796 Therefore, for the N-type MOS electrode, the doping concentration state, (4) t: r to Λ r / i_, l (htN \ - N2 too Γ 4 > ΰ < G and ~ one and so on. Fine, by △ 匕 Qin " 2 > 0 and △ % - 〆 0, or this t The layout pattern of Figure 4 will produce △Κι,"丨-"2 < 0 and △匕Ny~NA >〇

Obviously, the magnitude of the error voltage contributed by the 'wide N-type MOS transistor' is the same as the error _ size of the 布 关 骑 四. _ It can be seen that for the error/size 10(10)丨 contributed by the p-type total milk+conductor transistor, the layout of Fig. 4 = the size of the county to be produced, and the magnitude of the error voltage generated in the layout _ of Fig. 2. Therefore, the circuit layout 4 of the present invention can obtain a small error voltage Vos. In summary, the present invention places the transistor elements corresponding to the same differential half circuit in a diagonal direction, so that each-differential half circuit is affected by the process drift, and the operation amplification is avoided. produce. Further, this (4) depends on the division of the transistor (10). Therefore, the number of fingers per per-crystal element is still equal to one without increasing the area of the circuit. The above-mentioned households are the preferred embodiments of the present invention, and all changes and modifications made by the scope of the present invention should be within the scope of the present invention.丄乃5796 [Simple description of the diagram] Figure 1 is a schematic diagram of the circuit of a conventional operational amplifier. Figure 2 is a schematic diagram of one of the circuit layouts of a conventional operational amplifier. The 3rd is the hair _ New Shan - County County, the light of the county - layout flow spear master's thinking. Figure 4 is a schematic diagram of the circuit layout of the operational amplifier of the present invention.

[Major component symbol description] Operational amplifier wheel-in stage circuit output stage circuit 110 120 130, 140 N-type differential input pair P-type differential input active load m, N2, N3, N4 N-type gold gas semiconductor transistor P P2, P3, P4 P-type MOS transistor 30 layout process 300, 310, 320, 330 Step 40 Circuit

(S 12

Claims (1)

Correction of replacement 寅, patent application scope on August 17, 100: The operational amplifier amp that has improved the error voltage (Random Offset Voltage) includes: a substrate; a first matching transistor pair, including a first transistor and a first a second transistor, the first transistor and the second transistor are formed in parallel on the substrate; and a second matching transistor pair includes a third transistor and a fourth transistor, the third transistor and The fourth transistor respectively forms a position of a diagonal of the first transistor and the second transistor on the substrate; wherein the first transistor and the third transistor correspond to one of the operational amplifiers. a differential half circuit, and the second transistor and the fourth transistor correspond to a second differential half circuit of one of the operational amplifiers. Such as the request item! The operational amplifier, the pair of the first matching transistor pair and the far second matching transistor pair respectively form a differential input pair and an active load of the operational amplifier. The operation is as described in claim 2, wherein the first transistor, the second transistor, the second transistor, and the fourth transistor system are N-type MOS transistors. The operational amplifier of claim 3, wherein the differential input pair is a differential input pair, and the active age-N differential input is active. 1355796 5. 运算 6. The operational amplifier of claim 5, wherein the differential wheel is coupled to a p-type differential input pair and the active load is a p-type differential input pair active load. The operational amplifier of claim 1, wherein the first transistor, the second electrode H transistor, and the fourth transistor have the same gate direction. 8. A layout method for improving an error voltage of an operational amplifier, the operational amplifier comprising a first matching transistor pair and a second matching transistor pair, the first matching transistor The pair includes a first transistor and a second transistor, the second matching transistor pair includes a body B and a fourth transistor, and the first transistor and the third transistor are a first-differential half circuit of the operational amplifier, the second transistor and the fourth fourth transistor corresponding to the second differential half circuit of the operational amplifier, the layout method comprising: forming a substrate; a transistor and the second transistor are formed on the substrate in parallel; and the second transistor and the fourth transistor are divided into a diagonal of the first transistor and the second transistor on the substrate s position. 14 Aug. 17, the local method, wherein the first matching transistor pair and the differential input pair and the matched-optical transistor are divided into an active load of the operational amplifier. a crystal, the third transistor, and the fourth electric=two ha:= the layout method of claim H), wherein the differential input pair is a (four) differential input pair, and the active load system _N The type of differential input is the active load. The layout method of claim 9, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor system P-type semiconductor transistor 0 are arranged as described in claim 12 The method 'where the differential input pair is a p-type differential input pair, and the active load is a P-type differential input pair active load. The layout method of claim 8, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor have the same gate direction. 1355796 10 11 August 17, 100 revised replacement page 12 factory L 11〇~丨Η 120· Figure 1 1355796 Ρ2 Ρ4 γ A —^ X Figure 2 1355796 320 330 Figure 3 S 1355796 Y —^ X Figure 4