TWI355796B - Operational amplifiers capable of reducing random - Google Patents
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1355796 九、發明說明: 【發明所屬之技術領域】 ,本發明係指一種運算放大器之佈局方法,尤指一種用來改善運 算放大器之誤差電壓(Random Offset Voltage)的佈局方法。 【先前技術】 ,隨著積體電路製程技術的進步,電晶體元件尺寸不斷地縮減, _ 製程中不均勻的雜質參雜量,或㈣、光罩等步驟上的偏移對電 晶體元件所造成的影響也越來越大,而導致良率的降低。對於運 异放大器來說,半導體製程上的飄異會使得差動電路中電晶體產 生不匹配(Μ腦atch )的情況,而造成運算放大器誤差電壓(rand〇m offset voltage)的產生 ° 凊參考第1圖’第1圖係一習知運算放大器1〇之電路示意圖。 一般來說,習知運算放大器1〇具有兩級之電路結構,其由一輸入 ® 級電路11及一輸出級電路12所組成。輸入級電路u主要用來提 $運算放大斋的增ϋ (Gain) ’其包含有一 N型差動輸入對no、 一 P型差動入對120及主動負載13〇、14〇。其中,N型差動輸入 對110及主動負載140分別由互相匹配之n型金氧半導體電晶體 N卜N2及N3、N4所組成;而!》型差動入對ι2〇及主動負載13〇 分別由互相匹配之P型金氧半導體電晶體P1、P2&P3、p4所組 成。輸出級電路12則主要用來提升運算放大器的驅動能力,以驅 > 動後級連接之電容性或是電阻性負載。習知運算放大器10之詳細 1355796 運作原理係為業界所熟知,在此不贅述。 如前所述,製程上_異會使得差動電路中之電晶體產生不 匹配的情況,而造成運算放大器誤差電壓的產生。因此,對於運 算放大器10來說’主要影響誤差電壓之元件大致為差動輸入對 110 12〇及主動負載13〇、14〇等元件。然而,習知技術在對運算 放大器10進行佈力時,一般會將對應於同一差動半電路之電晶體 • 元件擺放於同-側,例如_型金氧半導體電晶體進行佈局時, 會分別將電晶體m、N3及電晶體N2、N4擺放於同-側,而對P 型金氧半導體電晶體進行佈局時,會分別將電晶體ρι 'Μ及電晶 體P2、P4擺放於同一側,如第2圖所示。在此情形下,當半導體 製程在同方向之參雜濃度不均勻時,例如第2圖中之X軸方向, 運异放大器很容易因門榧電壓(Thresh〇ld v〇ltage,V出)等電晶體 特性的不匹配,造成誤差電壓的產生。 因此,習知技術在對運算放大器進行佈局時,必須考量電晶體 擺放位置的對稱性及一致性,以使差動電路中互相匹配之電晶體 义到‘程因素影響的程度相同,而降低運算放大器的誤差電壓。 一般來說’習知技術係藉由共同質心(Common Centroid)的佈局 方式,將兩個相同尺寸的電晶體等比例地切割成複數個電晶體, 並以交錯方式進行排列,以使電晶體在空間中完全對稱,進而達 到精確的匹配特性。 1355796 然而,若使用傳統的共同質心佈局方法,每一電晶體的間極指 數目(Fingernumber)至少需要兩個以上,如此將會使電路佈局0 的面積增加。 【發明内容】 因此,本發明即在於提供一種可改善誤差電壓之運算放大器及 相關佈局方法。 °° 本發明係揭露-種可改善誤差電壓之運算放大器,其包含有一 基板、-第-随電晶體對及-第二匹配電晶體對。該第一匹配 電^體對包含有-第—電晶體及—第二電晶體。該第—電晶體及 雜二電晶體平行職於絲板上。糾二匹配電晶體對包含有 一第三電晶體及第四電晶體。該第三電晶體及該第四電晶體分別 形成該基板上該第一電晶體及該第二電晶體之—對角的位置。其 中,該第一電晶體及該第三電晶體對應於該運算放大器之一第二 ^動半電路,而該第二電晶體及該第四電晶體對應於該運算放大 器之一第二差動半電路。 本發㈣賊來改善放Μ之誤差電壓的佈局 曰法。該運算放大器包含有-第—匹配電晶體對及—第二匹配電 二體對。該第-匹配電晶體對包含有—第—電晶體及—第二電晶 ^而該第二匹配電晶體對包含有—第三電晶體及—第四電晶 —。該第-電晶體及該第三電晶體對應於該運算放大器之一第一 差動半電路’而該第二電晶體及該第四電晶體對應於該運算放大 器之一第二差動半電路。該佈局方法包含有形成-基板;將該第 一電晶體及該第二電晶體平行形成於該基板上;以及將該第三電 晶體及該第四電晶體分獅成於該基板上該第—電晶體及該第二 電晶體之一對角的位置。 【實施方式】 請參考第3爾,第3圖為本發明用來改善一運算放大器之誤差 電壓(Random Offset Voltage)之一佈局流程30之示意圖。一般 來說,運异放大器至少包含有一第一匹配電晶體對及一第二匹配 電晶體對。第一匹配電晶體對包含有互相匹配之一第一電晶體及 一第二電晶體,而第二匹配電晶體對包含有互相匹配之一第三電 晶體及一第四電晶體。其中,第一電晶體及第三電晶體係對應於 運具放大器之一第一差動半電路,而第二電晶體及第四電晶體則 對應於運算放大器之一第二差動半電路。佈局流程3〇包含有以下 步驟: 步驟300 :開始。 步驟310 :形成一基板。 步驟320 :將第一電晶體及第二電晶體平行形成於該基板上。 步驟330 :將第三電晶體及第四電晶體分別形成於該基板上第 一電晶體及第二電晶體之一對角的位置。 步驟340 :结束。 1355796 : 根據佈局流程30 ’當對S算放大器進行佈局時,本發明首先決 定第匹配電晶體對之位置。接著,本發明對第二匹配X電晶體對、 中之第二電晶體及第四電晶體進行配置’錢對應於相同差動半 黾路之電曰曰體元件擺放於對角。如此一來,在本發明運算放大琴 中’每-差動半電路將會受到姻程度的製程飄移影響,而避免 運算放大雜差糕的產生。此外,她於魏_f^(c_〇n1355796 IX. Description of the Invention: [Technical Field] The present invention relates to a method of arranging an operational amplifier, and more particularly to a layout method for improving the error voltage of an operational amplifier. [Prior Art] With the advancement of the integrated circuit process technology, the size of the transistor component is continuously reduced, the amount of impurity impurities in the process is uneven, or (4), the offset of the mask, etc. is applied to the transistor component. The impact is also increasing, leading to a reduction in yield. For the transmission amplifier, the drift of the semiconductor process will cause the transistor in the differential circuit to produce a mismatch (catch), resulting in the generation of the operational amplifier error voltage (rand〇m offset voltage). Fig. 1 'Fig. 1 is a schematic circuit diagram of a conventional operational amplifier 1 。. In general, the conventional operational amplifier 1A has a two-stage circuit structure composed of an input ® stage circuit 11 and an output stage circuit 12. The input stage circuit u is mainly used to increase the gain of the operation (Gain), which includes an N-type differential input pair no, a P-type differential input pair 120, and active loads 13〇, 14〇. Wherein, the N-type differential input pair 110 and the active load 140 are respectively composed of n-type MOS transistors Nb and N3, N4 which are matched with each other; and! The differential input pair ι2〇 and the active load 13〇 are respectively composed of matched P-type MOS transistors P1, P2 & P3, p4. The output stage circuit 12 is mainly used to boost the operational capability of the operational amplifier to drive a capacitive or resistive load connected to the subsequent stage. The details of the conventional operational amplifier 10 1355796 operating principle is well known in the industry, and will not be described here. As mentioned above, the process ignorance causes the transistors in the differential circuit to be mismatched, resulting in the generation of an operational amplifier error voltage. Therefore, for the operational amplifier 10, the components that mainly affect the error voltage are roughly the differential input pair 110 12 〇 and the active loads 13 〇, 14 〇 and the like. However, in the conventional technique, when the operational amplifier 10 is biased, the transistor elements corresponding to the same differential half circuit are generally placed on the same side, for example, when a _type MOS transistor is used for layout. The transistors m, N3 and the transistors N2 and N4 are placed on the same side, respectively, and when the P-type MOS transistor is laid out, the transistors ρι 'Μ and the transistors P2 and P4 are placed respectively. The same side, as shown in Figure 2. In this case, when the semiconductor process is uneven in the same concentration in the same direction, for example, in the X-axis direction in FIG. 2, the differential amplifier is easily caused by the threshold voltage (Thresh〇ld v〇ltage, Vout), etc. A mismatch in the characteristics of the transistor causes an error voltage to be generated. Therefore, the conventional technique must consider the symmetry and consistency of the position of the transistor when laying out the operational amplifier, so that the matching of the transistors in the differential circuit is the same as that of the process factor, and is reduced. The error voltage of the op amp. In general, the conventional technology divides two transistors of the same size into a plurality of transistors in a proportional manner by a common centroid layout, and arranges them in a staggered manner to make the transistors Completely symmetrical in space to achieve precise matching characteristics. 1355796 However, if a conventional common centroid layout method is used, at least two of the number of fingers per fuse (Fingernumber) are required, which will increase the area of circuit layout 0. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to an operational amplifier and related layout method that can improve an error voltage. The present invention discloses an operational amplifier capable of improving an error voltage, comprising a substrate, a --slave pair and a second matched transistor pair. The first matching electrode pair includes a -first transistor and a second transistor. The first transistor and the second transistor are operated in parallel on the wire plate. The pair of matching transistor pairs includes a third transistor and a fourth transistor. The third transistor and the fourth transistor respectively form a diagonal position of the first transistor and the second transistor on the substrate. The first transistor and the third transistor correspond to a second half of the operational amplifier, and the second transistor and the fourth transistor correspond to a second differential of the operational amplifier. Half circuit. This (4) thief to improve the layout of the error voltage of the arbitrage. The operational amplifier includes a -first matching transistor pair and a second matching electrical pair. The first matching transistor pair includes a first transistor and a second transistor, and the second matching transistor pair includes a third transistor and a fourth transistor. The first transistor and the third transistor correspond to one of the first differential half circuits of the operational amplifier, and the second transistor and the fourth transistor correspond to one of the second differential half circuits of the operational amplifier . The layout method includes forming a substrate; forming the first transistor and the second transistor in parallel on the substrate; and forming the third transistor and the fourth transistor on the substrate - the position of the transistor and one of the diagonals of the second transistor. [Embodiment] Please refer to the third embodiment, and FIG. 3 is a schematic diagram of a layout flow 30 for improving an operational amplifier's random offset voltage (Random Offset Voltage). In general, the operational amplifier includes at least a first matching transistor pair and a second matching transistor pair. The first matching transistor pair includes a first transistor and a second transistor that match each other, and the second matching transistor pair includes a third transistor and a fourth transistor that match each other. The first transistor and the third transistor system correspond to one of the first differential half circuits of the implement amplifier, and the second transistor and the fourth transistor correspond to one of the second differential half circuits of the operational amplifier. The layout process 3〇 includes the following steps: Step 300: Start. Step 310: Form a substrate. Step 320: Form a first transistor and a second transistor on the substrate in parallel. Step 330: Form a third transistor and a fourth transistor respectively at positions opposite to one of the first transistor and the second transistor on the substrate. Step 340: End. 1355796: The present invention first determines the position of the first matching transistor pair when laying out the S-amplifier according to the layout flow 30'. Next, the present invention arranges the second matching X-electrode pair, the second transistor, and the fourth transistor to be disposed at opposite corners of the electric body elements corresponding to the same differential half-turn. As a result, in the operational amplifier of the present invention, the 'per-differential half circuit will be affected by the process drift of the degree of marriage, and the operation of the amplification of the messy cake is avoided. In addition, she is in Wei _f^(c_〇n
CentroKi)的佈局方^ ’⑽本發明不彡麟電晶航件進行分割, % 因此每一電晶體元件之閘極指數目(Finger_ber)仍然等於一, 而不會增加電路的面積。 車乂佳地’第-互相匹配之電晶體對及第二互相匹配之電晶體對 可以是運算放大器之-差動輸人對及—絲負載。在此情形下, 若第-電晶體、第二電晶體、第三電晶體及第四電晶體皆N型金 氧半導體電晶體,上述差動輸人對係運算放大器之-N型差動輸 •入對而主動貞載係運算放大器之_p型差動輸人對的主動負載。 相反地’右第-電晶體、第二電晶體、第三電晶體及第四電晶體 係15¾金氧半導體電晶體,上述差動輸人细彳可以是運算放大器 之一P型差動輸入對,而主動負載則可以是運算放大器之一 差動輸入對的主動負載。 舉例來說’請同時參考第1圖及第4圖,第4圖為本發明運算 放大器之-電路佈局40之示意圖。假設上述第—匹配之電晶體對 及第二匹配之電晶體對分別為第1圖中用來形成N型差動輸入對 ^55796 :之電晶雜ι、Ν2&_㈣負請 N4,由於電晶體N1、N3 曰體對N3、 動半電路,·於電_時l2、N4 _镜於相同之差 电塔佈局8守,本發明會將電晶體N3、N4分別 設置於(基板上)電晶體N1、N2之對角,贿每—差 受到製程飄移_響程度_,叫低運算放大器的誤差電壓。 類她’P型金氧半導體電晶财以相同方式進行佈局,其佈局圖 案如第4圖所示,於此不贅述。The layout of CentroKi) is not divided by the present invention. Therefore, the number of gate fingers per finger (Finger_ber) is still equal to one without increasing the area of the circuit. The ferrule-first matching transistor pair and the second matching transistor pair can be the operational amplifier-differential input pair and the wire load. In this case, if the first transistor, the second transistor, the third transistor, and the fourth transistor are all N-type MOS transistors, the differential input of the differential input-type operational amplifier is -N type differential transmission • Active and load the active load of the _p differential input pair of the operational amplifier. Conversely, 'right first-transistor, second transistor, third transistor and fourth electro-crystal system 153⁄4 MOS transistor, the above differential input can be one of the operational amplifiers P-type differential input pair The active load can be the active load of one of the differential input pairs of the operational amplifier. For example, please refer to FIG. 1 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of the circuit layout 40 of the operational amplifier of the present invention. It is assumed that the above-mentioned first matching transistor pair and the second matching transistor pair are respectively used to form an N-type differential input pair ^55796 in the first figure: ^Cs, Ν2&_(4) negative N4, due to electricity The crystals N1, N3, the body pair N3, the moving half circuit, the electric _time l2, the N4 _ mirror are in the same differential tower layout 8 , the present invention will set the transistors N3, N4 respectively (on the substrate) The diagonals of the crystals N1 and N2, the bribes are poorly affected by the process drift _ loudness _, called the error voltage of the low operational amplifier. Her 'P-type MOS semiconductors are arranged in the same way, and the layout pattern is shown in Fig. 4, and will not be described here.
具體來說,若電晶體元件的尺寸誤差可忽略,運算放大器之誤 差電壓Vos可藉由下式表示:Specifically, if the dimensional error of the transistor component is negligible, the operational amplifier's error voltage Vos can be expressed by:
Ay v°s= —+ Ayth>PX_P2 · gm n ^ Δ ν,ΚΝ,_ΝΛ · g„liNJ + A . ^ 茗"_+茗丨 g„um +g(I1/5, , 其中、△〆",,㈣4、△%_”及△匕况4分別代表電晶體ni與 N2、電晶體N3與N4、電晶體pi與P2及電晶體ι>3與p4之門檻 電壓差值,即^及%4 ;而U、 〜·ΡΙ、仏⑽及g⑽則分別代表電晶體N1、pl、N3及p3之轉導值。 若將N型金氧半導體電晶體與p型金氧半導體電晶體分開來考 慮,則上式可進一步表示為:Ay v°s= —+ Ayth>PX_P2 · gm n ^ Δ ν,ΚΝ,_ΝΛ · g„liNJ + A . ^ 茗"_+茗丨g„um +g(I1/5, , where △〆 ",, (4) 4, △%_" and △ 匕 condition 4 represent the threshold voltage difference between the transistors ni and N2, the transistors N3 and N4, the transistors pi and P2, and the transistors ι > 3 and p4, respectively ^ And %4; and U, 〜ΡΙ, 仏(10), and g(10) represent the transduction values of the transistors N1, pl, N3, and p3, respectively. If the N-type MOS transistor is separated from the p-type MOS transistor To consider, the above formula can be further expressed as:
△ K -gm„ ^ AFW2 -g.,,, +AK ,xr S,n^' +Sm,Pl gm,m +g r〇S,N + Vn^ D " /、中'?’#及如,户分別代表]^型金氧半導體電晶體與卩型金氧半 導體電晶體所貢獻之誤差電壓大小。 (S ) 10 1355796 因此,對於N型金氧半導體電曰 上參雜濃度州,㈣t:r向 Λ r/ i_、l (htN\-N2 太Γ4>ΰ <G及〜一等兩種情況。細,藉由 △匕秦"2>0及△%-〆0,或者 本t明第4圖之佈局圖案將可產生 △Κι,"丨-"2 < 0及△匕 Ny~NA >〇等兩種情況△ K -gm„ ^ AFW2 -g.,,, +AK ,xr S,n^' +Sm,Pl gm,m +gr〇S,N + Vn^ D "/,中'?'# and The households respectively represent the error voltages contributed by the ^-type MOS transistor and the 卩-type MOS transistor. (S) 10 1355796 Therefore, for the N-type MOS electrode, the doping concentration state, (4) t: r to Λ r / i_, l (htN \ - N2 too Γ 4 > ΰ < G and ~ one and so on. Fine, by △ 匕 Qin " 2 > 0 and △ % - 〆 0, or this t The layout pattern of Figure 4 will produce △Κι,"丨-"2 < 0 and △匕Ny~NA >〇
很明顯地’广N型金氧半導體電晶體所貢獻的誤差電壓大小 如川來看’猎㈣4 __所纽之誤差電壓大小將小於 ^圖佈關騎產生之誤差_大小。_可知,對於p型全 乳+導體電晶體所貢獻的誤差·大小丨⑽丨來說,第4圖佈局 =所產生之縣賴大小則、於第2圖佈局_所產生之誤差 电壓大小。因此’本發明電路佈局4〇可以得到較小的誤差電壓 Vos。 綜上所述,本發明係將對應於相同差動半電路之電晶體元件擺 放於對角,以使每-差動半電路受到製程飄移的影響程度相同, 而避免運算放大ϋ誤差賴的產生。❹卜,本㈣賴對電晶體 ⑽進行分割’因此每-電晶體元件之·指數目仍然等於一, 而不會增加電路的面積。 以上戶_堇為本發明之較佳實施例,凡依本發明申請專利範 圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 丄乃5796 【圖式簡單說明】 第1圖係—習知運算放大器之電路示意圖。 第2圖為習知運算放大器之一電路佈局之示意圖。 第3^為本發_纽善—縣放衫之縣輕之—佈局流 矛主之示思圖。 第4圖為本發明運算放大器之_電路佈局之示意圖。Obviously, the magnitude of the error voltage contributed by the 'wide N-type MOS transistor' is the same as the error _ size of the 布 关 骑 四. _ It can be seen that for the error/size 10(10)丨 contributed by the p-type total milk+conductor transistor, the layout of Fig. 4 = the size of the county to be produced, and the magnitude of the error voltage generated in the layout _ of Fig. 2. Therefore, the circuit layout 4 of the present invention can obtain a small error voltage Vos. In summary, the present invention places the transistor elements corresponding to the same differential half circuit in a diagonal direction, so that each-differential half circuit is affected by the process drift, and the operation amplification is avoided. produce. Further, this (4) depends on the division of the transistor (10). Therefore, the number of fingers per per-crystal element is still equal to one without increasing the area of the circuit. The above-mentioned households are the preferred embodiments of the present invention, and all changes and modifications made by the scope of the present invention should be within the scope of the present invention.丄乃5796 [Simple description of the diagram] Figure 1 is a schematic diagram of the circuit of a conventional operational amplifier. Figure 2 is a schematic diagram of one of the circuit layouts of a conventional operational amplifier. The 3rd is the hair _ New Shan - County County, the light of the county - layout flow spear master's thinking. Figure 4 is a schematic diagram of the circuit layout of the operational amplifier of the present invention.
【主要元件符號說明】 運算放大器 輪入級電路 輸出級電路 110 120 130、140 N型差動輸入對 P型差動入對 主動負載 m、N2、N3、N4 N型金氣半導體電晶體 P卜P2、P3、P4 P型金氧半導體電晶體 30 佈局流程 300、310、320、330 步驟 40 電路伟局[Major component symbol description] Operational amplifier wheel-in stage circuit output stage circuit 110 120 130, 140 N-type differential input pair P-type differential input active load m, N2, N3, N4 N-type gold gas semiconductor transistor P P2, P3, P4 P-type MOS transistor 30 layout process 300, 310, 320, 330 Step 40 Circuit
(S 12(S 12
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TW97126375A TWI355796B (en) | 2008-07-11 | 2008-07-11 | Operational amplifiers capable of reducing random |
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