^5-5698 ' » 九、發明說明： : 【發明所屬之技術領域】 本發明係有關於一種半導體封裝基板之製造方法，特 別係有關於一種可薄化封裝構造及具有高密度接點之半 導體封裝基板之製造方法’該半導體封裝基板係為無核心 層之基板。 【先前技術】 # 習知封裝基板為了避免接點距離過近而導致短路，通 常將基板之上及下表面皆設置有線路，以使基板具有足夠 之接點，如第1A至π圖所示，首先請參閱第ία圖，提 ’ 供一基板本體W ’該基板本體10係具有一第一銅層10a， 第一介電層l〇b及一第二銅層i〇c，該第一銅層1〇£1與 該第二銅層l〇c係分別形成於該第一接^電層10b之上及下 表面，接著，請參閱第⑺圖，形成一貫穿該第一鋼層1〇a 與該第二銅層l〇c之開口 l〇d，之後，請參閱第1C圖，形 *鲁成.帛—鋼層11於該第一銅層l〇a、該第二銅層1〇〇及該 • 開口 10d内以電性導通該第一銅層10a與該第二銅層 l〇C，接著，請參閱第1D圖，蝕刻該第一銅層l〇a '該第 -· 一銅層1 〇c及該第三鋼層11以形成複數個線路12，並填 充一絕緣材13於該開〇 l〇d内，之後，請參閱第1E圖， 形成一第二介電層14於該第三銅層u及該第—介電層 1 〇b上並顯露出該些線路12，之後，請參閱第1F圖，形 成重刀配線路層15 (redistribution layer，RDL )於該些 線路1 2，接著’請參閱第1 G圖，蝕刻該重分配線路層1 5， 1355698 之後，請參閱第m圖，形成一防銲層16於該重分配線路 層15與該第二介電層14，最後，請參閱第II圖，蝕刻該 防銲層16以顯露出複數個接點17並在該些接點上形成一 錄金層18以形成-基板.1()，。然上述之基板製程繁項且基 板10’之厚度無法薄化，不符合目前電子產品之需求。 【發明内容】 本發明之主要目的係、在於提供―種半導體封裝基板 之製造方法’首先’提供—基板本體，該基板本體係具有 -第-金屬層、一第二金屬層與一第三金屬層，接著，圖 案化該第三金屬層以至少形成複數個第—接點及複數個 第二接點，之後’形成—介電層於該第二金屬層以覆蓋該 .些第-接點及該㈣二接點，接著，移除該基板本體之一 第-金屬層以顯露出該第二金屬&，之後，圖案化該第二 金屬層以形成一種子層於該些第—接點及該些第二接 點，最後，形成-第四金屬層於該種子層。藉由本發明之 基板製造方法所製成之其柘在i古 教战之基板係具有兩密度之接點且厚度 較薄，故將該基板應用於半導體封裝構造係可像半導體 裝構％具声薄.化之偉點。 一 — 本發明之次要目.的，係4於提供—種半導體封裝基板 之製造方法’其係在圖案化該第三金屬層冑，亦形成複數 個線路，並且該介電層亦覆蓋該些線路，此外在圖案化該 第二金屬層時，係顯露出該些竽路，並仏，黑氧化層於 料糾。藉由本發明之基板製造方法所製成之基板係具 有尚雄度之接點且厚度較薄。 ’ 、 7 ^55698 磉 本發明之保護範圍當視後附之申請專利範圍所界定 2為準，任何熟知此項技藝者，在不脫離本發明之精神和 範圍内所作之任何變化與修改，均屬於本發明之保護 圍。 、叹 【圖式簡單說明】 第1Α至II圖：習知半導體封裝基板之製造方法之截面示 意圖。 第2Α至2G圖：依據本發明之一具體實施例，一種半導體 封裝基板之製造方法之截面示意圖。 第 3 圖：依據本發明之一具體實施例，該半導體封 裝基板應用於封裝構造之截面示意圖。 【主要元件符號說明】 10 基板本體 105 基板 10a 第一銅層 10b 第一介電層 l〇c 第二銅層 10d 開口 11 第三銅層 12 線路 13 絕緣材 14 第二介電層 15 重分配線路層 16 防銲層 17 接點 18 鎳金層 20 基板本體 209 基板 21 第一金屬層 22 第二金屬層 22a 種子層 23 第三金屬層 23a 線路 23b 第一接點 23c 第二接點 24 介電層 24a 第一表面 24b 第二表面 24c 開D 25 黑氧化層 26 第四金屬層（金屬層） 11 1355698 100半導體封裝構造 11 0晶片 130銲球 電元件 111銲墊 120導 140密封膠^5-5698 ' » IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of fabricating a semiconductor package substrate, and more particularly to a thinned package structure and a semiconductor having high density contacts Method of Manufacturing Package Substrate 'The semiconductor package substrate is a substrate without a core layer. [Prior Art] # Conventional Package Substrate In order to avoid a short circuit caused by a short contact point, a circuit is usually provided on both the upper and lower surfaces of the substrate so that the substrate has sufficient contacts, as shown in FIGS. 1A to π. First, please refer to FIG. 3A, the substrate body 10 has a first copper layer 10a, a first dielectric layer 10b and a second copper layer i〇c, the first The copper layer 1〇1 and the second copper layer 10c are respectively formed on the upper surface and the lower surface of the first electrical layer 10b, and then, referring to the figure (7), a first steel layer is formed through the first layer 〇a and the opening of the second copper layer 10c, and then refer to FIG. 1C, the shape of the Lucheng. 帛-steel layer 11 in the first copper layer 10a, the second copper layer The first copper layer 10a and the second copper layer 10C are electrically connected to the opening 10d, and then, referring to FIG. 1D, etching the first copper layer l〇a 'the first- a copper layer 1 〇c and the third steel layer 11 to form a plurality of lines 12 and filled with an insulating material 13 in the opening 〇d, after which, referring to FIG. 1E, a second dielectric is formed Layer 14 The third copper layer u and the first dielectric layer 1 〇b are exposed to the lines 12, and then, referring to FIG. 1F, a redistribution layer 15 (RDL) is formed on the lines 1 2, then, please refer to FIG. 1G, after etching the redistribution circuit layer 15 5, 1355698, referring to the mth picture, forming a solder resist layer 16 on the redistribution line layer 15 and the second dielectric layer 14 Finally, referring to FIG. II, the solder resist layer 16 is etched to expose a plurality of contacts 17 and a gold layer 18 is formed on the contacts to form a substrate .1(). However, the above substrate process is complicated and the thickness of the substrate 10' cannot be thinned, which does not meet the requirements of current electronic products. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for fabricating a semiconductor package substrate. First, a substrate body is provided. The substrate has a -metal layer, a second metal layer and a third metal. a layer, and then patterning the third metal layer to form at least a plurality of first contacts and a plurality of second contacts, and then forming a dielectric layer on the second metal layer to cover the first contacts And the (four) two contacts, and then removing one of the metal layers of the substrate body to expose the second metal & and then patterning the second metal layer to form a sub-layer on the first And the second contacts, and finally, forming a fourth metal layer on the seed layer. The substrate made by the substrate manufacturing method of the present invention has a two-density contact and a thin thickness, so that the substrate can be applied to a semiconductor package structure like a semiconductor device. Thin. A second aspect of the present invention is to provide a method of fabricating a semiconductor package substrate by patterning the third metal layer and forming a plurality of lines, and the dielectric layer also covers the The lines, in addition to patterning the second metal layer, reveal the turns, and the black oxide layer is corrected. The substrate system produced by the substrate manufacturing method of the present invention has a male contact and a thin thickness. The scope of protection of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are It belongs to the protection enclosure of the present invention. [Simplified description of the drawings] Figs. 1 to II are schematic cross-sectional views showing a method of manufacturing a conventional semiconductor package substrate. 2A to 2G are schematic cross-sectional views showing a method of fabricating a semiconductor package substrate in accordance with an embodiment of the present invention. Fig. 3 is a cross-sectional view showing the semiconductor package substrate applied to a package structure in accordance with an embodiment of the present invention. [Major component symbol description] 10 substrate body 105 substrate 10a first copper layer 10b first dielectric layer 10c second copper layer 10d opening 11 third copper layer 12 line 13 insulating material 14 second dielectric layer 15 redistribution Circuit layer 16 solder resist layer 17 contact 18 nickel gold layer 20 substrate body 209 substrate 21 first metal layer 22 second metal layer 22a seed layer 23 third metal layer 23a line 23b first contact 23c second contact 24 Electrical layer 24a first surface 24b second surface 24c open D 25 black oxide layer 26 fourth metal layer (metal layer) 11 1355698 100 semiconductor package structure 11 0 wafer 130 solder ball electrical component 111 solder pad 120 guide 140 sealant
1212