TWI349944B - Dual in-line memory module, memory test system, and method for operating the dual in-line memory module - Google Patents

Dual in-line memory module, memory test system, and method for operating the dual in-line memory module

Info

Publication number
TWI349944B
TWI349944B TW096123896A TW96123896A TWI349944B TW I349944 B TWI349944 B TW I349944B TW 096123896 A TW096123896 A TW 096123896A TW 96123896 A TW96123896 A TW 96123896A TW I349944 B TWI349944 B TW I349944B
Authority
TW
Taiwan
Prior art keywords
dual
memory module
line memory
operating
test system
Prior art date
Application number
TW096123896A
Other languages
Chinese (zh)
Other versions
TW200818216A (en
Inventor
Kyung-Hoon Kim
Yong-Ki Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200818216A publication Critical patent/TW200818216A/en
Application granted granted Critical
Publication of TWI349944B publication Critical patent/TWI349944B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test
TW096123896A 2006-06-29 2007-06-29 Dual in-line memory module, memory test system, and method for operating the dual in-line memory module TWI349944B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20060059594 2006-06-29
KR1020070041097A KR20080001604A (en) 2006-06-29 2007-04-27 Dual in line memory module of using test and test system thereof

Publications (2)

Publication Number Publication Date
TW200818216A TW200818216A (en) 2008-04-16
TWI349944B true TWI349944B (en) 2011-10-01

Family

ID=39213588

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096123896A TWI349944B (en) 2006-06-29 2007-06-29 Dual in-line memory module, memory test system, and method for operating the dual in-line memory module

Country Status (2)

Country Link
KR (1) KR20080001604A (en)
TW (1) TWI349944B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100911186B1 (en) * 2008-02-14 2009-08-06 주식회사 하이닉스반도체 Semiconductor device and data output method thereof
KR102076724B1 (en) * 2018-07-20 2020-02-13 주식회사 메리테크 DIMM Distributed system for improved stability and test efficiency
KR102070643B1 (en) * 2018-07-20 2020-04-02 주식회사 메리테크 DIMM Distributed system for improved stability and test efficiency

Also Published As

Publication number Publication date
TW200818216A (en) 2008-04-16
KR20080001604A (en) 2008-01-03

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees