TWI345866B - Liquid crystal display device and test method thereof - Google Patents

Description

1 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Detection method. [Prior Art] Due to its advantages of lightness, thinness, and low power consumption, liquid crystal display devices are widely used in modern information devices such as televisions, notebook computers, mobile phones, and personal digital assistants. At present, the application in the LCD TV market is becoming more and more important. Please refer to FIG. 1, which is a circuit diagram of a prior art liquid crystal display. The liquid crystal display 10 includes a plurality of mutually parallel scan lines 101, a plurality of data lines 102 vertically insulated from the scan lines 101, a 5V power supply 110, and a control circuit 100. The scan line 101 and the data line 102 define a plurality of pixel units 103. Each pixel unit 103 includes an R sub-pixel unit, a G sub-pixel unit, and a B sub-pixel unit. The control circuit 100 includes a scan driver 120, a data driver 130, a timing controller 140, a buck 150, a DC/DC converter 160, and a Gamma circuit 170. The buck 150 includes a first voltage input 151 and an operating voltage output 152. The first voltage input 151 is coupled to the 5V power supply 110. The operating voltage output terminal 152 is connected to the timing controller 140, the scan driver 120, and the data driver 130, for providing the timing controller 140, the scan driver 120, and the data driver 130 with an operating voltage of 3.3V. . The DC/DC converter 160 includes a second voltage input terminal 161, a main 096142350, a form number A0101, a fifth page, a total of 44 pages, 1003148994-0, 1345866, on April 28, a positive replacement page operating voltage (VAVDD) output. 162. A high-level gate voltage (output 163 and a low-level gate voltage (Vr,) output terminal 164. The second

The u L voltage input 161 is connected to the 5V power supply 110. The gate high voltage output terminal 163 is coupled to the scan driving circuit 120 for outputting a gate high voltage to the scan driving circuit 120. The gate low voltage output 164 is coupled to the scan drive circuit 120 for outputting a gate low voltage to the scan drive circuit 120. The main operating voltage output 162 is coupled to the gamma circuit 170. The gamma circuit 170 converts the main operating voltage vAVDD into a complex gray scale voltage according to the gray scale that the liquid crystal display 10 needs to display, and outputs it to the data driver 130, and each gray scale voltage corresponds to a display gray scale. The gate has a high voltage of 26V and the gate has a low voltage of V. It can be a 6V, and the main operating voltage can be 12.75V. The scan driver 120 is configured to receive a gate high voltage and a gate low voltage V& and sequentially output a plurality of scan voltages to each of the scan lines 101. The timing controller 140 is configured to receive an externally transmitted Low Voltage Differential Signaling (LVDS) and output a plurality of R, G, and B digital signals to the data driver 130. [0009] The data driver 130 is configured to convert the plurality of R, G, and B digital signals received by the data driver 130 into complex R, G, and B analog signals, and each of the R analog signal, the G analog signal, and the B analog signal respectively represent an R. The sub-pixel unit, a G sub-pixel unit, and a B sub-pixel unit correspond to display gray scales. The data driver 130 also selects a complex gray scale voltage according to the complex R, G, and B analog signals, and outputs the data to each data line 102. 096142350 Form No. A0101 Page 6 of 44 Page 1003148994-0 1345866 - , April 28, 100 Press the rhyme page 1 [0010] Please refer to Figure 2, which is the DC/DC converter of the LCD 10 160 internal circuit schematic. The DC/DC converter 160 includes a boost converter 180 and a peripheral circuit 190. The boost converter 180 is a MAX1518, and includes a first modulation terminal 181, a second modulation terminal 182, a reference voltage terminal 183, a first feedback terminal 184, a second feedback terminal 185, and a third Feedback terminal 186. The peripheral circuit 190 includes a first charge pump 191, a second charge pump 192, a boost circuit 193, a first step-down circuit 194, a second step-down circuit 195, and a first feedback circuit 196. a second feedback circuit 197 and a third feedback circuit 198. The first feedback circuit 196 includes a first resistor 1961 and a second resistor 1962 in series. The second feedback circuit 197 includes a third resistor 1971 and a fourth resistor 1 972 in series. The third feedback circuit 198 includes a first fifth resistor 1981 and a sixth electrical resistor 1982.

[0012] The second voltage input terminal 161 is connected to the main working voltage output terminal 162 via the boosting circuit 193, and provides a main working voltage VA, nn for the main operating voltage output terminal 162. The first charge pump 191 is configured to convert the main operating voltage VAVDD outputted by the main working voltage output terminal 162 into 2Vavdd, and the first step-down circuit 194 is configured to convert the 2¥^^ into a gate high voltage and provide the gate Very high voltage output 163. The second charge pump 192 is configured to convert the main operating voltage VAVDD outputted by the main working voltage output terminal 162 to -VAVDD, and the second step-down circuit 195 is configured to convert the -乂 "heart" into a gate low voltage Vgl. The gate low voltage output terminal 164. [0013] The main operating voltage output terminal 162 is connected to the first feedback terminal 184 via the first resistor 1961, and is also sequentially numbered via the first resistor 1961 and the second resistor 096142350. A0101 Page 7 of 44 1003148994-0 [0014] 1345866 1 9 6 2 Grounding. On April 28, 100, the replacement of the goods ~ [0015] [0016] The first step-down circuit 194 includes a PNP type a bipolar transistor 1940. The gate (not labeled) of the PNP bipolar transistor 194 is connected to the first modulation terminal 181; a source (not labeled) is connected to the main operating voltage via the first charge pump 191 The output terminal 162 is connected to the second feedback terminal 185 via the third resistor 1971, and is also grounded via the third resistor 1971 and the fourth resistor 1 972 in sequence. The second step-down circuit 195 is provided. Including an NPN bipolar transistor 1 950, the gate of the NPN bipolar transistor 1950 ( The label is connected to the second modulation terminal 18 2 ; the source (not labeled) is connected to the main operating voltage output terminal 162 via the second charge pump 丨 2 2; the drain (not labeled) The third resistor 186 is connected to the third feedback terminal 186, and is also grounded via the sixth resistor 1 982. When the liquid crystal display 10 is in normal operation, the main working voltage output terminal 162 is operated by the main operating voltage VAVDJ). The gate high voltage v G Η of the gate high voltage output terminal 163 and the gate low voltage of the gate low voltage output terminal 164 respectively satisfy the following public GL ' ^ Equation 1, Equation 2, Equation 3: [0017] Equation 1: VAVDD = VFB(R1+R2)/R2, where VFB represents the voltage of the first feedback terminal 184, 1? 丨 represents the resistance value of the first resistor 1961, and R represents the resistance value of the second resistor 1 962; 2: VGH = VFBP(R3 + R4)/R4, wherein VFBP indicates the voltage of the second feedback terminal 185' R3 indicates the resistance value of the third resistor 1971, and R indicates the resistance value of the fourth resistor 1 972; 0019]

Equation 3: V

GL

FBN 096142350 Form No. A0101 _(VREF-VFM)R5/R6, where 'VFBN Table 8/44 page 1003148994-0 1345866 On April 28, 100, the shuttle is replacing the voltage of the third feedback terminal 186. VDI^ represents the voltage of the reference voltage terminal of 183 K hr, and 1^ represents the resistance value of the fifth resistor 1981, indicating the resistance value of the fifth-sixth resistor 1982. [0020] At present, with the advancement of technology, the market competition of the liquid crystal display 10 is becoming more and more fierce, and the quality of the product has higher requirements, mainly in the quality of its display screen, such as bright line defects, light line defects, etc. . This kind of factor prompts the enterprise to detect the liquid crystal display 10 before shipment. The detection method currently adopted is to use a high voltage source connector to externally charge the control circuit 100 with the main working voltage V4vnni and the gate high voltage. The old and gate low voltage Veu accelerates the exposure of the potential defects of the liquid crystal display 10 to detect the potential defect. [0021] Please refer to FIG. 3 together, which is a schematic diagram of the circuit when the liquid crystal display 10 is detected. When the liquid crystal display 10 is detected, the control circuit 100 is stopped from supplying a voltage of 5 V to disable the DC/DC converter 160, and is connected to the control circuit 100 by a high voltage stress (HVS) connector 111. The high voltage source connector 111 includes a first output terminal 121, a second output terminal 122, a third output terminal 123, a fourth output terminal 124, and a fifth output terminal 125. 2伏。 The first output terminal 121 is connected to the timing controller 140, the scan driver 120 and the data driver 130, for the timing controller 140, the scan driver 120 and the data driver 130 3. 3V Working voltage. The second and third output terminals 122, 123 are respectively connected to the scan driver 120, and the scan driver 120 is respectively provided with a gate high voltage VeH1 and a gate low voltage Veu. The fourth output terminal 124 is connected to the timing controller 140 for providing a start signal to the timing controller 140 096142350. Form number A0101 page 9/total 44 page 1003148994-0 1345866 page. The start signal is used to activate the Buid In System Test (BIST) of the liquid crystal display 10, so that the liquid crystal display 10 displays the test screen of its internal setting. The fifth output terminal 1 2 5 is connected to the gamma circuit 170 for outputting the main operating voltage VA „nn1 to the gamma circuit 170. [0023] The gate high voltage ^U1 is higher than the gate voltage during normal operation The gate Ο π 1 U π high voltage Vu can be 30 V. The gate low voltage is higher than the normal operation gate (j Η 1 (j L 1 pole low voltage, the gate low voltage Vq can be an 8V. Main working voltage u L u L 1

Vavddi is higher than the main working power during normal operation, the main working power

5伏。 A VDD voltage v AVDD1 can be a 13. 5V. [0024] However, when the second output terminal 122 outputs a gate voltage to the scan driver 120, the gate high voltage output terminal 163 of the DC/DC converter 160 is also connected to the scan driver 120. At this time, the DC/DC converter 160 is in an inoperative state, so the gate high voltage voltage is reversely pumped into the DC/DC converter 160, which easily causes the internal circuit of the DC/DC converter 160 to malfunction. The DC/DC converter 160 is even burned out. At present, since the detection causes the DC/DC converter 160 of the liquid crystal display 10 to burn out at a rate of up to 10%, the reliability of the liquid crystal display 10 when detected is low. SUMMARY OF THE INVENTION [0025] In view of the above, it is necessary to provide a liquid crystal display with high reliability in detection. In view of the above, it is also necessary to provide a detection method of the above liquid crystal display. 096142350 Form No. A0101 Page 10 of 44 1003148994-0 1345866 碡' [0027] A replacement liquid crystal display comprising a plurality of scanning lines, a plurality of data lines and a control circuit, the control circuit The utility model comprises a DC/DC converter, a scan driver and a data driver. The DC/DC converter comprises a main working voltage output terminal, a gate high voltage output terminal, a gate low voltage output terminal, a first regulating circuit, a second adjusting circuit and a third adjusting circuit, the scan driver is configured to receive the gate high voltage and the gate low voltage, and sequentially output a plurality of scan voltages to each scan line; the data driver is configured to receive the main operating voltage And outputting a plurality of gray scale voltages to each of the data lines, wherein the first regulating circuit is connected to the main working voltage output end, the second adjusting circuit is connected to the gate high voltage output end, and the third adjusting circuit is connected to The gate low voltage output end, the first adjusting circuit has a first end, the second adjusting circuit has a second end, the third adjusting power Having a third end, respectively, by controlling the three three-terminal regulator circuit, the control voltage output terminal of the three DC / DC converters. Are increases. [0028] A method for detecting a liquid crystal display, comprising the steps of: providing a working voltage to the control circuit; and connecting the control circuit by using a connector, the connector comprising a first connection end and a second connection end And a third connection end; the first connection end is connected to the first end; the second connection end is connected to the second end; the third connection end is connected to the third end; The three terminals are controlled to further control whether the voltage of the three output terminals of the DC/DC converter increases. Compared with the prior art, the DC/DC converter of the liquid crystal display of the present invention further comprises three adjustment circuits, which can be controlled by the three ends of the three adjustment circuits, respectively, when the liquid crystal display is working normally 096142350 No. A0101 Page 11 of 44 1003148994-0 [0029] 1345866 On April 28, 100, the replacement page was verified without increasing the voltage at the three output terminals of the DC/DC converter; when detecting the liquid crystal display, The three regulating circuits respectively increase the voltage of the three output terminals of the DC/DC converter to achieve the size required for detection. Therefore, when detecting the liquid crystal display device, it is not necessary to use the connector to externally charge the main working voltage, the gate high voltage and the gate low voltage, so there is no high voltage backflow to the DC/DC converter due to the gate, and the burning The problem of the DC/DC converter of the liquid crystal display is bad, so the reliability of the liquid crystal display is high. [Embodiment] [0030] Please refer to FIG. 4, which is a circuit diagram of a first embodiment of a liquid crystal display of the present invention. The liquid crystal display 20 includes a plurality of mutually parallel scan lines 201, a plurality of data lines 202 vertically insulated from the scan lines 201, a 5V power supply 210, and a control circuit 200. The scan line 201 and the data line 202 define a plurality of pixel units 203. Each pixel unit 203 includes an R sub-pixel unit, a G sub-pixel unit, and a B sub-pixel unit. [0031] The control circuit 200 includes a scan driver 220, a data driver 230, a timing controller 240, a buck 250, a DC/DC converter 260, and a Gamma circuit 270. [0032] The buck 250 includes a first voltage input 251 and an operating voltage output 252. The first voltage input 251 is coupled to the 5V power supply 210. The operating voltage output terminal 252 is connected to the timing controller 240, the scan driver 220, and the data driver 230, for providing the timing controller 240, the scan driver 220, and the data driver 230 with an operating voltage of 3. 3V. . [0033] 096142350 The DC/DC converter 260 includes a second voltage input terminal 261, a main form number A0101, page 12/44 pages, 1003148994-0 1345866 [0034] [0036] 100 years, April 28 The daily working waste output terminal 262, a gate high voltage output terminal 263 and a drain low voltage output terminal 264. The second electrical input 261 is coupled to the 5V power supply 210. The gate high voltage output terminal 263 is connected to the scan driving circuit 22A for outputting the gate voltage VGH to the scan driving circuit 220. The gate low voltage output terminal 264 is connected to the scan driving circuit 22A for output. The gate is low voltage VGL to the scan driving circuit 220. The main operating voltage output 262 is coupled to the gamma circuit 270. The gamma circuit 27 converts the main operating voltage v into a complex gray scale voltage according to the gray scale that the liquid crystal display 20 needs to display, and outputs it to the data driver 23, each gray scale voltage corresponding to a display gray scale. The gate high voltage vgh can be 26v, the gate low voltage VGL can be -6V, and the main operating voltage can be 12 75v. The scan driver 230 is configured to receive the gate high voltage Vgh and the gate low voltage, and sequentially output the complex scan voltage to each scan line 2〇1 ^ The timing controller 2 side receives the externally transmitted differential differential signal to (10) and outputs the complex number For displaying the r, G, and B digital signals to the data driver 230, the data driver 23G is configured to convert the plurality of R, G, and B digital signals received by the data driver 23G into complex R, G 'B analog signals, each The “R-type analog signal, the G-type=signal and the B-type analog signal respectively represent the display gray scale corresponding to the —R sub-pixel unit, the —g sub-pixel °°− and the B sub-pixel unit. The data driver 230 also selects a complex gray scale voltage according to the plurality of R, G, and B analog signals and rotates to each of the data lines 202 » : _ and refers to FIG. 5 , which is a DC/DC conversion of the liquid crystal display 2 . . Schematic diagram of the circuit. The DC/DC converter 260 includes - 096142350 Form Compilation A0101 Page 13 of 44 1003148994-0 [0037] On April 28, 100, the bus is replacing the page boost converter 280 and a peripheral circuit 29A. The boost converter 280 can be a MAX1518, including a first modulation terminal 281, a second modulation terminal 282, a reference voltage terminal 283, a first feedback terminal 284, a first feedback terminal 285, and a first Three feedback terminals 286. The second voltage input 261 is coupled to the in-pin of the boost converter ago. The first modulation terminal 281 is a DRVP pin of the boost converter 28. The second modulation terminal 282 is a DRVN pin of the beta boost converter 280. The first feedback terminal 284 is the FB pin of the boost converter 280. The second feedback terminal 285 is the FBP pin of the boost converter 280. The third feedback terminal 286 is the FBN pin of the boost converter 280. The reference voltage terminal 283 is the REF pin of the boost converter 280. The peripheral circuit 290 includes a first charge pump 291, a second charge pump 292, a boost circuit 293, and a first step-down. The circuit 294, a second step-down circuit 295, a first feedback circuit 296, a second feedback circuit 297, a third feedback circuit 298, a first resistor 2961, a second resistor 2971 and a third resistor 2981. The first feedback circuit 296 includes a fourth resistor 2962 and a fifth resistor 2963 in series. The second anti-single circuit 297 includes a sixth resistor 2972 and a seventh resistor 2973 connected in series. The third feedback circuit 298 includes an eighth resistor 2982 and a ninth resistor 2983 in series. [0〇39] The second voltage input terminal 2 61 is connected to the main working voltage output terminal 262 via the booster circuit 293. The main operating voltage output 262 is supplied with a main operating voltage VAVDj). The first charge pump 291 is configured to convert the main operating voltage VAVDD outputted by the main working voltage output terminal 262 into 2Vavdd, and the first step-down circuit 294 is configured to convert the 2Vavdd into a gate high voltage vgh to the 096142350 form number. A0101 Page 14 of 44 1003148994-0 1345866 _ 'May 28th, April 28th Correction Replacement Page The gate is still at the output 263. The second charge pump 292 is configured to convert the main operating voltage v of the output of the main working voltage output terminal 262 into a function, and the first step-down circuit 295 is configured to convert the ~7 "卯 into a gate low voltage Vgl. Gate low voltage output 264. The main operating voltage output terminal 262 is connected to the first feedback terminal 284 via the fourth resistor 2962, and is also grounded via the fourth resistor 2962 and the fifth resistor 2963 in sequence. The first resistor 2961 is connected to the first feedback end 284 ′ and the other end is floating. [0041] The first step-down circuit 294 includes a PNP-type bipolar transistor 294A. The gate of the PNP-type bipolar transistor 2940 (not labeled) is connected to the first modulation terminal 281; the source (not labeled) is connected to the main operating voltage output terminal 262 via the first-charge pump 291; The second high-voltage output terminal 263 is connected to the second high-voltage output terminal 263, and is also connected to the second feedback terminal 285' via the sixth resistor 2972, and is also grounded via the sixth resistor 2972 and the seventh resistor 2973. The second resistor 2971 is connected to the second feedback terminal 285 at one end and floated at the other end. [0042] The second step-down circuit 295 includes an NPN-type bipolar transistor 2950, and the gate (not labeled) of the NPN-type bipolar transistor 2950 is connected to the second modulation terminal 282; the source (not labeled) Connected to the main operating voltage output terminal 262 via the second charge pump 292 and the first charge pump 291; and the pole (not labeled) is connected to the gate low voltage output terminal 264, and is also connected via the eighth resistor 2982 The third feedback terminal 286 is also connected to the reference voltage terminal 283 via the eighth resistor 2982 and the ninth resistor 2983. The third resistor 2981 is connected at its end to the second feedback terminal 286 and at the other end. 096142350 Form No. A0101 Page 15 / Total 44 Page 1003148994-0 [0043] 1345866 [0044] One & [ϊ〇ό^〇4^ 28 Β The first resistance 296] ♦ 阳伯-r* Μ-- The resistance value of -1 can be Ι3ΚΩ. The resistance of the second resistor 2971 can be 32 〇 kQ β γ 笛 帝 帝 帝 298 Γ μ μ 第二 第二 第二 第二 第二 第二 电阻 » » » » » » » » » » » » » » » » » » » The resistance of the fifth resistor 2963 can be as high as 845 Ω. The sixth resistor 2972 can have a resistance of 24 Ω. The resistance value of the seventh emperor resistance 2973 can be 1.21 Κ Ω. The electrical value of the eighth resistor 2982 can be 24 Ω. The resistance of the ninth resistor 2983 can be 1. 21 KQ. The liquid crystal display is the main working voltage of the main working voltage output terminal 262. , ^ AVDD ^ gate high voltage output terminal 263 gate high voltage V, the gate low voltage output terminal 2fu ★ ^ G but Z 6 4 gate low voltage v respectively satisfy the following formula 1, formula 2, formula 3:

GH

[0046] Equation 1 'ν_Ά+Κ5)/Ι?5 'where '% indicates that the voltage % of the first feedback Μ 284 indicates that the resistance value r of the fourth resistor 2 is off, and the resistance value of the fifth resistor 2963 is represented. 5 Equation 2. Vgh=vfbp(Vr7)/r7, where vFBp indicates that the voltage of the second feedback terminal 285 represents the resistance value of the sixth resistor 2972, and (1) shows the resistance value of the seventh resistor 2973. 7 [ 0047] Equation 3: vgl=vfbn~(vref_v shows the voltage of the third feedback terminal 286, Vref represents the voltage of the reference voltage terminal 283 '% indicates the resistance value of the eighth resistor 2982'% indicates the ninth The resistance value of the resistor 2983. Please refer to Figure 6 for the circuit diagram of the 2G detection of the liquid crystal display. When detecting the liquid 曰a display 2〇, the control circuit 2〇〇 is still supplied with 5V voltage, and adopts - high The migration connector 211 is connected to the control circuit

Ref vfbn)R8/R9, where Vfbn table 096142350 Form number A0101 Page 16 of 44 1003148994-0 [0048] 1345866 April 28, 100 Nuclear replacement page 200. The high voltage source connector 211 includes an output end 221, a first connection end 222, a second connection end 223, and a third connection end 224. [0049] The output terminal 221 is coupled to the timing controller 240 for providing a start signal to the timing controller 240. The activation signal is used to activate the built-in test system of the liquid crystal display 20 to cause the liquid crystal display 20 to display a test screen of its internal settings. The first connection end 222 is connected to the floating end of the first resistor 2961 and is grounded (not shown). The second connection end 223 is connected to the floating end of the second resistor 2971 and is grounded (not shown). The third connection end 224 is connected to the floating end of the third resistor 2981 and is connected to a reference voltage equal to the voltage of the reference voltage terminal 283 (not shown, the first resistor 2961 and the fifth resistor 2963 are not shown. In parallel, the second resistor 2971 is connected in parallel with the seventh resistor 2973, and the third resistor 2981 is connected in parallel with the ninth resistor 2983. [0050] The 5V power supply still supplies 5V voltage to the control circuit 200 due to detection, so The DC/DC converter 260 is still in operation, and its main operating voltage output terminal 262, gate high voltage output terminal 263 and gate low voltage output terminal 264 still output voltage. In addition, the main operating voltage output terminal 262 outputs the main controller at this time. The operating voltage VAVDDi, the gate high voltage VeH1 outputted by the gate high voltage output terminal 263, and the gate low voltage Vri outputted by the gate low voltage output terminal 264 respectively satisfy the following formula 4, formula 5, and formula 6: [0051] Equation 4: VAVDD1=VFB(R4 + R5n)/R5", where VFB indicates that the voltage '1?4 of the first feedback terminal 284 indicates the resistance value of the fourth resistor 2962, and R5" indicates the first resistor 2961 and the fifth Resistor 2963 in parallel Resistance value; V, <R5; 096142350 Form number A0101 Page 17 / Total 44 page 1003148994-0 1345866 [0052] [0055] 096142350 April 28, 100 nuclear replacement page 5 VGH1 VFBP(R6 + R7")/R7", wherein the electric dust mites of the second feedback terminal 285 indicate the resistance value of the sixth resistor 2972, and R7 indicates that the first resistor 2971 is not connected with the seventh resistor 2973. Resistance value; R7"<R7; Equation 6 'VGL "VFBN~~ (v " REP FBN^ 8 9 Six T VFBN represents the voltage of the third feedback terminal 286, VREF represents the voltage of the reference voltage terminal 283, % Representing the resistance value of the eighth resistor 2982, R9" indicates the resistance value of the third resistor 2981 in parallel with the ninth resistor 2983; r "<R. 9 9 From the above, 'VA >v AVDD ^GHl GH GL1 GL1 设定 is set by the resistance values of the first resistor 2961, the second resistor 2971 and the third resistor 2981, so that the main working voltage, the gate high voltage VGH1 and the low voltage VGL1 are equal to the detection requirement respectively during detection. Thus, the liquid crystal display 20 is detected. For example, the gate high voltage V g3 〇 v G Η 1. The gate low voltage VGL1 can be. The main operating voltage VAVDM can be a 13.5V. Compared with the prior art, the DC/DC converter 260 of the liquid crystal display 2 further includes a first resistor 2961, a second resistor 2971 and a third resistor 2981. The three resistors 2961, 2971, 2981 operate normally on the liquid crystal display 20. Floating, when detecting the liquid crystal display 20, respectively, in parallel with the fifth resistor 2963, the seventh resistor 2973 and the ninth resistor 2983, thereby increasing the main working voltage output terminal 262, the gate high voltage output terminal 263, the The voltage of the gate low voltage output terminal 264 causes the voltages of the three output terminals 262, 263, and 264 to output the required Vivnn, V, respectively. , VGL1. Therefore, when detecting the liquid crystal display 20, it is not necessary to use the high voltage source form number A0101, page 18/44, 1003148994-0 1345866 _ 1100^04^ connector 211 is externally charged with a main working voltage, a gate high voltage and one The gate voltage is low. Therefore, there is no problem in the prior art that the gate voltage is reversely injected into the DC/DC converter 260 to burn out the DC/DC converter 260 of the liquid crystal display 20. Therefore, the liquid crystal display 2〇 The reliability of the detection is high [0056] Please refer to FIG. 7, which is a schematic diagram of the internal circuit of the DC/DC converter 360 of the second embodiment of the liquid crystal display of the present invention. The DC/DC converter 360 differs from the DC/DC converter 260 of the first embodiment of the liquid crystal display 2 in that the peripheral circuit 390 of the DC/DC converter 360 further includes a first switching element 391 ' - second The switching element 392 and a third switching element 3 93. The first switching element 391 is a transistor whose gate (not labeled) is floating; the source (not labeled) is grounded; and the drain (not labeled) is connected to the first feedback terminal 384 via the first resistor 3961. The second switching element 392 is a transistor whose gate (not labeled) is floating; the source (not labeled) is grounded; and the drain (not labeled) is connected to the second feedback terminal 385 via the second resistor 2971. The third switching element 393 is a transistor whose gate (not labeled) is floating; the source (not labeled) is connected to the reference voltage terminal 383; and the drain (not labeled) is connected to the third feedback via the third resistor 3981. End 386. [0057] detecting the liquid crystal display, the first connection end of the high voltage source connector is connected to the gate of the first switching element 391; the second connection end is connected to the gate of the second switching element 392; the third connection end Connected to the gate of the third switching element 393. The three terminals are connected to a south voltage, so that the two switching elements 391, 392, and 393 are both turned on. Therefore, the first resistor 3961 is connected in parallel with the fifth resistor 3963. The third resistor 3971 is connected in parallel with the seventh resistor 3973. The third resistor 3981 is connected in parallel with the ninth resistor 3983. 096142350 Form number face 1 % 19 44 1 1003148994-0 1345866 __ April 28th, 桉 替换 replacement page [0058] The DC/DC converter of the liquid crystal display of the present invention can also be modified in various other ways, such as: detecting the first In one embodiment, the first connection end 222 and the second connection end 223 of the high voltage source connector 211 may not be grounded, but are connected to a low voltage (for example, IV, 2V, etc.) as long as the The voltage of the main working voltage output terminal 262 and the gate high voltage output terminal 263 may be sufficient. [0059] When the liquid crystal display 20 of the DC/DC converter 260 of the liquid crystal display device 20 of the first embodiment is detected, the third connection end 224 of the high voltage source connector 211 may also be grounded. The source (not labeled) of the third switching element 393 of the DC/DC converter 360 of the second embodiment may also be grounded. [0060] The boost converter 280 of the DC/DC converter 260 of the first embodiment of the liquid crystal display 20 may be of other models having the same function, such as the AAT1168B. [0061] The DC/DC converter 260 of the liquid crystal display device 20 of the first embodiment may also use the three-regulation circuit composed of the three resistors 2961, 2971, 2981 and the three feedback circuits 296, 297, and 298 to realize the three outputs when detecting. The voltages at terminals 262, 263, and 264 are increased, and other three adjustment circuits having the same function are employed. [0062] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. [Simple Description of the Drawings] 096142350 Form No. A0101 Page 20 of 44 1003148994-0 100 Years 〇 April 28 Nuclear Replacement Page 1345866 [0063] FIG. 1 is a circuit diagram of a prior art liquid crystal display. 2 is a schematic diagram showing the internal circuit of a DC/DC converter of the liquid crystal display shown in FIG. 1. 3 is a schematic circuit diagram of the liquid crystal display shown in FIG. 1 when it is detected. 4 is a schematic circuit diagram of a first embodiment of a liquid crystal display of the present invention. 5 is a schematic diagram of an internal circuit of a DC/DC converter of the liquid crystal display shown in FIG. 4. 6 is a circuit diagram of the liquid crystal display shown in FIG. 4 when it is detected. 7 is a schematic diagram showing the internal circuit of a DC/DC converter of a second embodiment of the liquid crystal display of the present invention. [Main component symbol description] [0070] Liquid crystal display: 20 [0071] Control circuit: 200 [0072] Scanning line: 201 [0073] Data line: 202 [0074] Pixel unit: 203 [0075] 5V power supply: 210 [0076 High voltage source connector: 211 [0077] Scan driver: 220 [0078] Output: 221 [0079] First connection: 222 1003148994-0 096142350 Form number A0101 Page 21 / Total 44 page 1345866 [0080] Connection: 223 [0081] Third connection: 224 [0082] Data driver: 230 [0083] Timing controller: 240 [0084] Buck: 250 [0085] First voltage input: 251 [0086] Voltage output: 252 [0087] DC/DC converter: 260, 360 [0088] Second voltage input: 261 [0089] Main operating voltage output: 262 [0090] Gate high voltage output: 263 [0091] Gate low voltage output: 264 [0092] Gamma circuit: 2 7 0 [0093] Boost converter: 280 [0094] First modulation terminal: 281 [0095] Second modulation terminal: 282 [0096] Reference voltage terminal : 283, 383 [0097] First feedback end: 284, 384 [0098] Second feedback end: 285, 385 096142350 Form No. A0101 Page 22 / Total 44 Pages April 28, 100 Nuclear Replacement Page 1003148994-0 1345866 [0099] Third Feedback Terminal: 286, 386 [0100] Peripheral Circuit: 290, 390 [0101] First Charge Pump: 291 [0102] Second charge pump: 292 [0103] Boost circuit: 293 [0104] First step-down circuit: 294 [0105] Second step-down circuit: 295 [0106] First feedback circuit: 296 [ 0107] Second feedback circuit: 297 [0108] Third feedback circuit: 298 [0109] First transistor: 391 [0110] Second transistor: 392 [0111] Third transistor: 393 [0112] PNP type double Polar crystal: 2940 [0113] NPN type bipolar transistor: 2950 [0114] First resistance: 2961, 3961 [0115] Fourth resistance: 2962 [0116] Fifth resistance: 2963, 3963 [0117] Second resistance : 2971, 3971 096142350 Form No. A0101 Page 23 / Total 44 Pages April 28, 2014 Shuttle replacement page 1003148994-0 1345866 Correction replacement page on April 28, 100 [0118] Sixth resistance: 2972 [0119] Seven resistors: 2973, 3973 [0120] Third resistor: 2981, 3981 [0121] Eightth resistor: 2982 [0122] Ninth resistor: 2983, 3983 100314 8994-0 096142350 Form No. A0101 Page 24 of 44

Claims (1)

1345866 - 'April 28, 100 amendments to replace the seven hundred, patent application scope: 1. A liquid crystal display, comprising a plurality of scanning lines, a plurality of data lines and a control circuit, the control circuit comprising a DC / DC converter, a a scan driver and a data driver, the DC/DC converter comprising a main operating voltage output terminal, a gate high voltage output terminal, a gate low voltage output terminal, a first regulating circuit, a second regulating circuit and a third An adjustment circuit, the scan driver is configured to receive the gate high voltage and the gate low voltage, and sequentially output a plurality of scan voltages to each scan line; the data driver is configured to receive the main operating voltage and output a complex gray scale voltage to each a data line, wherein the first regulating circuit is connected to the main working voltage output end, the second adjusting circuit is connected to the gate high voltage output end, and the third adjusting circuit is connected to the gate low voltage output end, the first An adjustment circuit has a first end, the second adjustment circuit has a second end, and the third adjustment circuit has a third end - Each of the three three-terminal regulator control circuits, the control voltage output terminal of the three DC / DC converter is increased if the sum. 2. The liquid crystal display of claim 1, wherein the voltage at the three terminals of the DC/DC converter is controlled to increase by separately controlling the voltages of the three terminals of the three regulating circuits. 3. The liquid crystal display of claim 2, wherein the three adjustment circuits do not increase the voltage of the three output terminals of the DC/DC converter when the liquid crystal display operates normally; when detecting the liquid crystal display The three regulating circuits respectively increase the voltages of the three output ends of the DC/DC converter, so that the voltages of the three output terminals reach the detected size. 4. The liquid crystal display according to claim 3, wherein the DC/DC converter further comprises a boost converter and a peripheral circuit, the rise 096142350 form number A0101 page 25 / total 44 page 1003148994 0 1345866 On April 28, 100, the positive replacement page voltage converter includes a reference voltage terminal, a first feedback terminal, a second feedback terminal and a third feedback terminal, and the first adjustment circuit includes a first resistor, a fourth resistor and a fifth resistor, the first resistor is connected to the first feedback end and the other end is floating; the main working voltage output terminal is connected to the first feedback terminal via the fourth resistor, and sequentially The second resistor and the fifth resistor are grounded; the second regulator circuit includes a second resistor, a sixth resistor, and a seventh resistor, the second resistor is connected to the second feedback end and the other end is floating; The gate high voltage output terminal is connected to the second feedback terminal via the sixth resistor, and is also grounded through the sixth resistor and the seventh resistor in sequence; the third adjusting circuit includes a third resistor, an eighth resistor, and a ninth resistor, one end of the third resistor is connected to the third feedback end, and the other end is floating; the gate low voltage output end is connected to the third feedback end via the eighth resistor, and sequentially passes through the eighth resistor and The ninth resistor is connected to the reference voltage terminal; the three ends of the three regulating circuits are the above three floating terminals. 5. The liquid crystal display of claim 4, wherein the DC/DC converter further comprises a voltage input terminal via which a 5V power supply supplies an operating voltage to the DC/DC converter. 6. The liquid crystal display of claim 5, wherein the DC/DC conversion circuit further comprises a booster circuit, the voltage input terminal being connected to the main operating voltage output terminal via the booster circuit, The main operating voltage output provides the main operating voltage. 7. The liquid crystal display of claim 6, wherein the DC/DC conversion circuit further comprises a first charge pump and a first step-down circuit, the first charge pump for using the main operating voltage The main working voltage of the output of the output is converted to twice the main working voltage, and the first step-down circuit is used to convert the double main operating voltage into a gate high voltage to the gate high voltage output 096142350. Form No. A0101 No. 26 Page / Total 44 pages 1003148994-0 1345866 100 years old April 28th revised replacement page end. 8. The liquid crystal display according to claim 7, wherein the first step-down circuit comprises a PNP-type bipolar transistor, and a gate of the PNP-type bipolar transistor is connected to the first modulation end; A source is coupled to the main operating voltage output via the first charge pump; a drain is coupled to the high voltage output. 9. The liquid crystal display of claim 7, wherein the DC/DC conversion circuit further comprises a second charge pump and a second step-down circuit, the second charge pump for using the main operating voltage The main operating voltage of the output of the wheel is converted into a reverse main operating voltage, and the first step-down circuit is configured to convert the reverse main operating voltage into a gate low voltage to be supplied to the gate low voltage output terminal. The liquid crystal display of claim 9, wherein the second step-down circuit comprises an NPN-type bipolar transistor, and a gate of the NPN-type bipolar transistor is connected to the second modulation terminal The source is connected to the main operating voltage output via the second charge pump; the drain is connected to the gate low voltage output. The liquid crystal display of claim 9, further comprising a gamma circuit, the main working voltage output end being connected to the gamma circuit, the gamma circuit being in need of display according to the liquid crystal display The gray scale number $ converts the main working voltage into a complex gray scale voltage and outputs it to the data driver, and each gray scale voltage corresponds to a display gray scale. 12. The liquid crystal display of claim 11, further comprising a timing controller for receiving an externally transmitted low voltage differential signal and outputting a plurality of digital signals for display to the data driver. 13. The liquid crystal display according to claim 12, wherein the data driver converts the plurality of digital signals received by the data driver into a complex analog signal 096142350, form number A0101, page 27 / total 44 pages 1003148994-0 100 years 04 On the 28th of the month, press the replacement page 14 . 15 . 16 . ' Among them, the boost, the sub-worm - 丨Br- 4 丄υυ U4 is the 〇 〇 1 忒 料 驱动 drive also according to the - voltage, and turn to For each - the money corresponds to the selection of the complex gray scale, such as the patent application _ Item 12 (four) to find a buck, the buck test uses the time state, which further includes a device for converting the 5V power supply 3V voltage 'to the timing control ... „ 駆 及 及 及 及 及 如 如 如 如 如 如 如 如 如 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶 液晶The voltage input terminal is connected to the 1N chat of the boost converter, and the first modulation terminal is connected to the _P of the boost converter, and the second modulation terminal is the DRVN of the boost converter. a pin, a 7th feedback terminal is a μ pin of the phase transition (4), and the second feedback end is an FBp pin of the boost converter, and the third feedback end is a trimming pin of the boost converter, The reference voltage terminal is the REF pin of the boost converter. 096142350 17 . 18 . 19 . 20 . The liquid crystal display of claim 4, wherein the boost converter is of the type AAT1168B. The liquid crystal display according to claim 4, wherein the resistance of the first resistor is 13 ΚΩ, and the resistance value of the second resistor is 100 Ω. The resistance of the third resistor is 100 ΚΩ. In the liquid crystal display, the resistance of the fourth resistor is 8.2 Ω, the resistance of the fifth resistor is 845 Ω, the resistance of the sixth resistor is 2, and the resistance of the seventh resistor is 1.21. ΚΩ, the resistance value of the eighth resistor is negotiating, and the ninth resistor is electrically The value is 1.21 Κ Ω. The liquid crystal display form number Α 0101 as described in item 4 of the patent application scope 'where the liquid AB 曰 page 28 / total 44 pages 1003148994-0 1345866 100 April 28, according to the positive replacement page display normal During operation, the main working voltage of the main working voltage output terminal is equal to, VpR represents the voltage of the first feedback end, t table FB 4 5 5 FB 4 shows the resistance value of the fourth resistor, and R_ represents the fifth resistor resistance. The liquid crystal display of claim 20, wherein, when the liquid crystal display operates normally, a gate high voltage of the gate high voltage output terminal is equal to Vfbp (Ra + R7) / R7, and VPRP indicates the second The voltage at the feedback terminal, Rr represents 67 7 FBP 6 the resistance value of the sixth resistor, and r7 represents the resistance value of the seventh resistor. The liquid crystal display of claim 21, wherein the gate low voltage output terminal has a gate low voltage equal to VFBN-(VREF — VFBN) R8/R9 'VFM when the liquid crystal display operates normally. The voltage of the three feedback terminals, VDI7P represents the voltage of the reference voltage terminal, R. Indicates the K L r 〇 resistance value of the eighth resistor, and L represents the resistance value of the ninth resistor. The liquid crystal display of claim 3, wherein the DC/DC converter further comprises a boost converter and a peripheral circuit, the boost converter comprising a reference voltage terminal, a first feedback a first feedback circuit, a first resistance component, a first resistor, a fourth resistor, and a fifth resistor; the first resistor is connected to the first end a feedback end, the other end is grounded via the first switching element; the main working voltage output end is connected to the first feedback end via the fourth resistor, and is also grounded via the fourth resistor and the fifth resistor in sequence; The second adjusting circuit includes a second switching element, a second resistor, a sixth resistor and a seventh resistor; the second resistor is connected at one end to the second feedback end, and the other end is grounded via the second switching element; The very high voltage output terminal is connected to the second feedback terminal via the sixth resistor, and is also grounded via the sixth resistor and the seventh resistor in sequence; the third regulating circuit includes a third switching component and a third electrical component , an eighth resistor and a ninth resistor; the third resistor is connected to the 096142350 at one end. Form No. A0101 Page 29 / Total 44 Page 1003148994-0 1345866 __ 100 years April 2S nuclear correction page is connected to the third feedback The other end is connected to the reference voltage terminal via the third switching element; the gate low voltage output terminal is connected to the third feedback terminal via the eighth resistor, and is further connected through the eighth resistor and the ninth resistor in sequence To the reference voltage terminal; the three ends of the three regulating circuits are respectively control ends of the three switching elements for respectively controlling whether the three switching elements are turned on. The liquid crystal display according to claim 23, wherein the first switching element is a transistor whose gate is floating; the source is grounded; and the drain is connected to the first feedback end via the first resistor; The first end of the first adjustment circuit is the gate of the first switching element. The liquid crystal display according to claim 24, wherein the second switching element is a transistor whose gate is floating; the source is grounded; and the drain is connected to the second feedback terminal via the second resistor; The second end of the second regulating circuit is the gate of the second switching element. The liquid crystal display of claim 25, wherein the third switching element is a transistor whose gate is floating; the source is connected to the reference voltage terminal; and the drain is connected to the third via the third resistor The third feedback end; the third end of the third adjusting circuit is the gate of the third switching element. The liquid crystal display of claim 23, wherein the DC/DC converter further comprises a voltage input terminal via which a 5V power supply supplies an operating voltage to the DC/DC converter. The liquid crystal display of claim 27, wherein the DC/DC converter further comprises a boosting circuit, the voltage input terminal being connected to the main working voltage output terminal via the boosting circuit, The main operating voltage output provides the main operating voltage. The liquid crystal display of claim 28, wherein the DC/DC converter further comprises a first charge pump and a first step-down circuit 096142350. Form No. A0101 Page 30 / Total 44 Page 1003148994 0 1345866 On April 28, 100, the core is being replaced by a page, and the first charge pump is used to convert the main working voltage outputted from the main working voltage output terminal into twice the main working voltage. The first step-down circuit is used for Converting the double main operating voltage to a gate high voltage is provided to the gate high voltage output terminal. The liquid crystal display of claim 29, wherein the first step-down circuit comprises a PNP-type bipolar transistor, and a gate of the PNP-type bipolar transistor is connected to the first modulation end; The source is connected to the main operating voltage output terminal via the first charge pump; the drain is connected to the high voltage output terminal. The liquid crystal display according to claim 29, wherein the DC/DC converter is further The second charge pump is configured to convert the main operating voltage outputted from the main working voltage output terminal into a reverse main operating voltage, and the first step-down circuit is used for the first step-down circuit. The reverse main operating voltage is converted to a gate low voltage and supplied to the gate low voltage output terminal. The liquid crystal display of claim 31, wherein the second step-down circuit comprises an NPN-type bipolar transistor, and the gate of the NPN-type bipolar transistor is connected to the second modulation terminal; The source is coupled to the main operating voltage output via the second charge pump; the drain is coupled to the gate low voltage output. 33. The liquid crystal display of claim 31, further comprising a gamma circuit, the main working voltage output being connected to the gamma circuit, the gamma circuit being required to display a gray scale according to the liquid crystal display The main working voltage is converted into a complex gray scale voltage and output to the data driver, and each gray scale voltage corresponds to a display gray scale. 34. The liquid crystal display of claim 33, further comprising a timing controller for receiving an externally transmitted low voltage differential signal and outputting a plurality of digital signals for display to the data driver 096142350 Form No. A0101, page 31 of 44, 1003148994-0, 1345, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 The signal is converted into a complex analog signal, and the data driver also selects a complex gray scale voltage according to the complex analog signal and outputs it to each data line. 36. The liquid crystal display of claim 34, further comprising a buck for converting the 5V power to an operating voltage of 3.3 V, to the timing controller, the scanning Drive and the data drive. 37. The liquid crystal display of claim 23, wherein the boost converter is of the type 181518. 38. The liquid crystal display of claim 37, wherein the voltage input terminal is connected to an IN pin of the boost converter, and the first modulation end is a DRVP pin of the boost converter, The second modulation end is a DRVN pin of the boost converter, the first feedback end is an FB pin of the boost converter, and the second feedback end is an FBP pin of the boost converter, the third The feedback end is the FBN pin of the boost converter, and the reference voltage terminal is the REF pin of the boost converter. 39. The liquid crystal display of claim 23, wherein the boost converter is of the type AAT1168B. 40. The liquid crystal display of claim 23, wherein the first resistor has a resistance value of 13 ΚΩ, the second resistor has a resistance value of 320 ΚΩ, and the third resistor has a resistance value of 100 ΚΩ. The liquid crystal display according to claim 23, wherein the fourth resistor has a resistance value of 8.2 ΚΩ, the fifth resistor has a resistance value of 845 Ω, and the sixth resistor has a resistance value of 24 ΚΩ. The resistance value of the seventh resistor is 096142350. Form No. A0101 Page 32 / Total 44 Page 1003148994-0 1345866 » On April 28, 100, press the positive replacement page 1.21ΚΩ, the resistance value of the eighth resistor is 24ΚΩ, the ninth resistor The resistance value is 1. 21 Κ Ω. 42. The liquid crystal display according to claim 23, wherein, when the liquid crystal display operates normally, a main working voltage of the main working voltage output terminal is equal to Vp/l + RJ/Rq, and VPR indicates the first feedback end The voltage, I table FB 4 5 5 FB 4 shows the resistance value of the fourth resistor, R. Indicates the resistance value of the fifth resistor. The liquid crystal display of claim 42, wherein when the liquid crystal display operates normally, the gate high voltage of the gate high voltage output terminal is equal to Vfbp (Rr + R7) / R7, and VFRP indicates the second The voltage at the feedback terminal, RK represents the resistance value of 67 7 FBP 6 and the resistance value of the sixth resistor, and r7 represents the resistance value of the seventh resistor. 44. The liquid crystal display according to claim 43, wherein, when the liquid crystal display operates normally, a gate low voltage output terminal has a gate low voltage equal to Vfbn — (Vref−Vfbn) R8/R9, and VFBN indicates the first The voltage at the three feedback terminals, VDPC_ indicates the voltage at the reference voltage terminal, R. Indicates the resistance value of the eighth resistor, and r9 represents the resistance value of the ninth resistor. 45. A method for detecting a liquid crystal display according to claim 1, comprising the steps of: providing a working voltage to the control circuit; and connecting the control circuit by a connector, the connector a first connecting end, a second connecting end and a third connecting end; the first connecting end is connected to the first end; the second connecting end is connected to the second end; the third connecting end is connected to The third end is controlled by the three terminals to further control whether the voltage of the three output terminals of the DC/DC converter increases. The method for detecting a liquid crystal display according to claim 45, wherein the DC/DC converter of the liquid crystal display further comprises a boost converter and a peripheral circuit, the boost converter including a reference voltage End, 096142350 Form No. A0101 Page 33 / Total 44 Page 1003148994-0 1345866 On April 28, 100, the first adjustment circuit, the second feedback end and a third feedback end are replaced by the first adjustment circuit. The first resistor, the fourth resistor, and the fifth resistor are connected to the first feedback end and the other end is floating; the main working voltage output is connected to the first feedback via the fourth resistor. The second adjusting circuit includes a second resistor, a sixth resistor, and a seventh resistor, and the second resistor is connected to the second feedback end. The other end is floating; the gate high voltage output is connected to the second feedback terminal via the sixth resistor, and is also grounded via the sixth resistor and the seventh resistor in sequence; the third regulating circuit includes a third resistor, an eighth resistor and a ninth resistor, the third resistor being connected to the third feedback terminal at one end and floating at the other end; the gate low voltage output terminal is connected to the third feedback terminal via the eighth resistor The first connection end is connected to the floating end of the first resistor and grounded; the first connection end is connected to the reference voltage terminal through the eighth resistor and the ninth resistor. The second connection end is connected to the floating end of the second resistor and is grounded; the third connection end is connected to the third feedback end via the third resistor, and is connected to a reference voltage equal to the voltage of the reference voltage terminal. 47. The method of detecting a liquid crystal display according to claim 46, wherein the liquid crystal display further comprises a timing controller for receiving an externally transmitted low voltage differential signal and outputting a plurality of digital signals for display To the data driver, the connector further includes an output connected to the timing controller, the output is configured to provide an activation signal to the timing controller, and the activation signal is used to activate the built-in test system of the liquid crystal display , so that the liquid crystal display displays the test screen of its internal setting. 48. The method of detecting a liquid crystal display according to claim 47, wherein the power source is 5V, directly supplied to the DC/DC converter, the liquid 096142350, form number A0101, page 34, total 44, 1003148994- 0 1345866 > 100 years 〇 April 28th Shuttle replacement pheno-crystal display further includes a buck, which converts the 5V power to an operating voltage of 3.3V, which is supplied to the timing controller, the scan driver and the data driver. The method for detecting a liquid crystal display according to claim 48, wherein, when detecting the liquid crystal display, a main working voltage of the main working voltage output terminal is equal to Vpr(R4 + R/)/R/, wherein VpR represents the voltage of the first feedback FB 4 5 FB terminal, R represents the resistance value of the fourth resistor, and R/ represents the resistance value of the first 4 5 resistor in parallel with the fifth resistor. 50. The method for detecting a liquid crystal display according to claim 49, wherein, when detecting the liquid crystal display, a gate high voltage of the gate high voltage output terminal is equal to vfbp (r6+r7")/r7", wherein vFBp represents the voltage of the second feedback terminal, Re represents the resistance value of the sixth resistor, and R7" represents the second electric b (resistance of the resistance in parallel with the seventh resistor. 51. As claimed in claim 50 The detection method of the liquid crystal display, wherein, when detecting the liquid crystal display, the gate low voltage of the gate low voltage output terminal is equal to VFBN_(VREF — VFM) R8/R9”, wherein VFM represents the voltage of the third feedback terminal, VDI7P represents the voltage of the reference voltage terminal, Ra represents the resistance value of the KL·r 〇 eighth resistor, and r9" represents the resistance value of the third resistor in parallel with the ninth resistor. 52. As claimed in claim 45 The method for detecting a liquid crystal display, wherein the DC/DC converter of the liquid crystal display is a boost converter and a peripheral circuit, the boost converter includes a reference voltage terminal, a first feedback terminal, a second feedback terminal and a third feedback terminal; the first adjustment circuit includes a first switching component, a first resistor, a fourth resistor, and a fifth resistor; the first resistor is connected to the first feedback end The other end is grounded via the first switching element; the main working voltage output terminal is connected to the fourth resistor via the fourth resistor 096142350, form number A0101, page 35, total page 44, 1003148994-0 1345866, April 28, 2014 The first feedback terminal is also grounded through the fourth resistor and the fifth resistor in sequence; the second adjustment circuit includes a second switching component, a second resistor, a sixth resistor, and a seventh resistor; One end of the two resistors is connected to the second feedback end, and the other end is grounded via the second switching element; the gate high voltage output end is connected to the second feedback end via the sixth resistor, and sequentially via the sixth resistor and the The seventh resistor is grounded; the third regulating circuit includes a third switching component, a third resistor, an eighth resistor, and a ninth resistor; the third resistor is connected at one end to the third feedback terminal, and the other end is connected to the third resistor a third switching component is connected to the reference voltage terminal; the gate low voltage output terminal is connected to the third feedback terminal via the eighth resistor, and is further connected to the reference voltage terminal via the eighth resistor and the ninth resistor. In the detection method of the liquid crystal display, the first connection end is connected to the gate of the first switching element to turn on the first switching element; the second connection end is connected to the gate of the second switching element, so that the second connection end The switching device is turned on; the third connecting end is connected to the gate of the third switching element, and the third switching element is turned on. 53. The method for detecting a liquid crystal display according to claim 52, wherein the liquid crystal display Further comprising a timing controller for receiving the externally transmitted low voltage differential signal and outputting a plurality of digital signals for display to the data driver, the connector further comprising an output connected to the timing controller, the output The end is used to provide a start signal to the timing controller, and the start signal is used to activate the built-in test system of the liquid crystal display to make the liquid crystal Setting display shows the inside of the test screen. 54. The method of detecting a liquid crystal display according to claim 53, wherein the power supply is 5 V, directly supplied to the DC/DC converter, and the liquid crystal display further includes a buck, the 5 V power supply Converted to 3.3V operating voltage, provided to the timing controller, the scan driver and the 096142350 Form No. A0101 Page 36 / Total 44 Page 1003148994-0 1345866 * April 28, 100 nuclear replacement page material drive. 55. The method of detecting a liquid crystal display according to claim 54, wherein, when detecting the liquid crystal display, a main working voltage of the main working voltage output terminal is equal to + ", wherein VpR represents the first feedback FB 4 5 5 The voltage at the FB terminal, R, represents the resistance value of the fourth resistor, and Rc" represents the resistance value of the first 4 5 resistor in parallel with the fifth resistor. The method for detecting a liquid crystal display according to claim 55, wherein, when detecting the liquid crystal display, a gate high voltage of the gate high voltage output terminal is equal to Vprp(Rr + R7")/R7", wherein VpRp represents the voltage of the second feedback terminal FBP 67 7 FBP, Re represents the resistance value of the sixth resistor, and R/ represents the second power 0 (resistance of the resistance in parallel with the seventh resistor. 57. The method for detecting a liquid crystal display according to Item 56, wherein, when detecting the liquid crystal display, the gate low voltage of the gate low voltage output terminal is equal to VFM-(VREF-VFBN)R8/R9", wherein VFM indicates the third The voltage at the feedback terminal, VDI7I? indicates the voltage at the reference voltage terminal, R. indicates the resistance value of the REF 8 eighth resistor, and r9" indicates the resistance value of the third resistor in parallel with the ninth resistor. 096142350 Form No. A0101 37 pages / total 44 pages 1003148994-0