1345691 100年04月26日修正替換頁 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種穩壓裝置，尤其係關於一種低壓降線性 穩壓裝置。 【先前技術】 [0002] 低壓降線性穩壓器（Low Drop-out LineaF RegulatQf ，LDO)係被廣泛應用於手機、DVD、數碼相機以及Mp3等 多種消費類電子產品中之穩壓晶片’為了滿足這些精密 電子產品之要求’在電源之輸入端加入線性穩壓器，以 保證電源電壓恒定與實現有源雜訊濾波。此外，這些電 子產品通常只有一組電池供電，為了節省供電池之電量 ，希望在設備不工作時，LD0工作於睡眠狀態。為此，大 部分LD0都具有使能控制功能，從而方便用戶控制使用。 [0003] 惟，該LD0在方便用戶使用之同時，存在_個無法避免之 問題：LD0之使能控制模組之邏輯工作電平沒有辦法覆蓋 一個連續之工作電平，從而造成當控制信號處於這個不 連續工作電平時候，使能控制模組處於浮動狀態（介於高 電平Η與低電平L之間之一個無法控制之階段），從而LD〇 失去對輸出狀態之控制》 【發明内容】 [0004] 有鑒於此，有必要提供一種解決低壓降線性穩壓器失去 對輸出狀態之控制問題之低壓降線性穩壓裝置。 [〇_ -種低壓降線性穩壓裝置，其包括一個低壓降線性穩壓 器及-個電祕樣模組，該健降線性穩壓器具有—個 能輸出第二控制邏輯之使能控制模組，該電壓採樣模組 096145634 表單編號A0101 1003145696-0 第5頁/共18頁 1345691 100年04月26日核正脊换頁 對該低壓降線性穩壓器之輸出電壓進行採樣，並輸出第 一控制邏輯，該第一控制邏輯與該第二控制邏輯構成第 三控制邏輯，該第一控制邏輯、該第二控制邏輯與該第 三控制邏輯滿足以下邏輯關係式：1345691 Correction and replacement page of April 26, 100. Description of the Invention: [Technical Field] [0001] The present invention relates to a voltage stabilizing device, and more particularly to a low voltage drop linear voltage stabilizing device. [Prior Art] [0002] Low Drop-out LineaF RegulatQf (LDO) is widely used in mobile phones, DVDs, digital cameras, and regulator chips in various consumer electronic products such as Mp3. The requirements of these precision electronic products 'add a linear regulator to the input of the power supply to ensure constant supply voltage and achieve active noise filtering. In addition, these electronic products are usually powered by only one battery. In order to save power for the battery, it is desirable that the LD0 be in a sleep state when the device is not operating. For this reason, most LD0s have an enable control function to facilitate user control. [0003] However, while the LD0 is convenient for the user to use, there is an unavoidable problem: the logic working level of the LD0 enable control module cannot cover a continuous working level, thereby causing the control signal to be at When the discontinuous working level is reached, the enabling control module is in a floating state (an uncontrollable phase between a high level Η and a low level L), so that the LD 〇 loses control of the output state. [0004] In view of this, it is necessary to provide a low-dropout linear regulator that solves the problem of low-dropout linear regulator losing control of the output state. [〇_-A low-dropout linear regulator device, which includes a low-dropout linear regulator and an electric secret-like module. The down-converting linear regulator has an enable control that can output the second control logic. Module, the voltage sampling module 096145634 Form No. A0101 1003145696-0 Page 5 of 18 1345691 April 26, 2005 Nuclear ridges page to sample the output voltage of the low-dropout linear regulator, and output The first control logic, the first control logic and the second control logic form a third control logic, and the first control logic, the second control logic and the third control logic satisfy the following logical relationship:
為該第一控制邏輯、 為該第二控制邏輯、γ為該第三控制邏輯。 [0006] 所述低壓降線性穩壓裝置，籍由該第三控制邏輯來控制 該低壓降線性穩壓器之輸出狀態，避免了因該使能控制 模組處於浮動狀態而導致該低壓降線性穩壓器之輸出狀 態處於失效模式。 【實施方式】 _ [0007] 下面將結合附圖，舉以下較佳實施方式並配合圖式詳細 描述如下。 [0008] 請參閱圖1，係本發明第一實施方式提供之一種低壓降線 性穩壓裝置100，該低壓降線性穩壓裝置100包括一個低 壓降線性穩壓器101及一個電壓採樣模組102。該低壓降 線性穩壓器101包括一個使能控制模組1011、MOS驅動模 組1012、MOS開關模組1013、第四比較放大器1014及反 饋模組1015。該電壓採樣模組102包括有一個邏輯輸出模 組1 024、一個比較放大器模組1 025及一個延遲模組1026 ，該比較放大器模組1 025具有第一比較放大器1 0251與 第二比較放大器1 0252。 [0009] 該低壓降線性穩壓器101接收外部輸入電壓V.，經内部 1 η 096145634 表單編號Α0101 第6頁/共18頁 1003145696-0 1345691For the first control logic, the second control logic, γ is the third control logic. [0006] the low-dropout linear voltage regulator device controls the output state of the low-dropout linear regulator by the third control logic, thereby avoiding the low-dropout linearity caused by the enable control module being in a floating state The output state of the regulator is in the fail mode. [Embodiment] [0007] The following preferred embodiments will be described in detail below with reference to the accompanying drawings. Please refer to FIG. 1 , which is a low-voltage drop linear regulator device 100 according to a first embodiment of the present invention. The low-dropout linear regulator device 100 includes a low-dropout linear regulator 101 and a voltage sampling module 102. . The low dropout linear regulator 101 includes an enable control module 1011, a MOS drive mode group 1012, a MOS switch module 1013, a fourth comparison amplifier 1014, and a feedback module 1015. The voltage sampling module 102 includes a logic output module 1 024, a comparison amplifier module 1 025 and a delay module 1026. The comparison amplifier module 1 025 has a first comparison amplifier 10251 and a second comparison amplifier 1 0252. [0009] The low dropout linear regulator 101 receives an external input voltage V., via internal 1 η 096145634 Form number Α 0101 Page 6 / 18 pages 1003145696-0 1345691
1100年04月26日修正替换頁I 處理輸出電愿V〇ut ’以保證電源電壓恒定與實現有源雜訊 濾波。該電壓採樣模組1〇2對該低壓降線性穩壓器1〇1之 輸出電壓ν_進行分時採樣，得到第—採樣電壓'與第二 採樣電壓，並判斷該兩次採樣電壓'、、之邏輯電平 ，得到第一採樣電壓V!之邏輯電平、與第二採樣電壓、 之邏輯電平A2，最後，將\與、構成一個第一控制邏輯 Yl〇 [0010] 该低壓降線性穩壓裝置1〇〇之使能控制模組1〇1丨輸出具有 一個參考電壓Vref與一個第二控制邏輯γ2。該反饋模組 101 5對該低壓降線性穩壓器1〇1之輸出電壓V 進行即蚌 out 丨呵 採樣，並分別送入該第四比較放大器1〇14、該第一比較 放大器1 0251與該延遲模組1 026。該第四比較放大器 1014接收該反饋模組1015之輸出信號與該參考電壓v ref ’並將該兩個信號進行比較放大後輸出用來驅動該M〇s驅 動模組1012。該第一比較放大器10251在第一時刻、接 收該反饋模組101 5之輸出信號，得到第一採樣電壓\。 該第一比較放大器10251將該第一採樣電壓Vi與該參考電 壓\“構成第一邏輯電平Αι。該第二比較放大器1〇252因 為該延遲模組1026之存在’所以，在第二時刻t接收該 2 反饋模組1015之輸出信號，得到第二採樣電壓V2。該第 二比較放大器10252將該第二採樣電壓V2與該參考電壓 Vref構成第二邏輯電平A2。該邏輯輸出模組1〇24接收該 第一邏輯電平Ai與該第二邏輯電平A2，並構成該第一控 制邏輯Yi。該M0S驅動模組1012接收該第四比較放大器模 組1014之輸出信號、該第二控制邏輯Y2&該第一控制邏 096145634 表單編號Α0101 第7頁/共18頁 1003145696-0 1345691 100年04月26日核正菁換頁 輯\ ’並將該第二控制邏輯¥2與該第一控制邏輯Yi構成 第三控制邏輯Y。該M0S開關模組1013接收該低壓降線性 穩壓器ιοί之外部輸入電壓vin與該第三控制邏輯γ，用來 控制該低壓降線性穩壓器101之輪出電壓V ^ out [0011] 請參閲圖2，係圖1中低壓降線性穩壓器101之輸出電壓 Vout與時間t之關係曲線圖。該低壓降線性穩壓器ιοί之 輸出電壓V〇ut與時間t之關係曲線為，該電壓採樣模組 102在、％時刻對輸出電壓v〇ut之採樣電壓分別為'、 V U 1On April 26, 1100, the replacement page I was processed to process the output power V〇ut ’ to ensure that the power supply voltage was constant and active noise filtering was implemented. The voltage sampling module 1〇2 samples the output voltage ν_ of the low-voltage drop linear regulator 1〇1 to obtain a first sampling voltage 'and a second sampling voltage, and determines the two sampling voltages', The logic level, the logic level of the first sampling voltage V!, the second sampling voltage, the logic level A2, and finally, \, constitute a first control logic Yl 〇 [0010] the low pressure drop The linear regulator device 1's enable control module 1〇1丨 output has a reference voltage Vref and a second control logic γ2. The feedback module 101 5 samples the output voltage V of the low-dropout linear regulator 1〇1, and sends it to the fourth comparison amplifier 1〇14, the first comparison amplifier 1 0251 and The delay module 1 026. The fourth comparison amplifier 1014 receives the output signal of the feedback module 1015 and the reference voltage v ref ' and compares and amplifies the two signals to output the M〇s driving module 1012. The first comparison amplifier 10251 receives the output signal of the feedback module 101 5 at the first moment to obtain a first sampling voltage. The first comparison amplifier 10251 compares the first sampling voltage Vi with the reference voltage \"constituting a first logic level 。ι. The second comparison amplifier 1 252 is present because of the delay module 1026", so at the second moment Receiving the output signal of the 2 feedback module 1015 to obtain a second sampling voltage V2. The second comparison amplifier 10252 forms the second sampling voltage V2 and the reference voltage Vref to form a second logic level A2. The logic output module Receiving the first logic level Ai and the second logic level A2, and forming the first control logic Yi. The MOS driving module 1012 receives the output signal of the fourth comparison amplifier module 1014, the first The second control logic Y2 & the first control logic 096145634 form number Α 0101 page 7 / total 18 pages 1003145696-0 1345691 100 years of April 26 nuclear reform page \ ' and the second control logic ¥ 2 and the first A control logic Yi constitutes a third control logic Y. The MOS switch module 1013 receives an external input voltage vin of the low-dropout linear regulator ιοί and the third control logic γ for controlling the low-dropout linear regulator 101. Wheel power V ^ out [0011] Please refer to FIG. 2 , which is a graph of the output voltage Vout of the low-dropout linear regulator 101 and time t in FIG. 1. The output voltage V〇ut of the low-dropout linear regulator ιοί The relationship between the time t is that the sampling voltage of the output voltage v〇ut at the time of the voltage sampling module 102 is ', VU 1
[0012] 請參閱圖3，係圖2中採樣電壓' 乂2對應之邏輯電平A 八2與輸出電壓Vout之關係示意圖。、與t2之間之時間間 隔為τ ,在本實施方式中，、與、之間之時間間隔7大於 該低壓降線性穩壓器101之軟啟動時間，以避免負載突然 變化造成誤動作。籍由判斷、、、對應之邏輯電平、、 A2，得到該第一控制邏輯、’其邏輯關係轉化為真^表 可由下表1所示。 表1Please refer to FIG. 3 , which is a schematic diagram showing the relationship between the logic level A 八 2 corresponding to the sampling voltage ' 乂 2 and the output voltage Vout in FIG. 2 . The time interval between t2 and t2 is τ. In the present embodiment, the time interval 7 between and is greater than the soft start time of the low-dropout linear regulator 101 to avoid a malfunction caused by a sudden change in load. The first control logic is obtained by the judgment, the corresponding logic level, and A2, and the logical relationship is converted into a true ^ table as shown in Table 1 below. Table 1
上表1可由 以下邏輯關係式表 不 表單編號Α0101 [0013] [0014] 096145634 第8頁/共18頁 1003145696-0 1345691 _ 100年04月26日修正替換頁 [0015] 該低壓降線性穩壓器1〇1之使能控制模組1〇11之第二控制 邏輯丫2與該第一控制邏輯Yl，構成該第三控制邏輯γ，其 邏輯關係轉化為真值表可由下表2所示。 表2 輸入 輸入 輸出 γ, Υ2 Υ 0 0 0 0 1 1 1 0 1 1 1 1 上表2可由以下邏輯關係式表示： [0016] [0017] y = Y1xY1+Yl [0018] 因為Υ!由該V〗、乂2對應之邏輯電平Α 、Α之邏輯關係構 1 Lt 成，所以，該八丨、A2與該第二控制邏輯γ 、該第三控制 L· 邏輯Y之邏輯關係轉化為真值表可由下表3所示。 [0019] 表 3 ------- 輸入 輸入 輸入 輸出 Αι A2 γ2 Υ 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 表單編號A0101 第9頁/共18頁 1003145696-0 096145634 1345691 _1〇〇年04月26日梭正替換頁 1 0 1…·· ~ 1 1 1 0 0 1 1 1 1 上表3可由以下邏輯關係式表示： Y =(〜.A2 )x Y2 + a! X A2。 [0021] "月參閲圖4，係本發明第二實施方式提供之一種低壓降線 性穩壓裝置200，該低壓降線性穩壓裝置200包括一個低 壓降線性穩壓器1〇1及一個電壓採樣模組1〇3。該第二實 施方式與該第-實施方式之區別在於，Μ電屋採樣模組 103對該低壓降線性穩壓器1〇1之輸出電壓ν進行即時 採樣，該電壓採樣模組103包括有一個第三比較放大器 1 0253，且該電壓採樣模組1〇3接收一個外部參考電壓〆 ref »該外部參考電壓V’ ref根據用戶之需求進行設置， 因為該外部參考電壓v w決定了該低壓降線性穩壓器 101之輸出電壓，所以該外部參考電壓/ 小於該使能 控制模組1G11之參考電壓vref。該第三比^放A|§1〇253 在時刻，接收該反饋模組1015之輪出信號，得到第三 輸出電壓vg。該第三比較放大器1 0253將該第三輸出電壓 Vg與該外部參考電壓V ref構成該第一控制邏輯 [0022] 綜上所述，在第一、第二實施方式中，當該電壓採樣模 組102之邏輯輸出ΥΘ高電平Η時，無論該使能控制模組 1011之邏輯輸出Υζ處於什麼狀態，總邏輯輪出Υ關閉該 M0S開關模組1013;當丫丨為低電平L時，、為高電平11時 ’該M0S開關模組1013也關閉，為低電平㈣，不對該 096145634 表單編號Α0101 第10頁/共18頁 1003145696-0 1345691 100年04月26日修正替換頁 M0S開關模組1013做控制。這樣，就避免因該使能控制模 組1 0 11處於浮動狀態而使該低壓降線性穩壓器1 01之輸出 狀態處於失效模式之問題出現。 [0023] 综上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施方式，本 發明之範圍並不以上述實施方式為限，舉凡熟悉本案技 藝之人士援依本發明之精神所作之等效修飾或變化，皆 應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0024] 圖1係本發明第一實施方式提供之低壓降線性穩壓裝置之 功能模組圖。 [0025] 圖2係圖1中低壓降線性穩壓器之輸出電壓與時間之關係 曲線圖。 [0026] 圖3係圖2中採樣電壓之邏輯電平與輸出電壓之關係示意 圖。 [0027] 圖4係本發明第二實施方式提供之低壓降線性穩壓裝置之 功能模組圖。 【主要元件符號說明】 [0028] 低壓降線性穩壓裝置：100 [0029] 電壓採樣模組：102 [0030] 低壓降線性穩壓器：101 [0031] 使能控制模組：1011 [0032] MOS驅動模組：1012 096145634 表單編號A0101 第11頁/共18頁 1003145696-0 1345691 _ 1〇〇年04月26日梭正晉换頁 [0033] MOS開關模組：1013 [0034] 第四比較放大器： 1014 [0035] 反饋模組：1015 [0036] 參考電壓：V f ref [0037] 第一控制邏輯：yi [0038] 第二控制邏輯：Y. L ； [0039] 第三控制邏輯：Y [0040] 邏輯輸出模組：1024 [0041] 比較放大器模組： 1025 [0042] 第一比較放大器： 1 0251 [0043] 第二比較放大器： 1 0252 [0044] 延遲模組：1026 [0045] 第一採樣電壓：V, [0046] 第二採樣電壓：^ ； [0047] 第一時刻： [0048] 第二時刻：t2 [0049] 關係曲線：h [0050] 外部參考電壓：/ ref [0051] 第三採樣電壓：V«_ 1003145696-0 096145634 表單編號A0101 第12頁/共18頁 1〇〇年04月26日修正替换頁 1345691 [0052] 低壓降線性穩壓裝置：200 . [0053] 電壓採樣模組：103 [0054] 第三時刻： ό [0055] 第三比較放大器：10253 [0056] 第一邏輯電平：Ai [0057] 第二邏輯電平：A2 096145634 表單編號A0101 第13頁/共18頁 1003145696-0Table 1 above can be represented by the following logical relationship table no form number Α0101 [0014] 096145634 Page 8 / Total 18 pages 1003145696-0 1345691 _ 100 April 26 revised replacement page [0015] The low dropout linear regulator The second control logic 丫2 of the enable control module 1〇11 and the first control logic Y1 constitute the third control logic γ, and the logical relationship thereof is converted into a truth table as shown in Table 2 below. . Table 2 Input Input Output γ, Υ2 Υ 0 0 0 0 1 1 1 0 1 1 1 1 The above Table 2 can be expressed by the following logical relationship: [0017] y = Y1xY1+Yl [0018] Because Υ! V, 乂2 corresponds to the logical level Α, Α logical relationship 1 Lt into, so the logical relationship between the gossip, A2 and the second control logic γ, the third control L· logic Y is converted to true The value table can be as shown in Table 3 below. [0019] Table 3 ------- Input Input I/O Αι A2 γ2 Υ 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 Form No. A0101 Page 9 of 18 1003145696-0 096145634 1345691 _1 April 26th, the shuttle is replacing page 1 0 1...·· ~ 1 1 1 0 0 1 1 1 1 The above table 3 can be represented by the following logical relationship: Y = (~.A2) x Y2 + a! X A2. [0021] FIG. 4 is a low-dropout linear voltage regulator 200 according to a second embodiment of the present invention. The low-dropout linear regulator 200 includes a low-dropout linear regulator 1〇1 and a Voltage sampling module 1〇3. The difference between the second embodiment and the first embodiment is that the power module sampling module 103 instantaneously samples the output voltage ν of the low-voltage drop linear regulator 1〇1, and the voltage sampling module 103 includes one The third comparison amplifier 1 0253, and the voltage sampling module 1〇3 receives an external reference voltage 〆ref » the external reference voltage V' ref is set according to the user's demand, because the external reference voltage vw determines the low dropout linearity The output voltage of the regulator 101 is such that the external reference voltage / is less than the reference voltage vref of the enable control module 1G11. The third ratio A|§1〇253 receives the rounding signal of the feedback module 1015 at the time to obtain the third output voltage vg. The third comparison amplifier 1 0253 forms the third output voltage Vg and the external reference voltage V ref to form the first control logic. [0022] In summary, in the first and second embodiments, when the voltage sampling mode When the logic output of the group 102 is ΥΘ high level, regardless of the state of the logic output 该 of the enable control module 1011, the total logic wheel turns off the MOS switch module 1013; when 丫丨 is low level L , when the level is high 11 'The MOS switch module 1013 is also closed, is low level (four), not 096145634 form number Α 0101 page 10 / total 18 pages 1003145696-0 1345691 100 years April 26 correction replacement page The MOS switch module 1013 is controlled. Thus, the problem that the output state of the low-dropout linear regulator 101 is in the fail mode due to the enable control mode group 101 is in a floating state is avoided. [0023] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0024] FIG. 1 is a functional block diagram of a low-dropout linear voltage regulator provided by a first embodiment of the present invention. 2 is a graph showing the output voltage versus time of the low-dropout linear regulator of FIG. 1. 3 is a schematic diagram showing the relationship between the logic level of the sampled voltage and the output voltage in FIG. 2. 4 is a functional block diagram of a low-dropout linear voltage regulator provided by a second embodiment of the present invention. [Main component symbol description] [0028] Low-dropout linear regulator: 100 [0029] Voltage sampling module: 102 [0030] Low-dropout linear regulator: 101 [0031] Enable control module: 1011 [0032] MOS driver module: 1012 096145634 Form number A0101 Page 11 / 18 pages 1003145696-0 1345691 _ 1 year of April 26th shuttle Zhengjin page [0033] MOS switch module: 1013 [0034] Fourth comparison Amplifier: 1014 [0035] Feedback Module: 1015 [0036] Reference Voltage: V f ref [0037] First Control Logic: yi [0038] Second Control Logic: Y. L; [0039] Third Control Logic: Y [0040] Logic output module: 1024 [0041] Comparison amplifier module: 1025 [0042] First comparison amplifier: 1 0251 [0043] Second comparison amplifier: 1 0252 [0044] Delay module: 1026 [0045] One sampling voltage: V, [0046] Second sampling voltage: ^; [0047] First time: [0048] Second time: t2 [0049] Relationship curve: h [0050] External reference voltage: / ref [0051] Third sampling voltage: V«_ 1003145696-0 096145634 Form number A0101 Page 12 of 18 Amendment April 14th, Amendment Replacement Page 1345691 [0052] Low-dropout linear regulator: 200. [0053] Voltage Sampling Module: 103 [0054] Third Time: ό [0055] Third Comparison Amplifier: 10253 [0056] ] First logic level: Ai [0057] Second logic level: A2 096145634 Form number A0101 Page 13 of 18 Page 1003145696-0