200923610 九、發明說明： 【發明所屬之技術領域】 本發明涉及一種穩壓裝置，尤其係關於一種低壓降線性 穩壓裝置。 【先前技術】 低壓降線性穩壓器（Low Drop-out Linear Regulator， LDO)係被廣泛應用於手機、DVD、數碼相機以及Mp3等 多種消費類電子產品中之穩壓晶片，為了滿足這些精密電 子產品之要求5在電源之輸入端加入線性穩壓器’以保證 電源電壓恒定與實現有源雜訊濾波。此外，這些電子產品 通常只有一組電池供電，為了節省供電池之電量，希望在 設備不工作時，LDO工作於睡眠狀態。為此，大部分LDO 都具有使能控制功能，從而方便用戶控制使用。 惟，該LDO在方便用戶使用之同時，存在一個無法避 免之問題：LDO之使能控制模組之邏輯工作電平沒有辦法 覆蓋一個連續之工作電平，從而造成當控制信號處於這個 不連續工作電平時候，使能控制模組處於浮動狀態（介於高 電平Η與低電平L之間之一個無法控制之階段），從而LDO 失去對輸出狀態之控制。 【發明内容】 有鑒於此，有必要提供一種解決低壓降線性穩壓器失 去對輸出狀態之控制問題之低壓降線性穩壓裝置。 一種低壓降線性穩壓裝置，其包括一個低壓降線性穩 壓器及一個電壓採樣模組，該低壓降線性穩壓器具有一個 7 200923610 控制邏輯之使能控制模組’該電壓採樣模組對 :、羅輯2穩壓器之輸出電壓進行採樣，並輸出第-控 、二"第一控制邏輯與該第二控制邏輯構成第三控制 趨輯0 制該生穩壓裝置，籍由該第三控制邏輯來控 :二l、‘性％壓器之輸出狀態，避免了因該使能控制 於洋動狀態而導致該低壓降線性穩壓器 處於失效模式。 【實施方式】 下面將結合附圖，舉以下較佳實施方式並配合圖式詳 細描述如下。 請參閱圖1，係本發明第-實施方式提供之一種低壓降 線性穩壓裝置1〇〇，該低壓降線性穩壓裝置1〇〇包括一個低 壓降線性穩壓器101及一個電壓採樣模組102。該低壓降線 性穩壓器101包括一個使能控制模組1〇11、動模組 1012、MOS開關模組1013、第四比較放大器1〇14及反饋模 組1015。該電壓採樣模組1〇2包括有一個邏輯輸出模組 1024、一個比較放大器模組1〇25及—個延遲模組1〇26，該 比較放大器模組1025具有第一比較放大器^0251與第二比 較放大器10252。 該低壓降線性穩壓器ιοί接收外部輸入電壓Vin，經内 部處理輸出電壓VQUt，以保證電源電壓恒定與實現有源雜訊 濾波。該電壓採樣模組102對該低壓降線性穩壓器1〇1之輪 出電壓Vcut進行分時採樣，得到第—採樣電壓％與第二採樣 8 200923610 • 電壓V2,並判斷該兩次採樣電壓Vi、v2之邏輯電平，得到 . 第一採樣電壓Vl之邏輯電平Ai與第二採樣電壓％之邏輯電 平A2，隶後，將八1與八2構成一個第一控制邏輯1。 該低壓降線性穩壓裝置100之使能控制模組1〇11輸出 具有-個參考電壓L㈣二控顧輯Υ2。該反饋模組 1〇15對該低壓降線性穩壓器皿之輸出電壓ν⑽進行即時採 樣，並分別送入該第四比較放大器1014、該第一比較放大 (' 斋10251與該延遲模組1026。該第四比較放大器1014接收該 反饋权組1015之輸出信號與該參考電壓Vref，並將該兩個信 號進行比較放大後輸出用來驅動動模組1〇12。該 第一比較放大器10251在第一時刻ti接收該反饋模組1〇15之 輸出^號，得到第一採樣電壓V :。該第一比較放大器丄〇 2 5工 將該第一採樣電壓Vi與該參考電壓Vref構成第一邏輯電平 A!。該第一比較放大器1〇252因為該延遲模組皿6之存在， 所以，在第二時刻t2接收該反饋模組1015之輸出信號，得到 ί 第一採樣電壓V2。該第二比較放大器10252將該第二採樣電 壓A與該參考電壓Vref構成第二邏輯電平八2。該邏輯輸出模 組1024接收該第一邏輯電平、與該第二邏輯電平，並構 成該第一控制邏輯Yl。該MOS驅動模組1012接收該第四比 車乂放大益拉組10M之輸出信號、該第二控制邏輯Y〗及該第 一控制邏輯Yl，並將該第二控制邏輯1與該第一控制邏輯 Υι構成第二控制邏輯Y。該]^〇8開關模組1〇13接收該低壓 降線性穩壓器101之外部輸入電壓Vin與該第三控制邏輯 Y ’用來控制該低壓降線性穩壓器1〇1之輸出電壓。 200923610 請+參閱圖2，係圖i中低壓降線性穩壓器1〇1之輸出電壓 /11^、蚪間t之關係曲線圖。該低壓降線性穩壓器之輸出 電壓v°ut與時間t之關係曲線為^，該電壓採樣模組102在 時刻對輸出電壓vQut之採樣電壓分別為Vi、。 知參閱圖3，係圖2中採樣電壓Vi、Vz對應之邏輯電平 \、八2與輪出電壓乂⑽之關係示意圖。“與。之間之時間間 隔為τ’在本實施方式中’咖2之間之時間間隔τ大於該低 堡降線性觀H1G1之軟啟動時間，以避免負載突然變化造 成，動作。籍由判斷Vl、V2對應之邏輯電平心、a2，得到 該第一控制埏輯丫1，其邏輯關係轉化為真值表可由下表工 戶斤示。 表1 輸入 輸入 輸出 Αι ^2 γ. 0 0 x 1 0 0 1 1 1 0 0 1 1 0 上表1可由以下邏輯關係式表示：。 該低壓降線性穩壓器101之使能控制模2 控制邏輯丫2與該第-控制邏糾，構成該第三控制^ Y，其邏輯關係轉化為真值表可由下表2所示。 200923610 表2 輸入 輸入 輸出 Υι γ2 Υ 0 0 0 0 1 1 1 0 1 1 1 1 上表2可由以下邏輯關係式表示： 因為Y!由該ν!、V2對應之邏輯電平A:、A2之邏輯關係 構成，所以，該Αχ、A2與該第二控制邏輯Y2、該第三控制 邏輯Υ之邏輯關係轉化為真值表可由下表3所示。 表3 輸入 輸入 輸入 輸出 Ai γ2 Υ 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 π 200923610 上表3可由以下邏輯關係式表示： Υ = (Α1+Χ；)χΥ2+Χ；ΧΑ2。 請參閱圖4,係本發明第二實施方式提供之一種低壓降 線性穩壓裝置200，該低壓降線性穩壓裝置200包括一個低 壓降線性穩壓器101及一個電壓採樣模組103。該第二實施 方式與該第一實施方式之區別在於，該電壓採樣模組103 對該低壓降線性穩壓器101之輸出電壓乂_進行即時採樣， 該電壓採樣模組103包括有一個第三比較放大器10253，且 該電壓採樣模組103接收一個外部參考電壓V’ref。該外部參 考電壓V’ref根據用戶之需求進行設置，因為該外部參考電 壓V’w決定了該低壓降線性穩壓器101之輸出電壓，所以該 外部參考電壓V’rei小於該使能控制模組1011之參考電壓 Vref。該第三比較放大器10253在t3時刻，接收該反饋模組 1015之輸出信號，得到第三輸出電壓V3。該第三比較放大 器10253將該第三輸出電壓V3與該外部參考電壓V’ref構成 該第一控制邏輯Y；l。 綜上所述，在第一、第二實施方式中，當該電壓採樣 模組102之邏輯輸出丫1為高電平Η時，無論該使能控制模組 1011之邏輯輸出Υ2處於什麼狀態，總邏輯輸出Υ關閉該 MOS開關模組1013;當丫1為低電平L時，Υ2為高電平Η時， 該MOS開關模組1013也關閉，Υ2為低電平L時，不對該MOS 開關模組1013做控制。這樣，就避免因該使能控制模組1011 處於浮動狀態而使該低壓降線性穩壓器101之輸出狀態處 於失效模式之問題出現。 12 200923610 < 綜上所述，本發明符合發明專利要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施方式，本 ' 發明之範圍並不以上述實施方式為限，舉凡熟悉本案技藝 之人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本發明第一實施方式提供之低壓降線性穩壓裝 , 置之功能模組圖。 圖2係圖1中低壓降線性穩壓器之輸出電壓與時間之 關係曲線圖。 圖3係圖2中採樣電壓之邏輯電平與輸出電壓之關係 示意圖。 圖4係本發明第二實施方式提供之低壓降線性穩壓裝 置之功能模組圖。 【主要元件符號說明】 低壓降線性穩壓裝置 100 電壓採樣模組 102 低壓降線性穩壓器 101 使能控制模組 1011 MOS驅動模組 1012 MOS開關模組 1013 第四比較放大器 1014 反饋模組 1015 參考電壓 Vref 第一控制邏輯 Υι 第二控制邏輯 γ2 第三控制邏輯 Y 邏輯輸出模組 1024 比較放大器模組 1025 第一比較放大器 10251 第二比較放大器 10252 延遲模組 1026 第一採樣電壓 Vi 13 200923610 第二採樣電壓 V2 第一時刻 h 第二時刻 h 關係曲線 Li 外部參考電壓 V’ref 第三採樣電壓 V3 低壓降線性穩壓裝置 200 電壓採樣模組 103 第三時刻 h 第三比較放大器 10253 第一邏輯電平 Αι 第二邏輯電平 A2 14200923610 IX. Description of the Invention: [Technical Field] The present invention relates to a voltage stabilizing device, and more particularly to a low-dropout linear voltage stabilizing device. [Prior Art] Low Drop-out Linear Regulator (LDO) is widely used in voltage regulators in a variety of consumer electronic products such as mobile phones, DVDs, digital cameras, and Mp3, in order to meet these precision electronics. Product Requirements 5 Add a linear regulator at the input of the power supply to ensure constant supply voltage and active noise filtering. In addition, these electronic products are usually powered by only one battery. In order to save power for the battery, it is desirable that the LDO be in a sleep state when the device is not operating. For this reason, most LDOs have an enable control function that is convenient for the user to control. However, while the LDO is convenient for users, there is an unavoidable problem: the logic operating level of the LDO enable control module cannot cover a continuous working level, causing the control signal to be in this discontinuous operation. At the level, the enable control module is in a floating state (an uncontrollable phase between the high level Η and the low level L), so that the LDO loses control of the output state. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a low-dropout linear regulator that solves the problem of controlling the output state of a low-dropout linear regulator. A low-dropout linear regulator device includes a low-dropout linear regulator and a voltage sampling module, the low-dropout linear regulator has a 7200923610 control logic enable control module 'the voltage sampling module pair :, the output voltage of the Luo 2 regulator is sampled, and the first control and the second control logic are combined with the second control logic to form a third control system. The third control logic controls: the output state of the '%-% voltage device, avoiding the low-voltage drop linear regulator in a failure mode due to the enable control being in the ocean state. [Embodiment] Hereinafter, the following preferred embodiments will be described in detail with reference to the accompanying drawings. Please refer to FIG. 1 , which is a low-dropout linear voltage regulator device according to a first embodiment of the present invention. The low-voltage drop linear regulator device includes a low-dropout linear regulator 101 and a voltage sampling module. 102. The low-dropout linear regulator 101 includes an enable control module 111, a dynamic module 1012, a MOS switch module 1013, a fourth comparison amplifier 1〇14, and a feedback module 1015. The voltage sampling module 1〇2 includes a logic output module 1024, a comparison amplifier module 1〇25, and a delay module 1〇26. The comparison amplifier module 1025 has a first comparison amplifier ^0251 and a first Second, the amplifier 10252 is compared. The low-dropout linear regulator ιοί receives the external input voltage Vin and internally processes the output voltage VQUt to ensure constant supply voltage and active noise filtering. The voltage sampling module 102 performs time-division sampling on the voltage Vcut of the low-voltage drop linear regulator 1〇1 to obtain a first sampling voltage % and a second sampling 8 200923610 • a voltage V2, and determines the two sampling voltages. The logic level of Vi and v2 obtains the logic level Ai of the first sampling voltage V1 and the logic level A2 of the second sampling voltage %, and thereafter, 八1 and 八2 constitute a first control logic 1. The enable control module 1 〇 11 output of the low-dropout linear regulator device 100 has a reference voltage L (four) two control Υ 2 . The feedback module 1〇15 instantaneously samples the output voltage ν(10) of the low-dropout linear regulator vessel, and sends the same to the fourth comparison amplifier 1014, and the first comparison amplification ('Zhai 10251 and the delay module 1026. The fourth comparison amplifier 1014 receives the output signal of the feedback weight group 1015 and the reference voltage Vref, and compares and amplifies the two signals to output the driving module 1〇12. The first comparison amplifier 10251 is in the first Receiving the output ^ of the feedback module 1〇15 at a moment ti, obtaining a first sampling voltage V: the first comparison amplifier 52 is configured to form the first sampling voltage Vi and the reference voltage Vref to form a first logic Level A! The first comparison amplifier 1〇252 receives the output signal of the feedback module 1015 at the second time t2 because of the presence of the delay module 6, and obtains a first sampling voltage V2. The second comparison amplifier 10252 forms the second sampling voltage A and the reference voltage Vref to form a second logic level 八 2. The logic output module 1024 receives the first logic level and the second logic level, and constitutes the first One control The MOS drive module 1012 receives the output signal of the fourth ratio yoke amplification group 10M, the second control logic Y and the first control logic Y1, and the second control logic 1 The first control logic Υ1 constitutes a second control logic Y. The switch module 1〇13 receives the external input voltage Vin of the low-dropout linear regulator 101 and the third control logic Y′ is used to control the low voltage. Decrease the output voltage of the linear regulator 1〇1. 200923610 Please refer to Figure 2, which is the graph of the output voltage of the low-dropout linear regulator 1〇1/11^ and the inter-turn t. The output voltage v°ut of the linear regulator is plotted against the time t. The sampling voltage of the voltage sampling module 102 at the time of the output voltage vQut is Vi, respectively. See Figure 3 for the sampling voltage in Figure 2. Schematic diagram of the relationship between the logic level \, 八2 and the wheeling voltage 乂(10) corresponding to Vi and Vz. The time interval between "and" is τ'. In the present embodiment, the time interval τ between the coffee makers 2 is greater than the low Fort fall linear view H1G1 soft start time to avoid sudden changes in load caused by action By judging the logical level heart corresponding to Vl, V2, a2, the first control set 丫1 is obtained, and the logical relationship thereof is converted into a truth table, which can be shown by the following table. Table 1 Input and output Αι ^2 γ 0 0 x 1 0 0 1 1 1 0 0 1 1 0 The above table 1 can be expressed by the following logical relationship: The enable of the low dropout linear regulator 101 controls the modulo 2 control logic 丫 2 and the first control logic Correction, constitute the third control ^ Y, and its logical relationship is converted into a truth table as shown in Table 2. 200923610 Table 2 Input input and output Υι γ2 Υ 0 0 0 0 1 1 1 0 1 1 1 1 Table 2 above The following logical relation is expressed: Since Y! is composed of the logical relationship of logic levels A: and A2 corresponding to ν! and V2, the Αχ, A2 and the second control logic Y2, the third control logic The logical relationship is converted to a truth table as shown in Table 3 below. Table 3 Input input and output Ai γ2 Υ 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 π 200923610 The following table 3 can be logically related Expression: Υ = (Α1+Χ;)χΥ2+Χ;ΧΑ2. Referring to FIG. 4, a low-voltage drop linear regulator device 200 according to a second embodiment of the present invention includes a low-dropout linear regulator 101 and a voltage sampling module 103. The difference between the second embodiment and the first embodiment is that the voltage sampling module 103 instantaneously samples the output voltage 乂_ of the low-voltage drop linear regulator 101, and the voltage sampling module 103 includes a third The amplifier 10253 is compared and the voltage sampling module 103 receives an external reference voltage V'ref. The external reference voltage V'ref is set according to the user's demand, because the external reference voltage V'w determines the output voltage of the low-dropout linear regulator 101, so the external reference voltage V'rei is smaller than the enable control mode. The reference voltage Vref of group 1011. The third comparison amplifier 10253 receives the output signal of the feedback module 1015 at time t3 to obtain a third output voltage V3. The third comparison amplifier 10253 forms the third output voltage V3 and the external reference voltage V'ref to form the first control logic Y; In summary, in the first and second embodiments, when the logic output 丫1 of the voltage sampling module 102 is at a high level, regardless of the state of the logic output Υ2 of the enable control module 1011, The total logic output Υ turns off the MOS switch module 1013; when 丫1 is low level L, when Υ2 is high level Η, the MOS switch module 1013 is also turned off, and when Υ2 is low level L, the MOS is not The switch module 1013 performs control. Thus, the problem that the output state of the low-dropout linear regulator 101 is in the fail mode due to the enable control module 1011 being in a floating state is avoided. 12 200923610 < In summary, the present invention complies with the patent requirements of the invention and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. All should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a functional block diagram of a low-dropout linear voltage regulator device according to a first embodiment of the present invention. Figure 2 is a graph showing the output voltage vs. time of the low-dropout linear regulator of Figure 1. Figure 3 is a schematic diagram showing the relationship between the logic level of the sampled voltage and the output voltage in Figure 2. 4 is a functional block diagram of a low-dropout linear regulator provided by a second embodiment of the present invention. [Main component symbol description] Low-dropout linear regulator device 100 Voltage sampling module 102 Low-dropout linear regulator 101 Enable control module 1011 MOS driver module 1012 MOS switch module 1013 Fourth comparison amplifier 1014 Feedback module 1015 Reference voltage Vref First control logic 第二 Second control logic γ2 Third control logic Y Logic output module 1024 Comparison amplifier module 1025 First comparison amplifier 10251 Second comparison amplifier 10252 Delay module 1026 First sampling voltage Vi 13 200923610 Two sampling voltage V2 First time h Second time h Relation curve Li External reference voltage V'ref Third sampling voltage V3 Low voltage drop linear voltage regulator 200 Voltage sampling module 103 Third time h Third comparison amplifier 10253 First logic Level Α second logic level A2 14