0960056TW 25362twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種注入鎖定除頻器，且特別是關於一 種增強注入信號’以擴大注入鎖定範圍之注入鎖定除頻器。 【先前技術】 隨著無線通訊的迅速發展，不僅增進了人類的生活品 質，也帶動了可觀的經濟利益。現今人們只需透過筆記型 電腦、個人數位助理或者手機，便可即時地進行資訊交換 及分旱。在無線通訊糸統中，頻率合成器（frequenCy synthesizer)為產生載波信號的重要元件，其内包含有除頻 器（frequency divider) ’用以將輸入信號進行除頻，以產生 所需頻率之信號。而此除頻器也廣泛地應用在多工器 (multiplexer)、鎖相迴路(phase locked loop)以及時脈產生器 等電路之中。 除頻器可分為兩大類，分別為數位除頻器及類比除頻 器。數位除頻器之實現架構有共模邏輯形式(common mode logic)以及動態邏輯形式(dynamic logic)，而類比除頻器之 實現架構則有米勒除頻器(miller divider)及注入鎖定除頻 器（injected-locked frequency divider)。一般的除頻器於高頻 運作下會消耗相當大的功率，造成系統的工作效能降低。 而射頻通訊系統中，注入鎖定除頻器因其最大工作頻率較 其他除頻器高，且功率消耗低，而從眾多種類的除頻器脫 拳頁而出。 0960056TW 25362nvf.doc/n 圖1繪示為傳統注入鎖定除頻器之電路圖。請參照圖 1，傳統注入鎖定除頻器10〇包括信號注入單元11〇及 共振槽120。信號注入單元11〇包括]^塑電晶體p卜用以 接收頻率為fl的注入信號Vinj。Lc共振槽12〇包括電感 II、12以及可變電容Cvl、Cv2，其透過控制信號Vtu狀 控制可變電容Cv卜Cv2兩端的電壓差，來調整除頻信號 si之振麵率f〇。當録辦f。接近注人信號vinj之頻 =fl的一半時，注入鎖定除頻器100便鎖定且透過A ' B 節點輸出頻率為(fi/2)的除頻信號S1。其中，N型電晶體 P2、P3以父叉耦合的方式產生負阻抗消除^匚共振槽 所產生之等效阻抗。 ，然而，當LC共振槽120之振盪頻率f〇與注入信號之 -半頻率(fi/2)相差甚矩時，注人鎖定除頻器⑽便盎法鎖 定除頻信號S1之頻率。—般而言，注人歡範即献心 比例值LR為最高能被歡之辭fiH，減去最低 月b被鎖定之鮮fIL ’而後再除以兩倍MC共振槽⑼之 =頻率fo，以數學型式表示即為LR=(fiH_fiL)/(2xf〇)。雖 …、、傳統注入鎖定除頻器議能運作於極高頻率下，但其主 要缺點在於注人觀範隨小，造成實際可義的範圍太 :右：ΐΐΪ可變電容CW、〜2來調整振盪頻率，仍無 ΐί 士鎖定範圍。另外，當注人信號Vinj注入電 j二;;注：^信號_於焊整上會有損耗，造成實際 注入#號Vmj哀減，也使得注入鎖定範圍變窄。 圖2，’’a不為傳統注入鎖定除頻器之電路圖。請參照圖 1344749 0960056TW 25362twf.doc/n L傳統注入鎖定除頻器㈣包括信號注入單元21〇及LC ^2()圖2之注入鎖定除頻器綱與圖1之注入鎖 100不同之處在於£(:共振槽220包含電感13及 二义；合Cv3〜cv4。由於電感13與可變電容Cv3〜Cv4並 ”電感13之兩端分別與交叉耗合之p型電晶體p4〜p5BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an injection-locked frequency divider, and more particularly to an injection-locked frequency divider that enhances the injection signal' to expand the injection locking range. [Prior Art] With the rapid development of wireless communication, it not only enhances the quality of human life, but also drives considerable economic benefits. Nowadays, people can exchange information and divide droughts instantly through a laptop, personal digital assistant or mobile phone. In a wireless communication system, a frequency synthesizer (frequenCy synthesizer) is an important component for generating a carrier signal, and includes a frequency divider 'to divide the input signal to generate a signal of a desired frequency. . This frequency divider is also widely used in circuits such as multiplexers, phase locked loops, and clock generators. The frequency dividers can be divided into two categories, namely digital frequency dividers and analog frequency dividers. The architecture of the digital frequency divider has common mode logic and dynamic logic, while the architecture of the analog frequency divider has a Miller divider and injection-locked frequency division. Injected-locked frequency divider. A typical frequency divider consumes a considerable amount of power at high frequencies, resulting in reduced system performance. In the RF communication system, the injection-locked frequency divider has a higher operating frequency than other frequency dividers and has low power consumption, and is out of the box of many types of frequency dividers. 0960056TW 25362nvf.doc/n Figure 1 shows the circuit diagram of a conventional injection-locked frequency divider. Referring to FIG. 1, the conventional injection locking frequency divider 10A includes a signal injection unit 11A and a resonance tank 120. The signal injection unit 11 includes a plastic transistor pb for receiving an injection signal Vinj having a frequency f1. The Lc resonant tank 12A includes inductors II and 12 and variable capacitors Cv1 and Cv2, which control the voltage difference between the variable capacitors Cv and Cv2 through a control signal Vtu to adjust the vibration plane rate f〇 of the frequency-divided signal si. When recording f. When the frequency of the injection signal vinj is half of fl, the injection lock frequency divider 100 locks and outputs the frequency-divided signal S1 having a frequency of (fi/2) through the A'B node. Among them, the N-type transistors P2 and P3 generate a negative impedance to eliminate the equivalent impedance generated by the resonant cavity by means of a parent-fork coupling. However, when the oscillation frequency f〇 of the LC resonance groove 120 is different from the half frequency (fi/2) of the injection signal, the frequency of the frequency-divided signal S1 is locked by locking the frequency divider (10). In general, the note value is LR is the highest can be happy words fiH, minus the minimum month b is locked fresh fIL ' and then divided by twice the MC resonance slot (9) = frequency fo, Expressed in mathematical form, it is LR=(fiH_fiL)/(2xf〇). Although..., the traditional injection-locked frequency divider can operate at very high frequencies, but its main disadvantage is that the scope of the injection is small, resulting in a practical range of right: right: ΐΐΪ variable capacitance CW, ~ 2 Adjust the oscillation frequency and still have no lock range. In addition, when the injection signal Vinj is injected into the electricity j 2;; Note: ^ signal _ there will be loss on the welding, causing the actual injection #Vmj sag, which also narrows the injection locking range. Figure 2, ''a is not a circuit diagram of a conventional injection-locked frequency divider. Please refer to FIG. 1344749 0960056TW 25362twf.doc/n L conventional injection locking frequency divider (4) including signal injection unit 21〇 and LC ^2() The injection locking frequency divider of FIG. 2 is different from the injection lock 100 of FIG. £(: Resonant slot 220 includes inductor 13 and ambiguous; Cv3~cv4. Since inductor 13 and variable capacitor Cv3~Cv4 are combined, the two ends of inductor 13 are respectively cross-consistent p-type transistors p4~p5
=接’以使注入鎖定除頻器雇能於交流電壓下正常運 t雖然交叉輕合之電晶體P4〜P5能消除Lc共振槽22〇 生之等效阻抗，但是電晶體p4〜P5所產生之寄生電容 2也會使注入鎖定除頻器細之振蘆頻率較圖ι之注入 ^除頻If 1G0低’也因此注人鎖定除頻器較不宜操 1於超高頻系統中’且與圖！之注入鎖定除頻器相同 地遭遇到注入信號Vinj衰減的問題。 ，此，如何解決注入鎖定除頻器注入鎖定範圍不足及 ^入㈣Vmj衰減的問題，以擴大其可應用的範圍，便成 為現今的重要課題之一。 【發明内容】 。本發明提供一種注入鎖定除頻器，其為增強注入信 唬’補償注入信號所受到的損耗’進而擴大注入鎖定範圍。 〇„ ，發明提出一種注入鎖定除頻器包括第一壓控振盪 态、第一信號注入單元以及匹配電路單元，其中第一壓控 振盪1§產生包含第一振盪信號及第二振盪信號之第一差動 振盪信號，且第一壓控振盪器包括第一 LC共振槽以及第 負阻單兀。第一 LC共振槽調整第一壓控振盪器之電抗 1344749 0960056TW 25362twf.doc/n 值，並共振產生第一差動振盪信號，第一 LC共振槽具有 第一連接端及第二連接端分別輸出第一振盪信號及第二振 盪信號。第一負阻產生單元耦接第一 [〇共振槽之第一連 接端及第二連接端’用㈣除第—Lc共簡所產生之等 ^且抗，使第-壓控減器持續振盪。第—信號注入單元 耗接連接端及第二連接端，㈣接收注人信號。匹配 電路單元祕第-信餘人單元，用輯人信號並 傳送注入信號至第一信號注入單元。 上述之注入鎖疋除頻器，在—實施例中匹配電路單元 ^括第-電容以及第-電感。第―電容之第—端接收注入 ’其第二端輕接第—信號注人單^。第—電感之第一 端轉接第-電容之第二端，其第二端减偏歷。 上述之注入鎖定除頻器，在—實施例中第一 共振 槽包括第-及第二電感、第—及第二可變電容。第一電感 之第一端為第一連接端，其第二端耦接第一電壓。第二電 感之第一端為第二連接端，其第二端耦接第一電壓。第一 可變電容之第一端耦接第一電感之第一端，其第二端接收 電抗控制信號。第二可變電容之第一端耦接第二可變電容 之第二端，其第二端耦接第二電感之第一端。其中，第一 LC共振槽依據電抗控制信號調整其電抗值。 上述之注入鎖定除頻器，在一實施例中第一 LC共振 槽包括第一電感、以及第一及第二可變電容。第一電感之 第^及第二端分別為第一及第二連接端。第一可變電容 之第一端耦接第一電感之第一端，其第二端接收電抗控制 9 c S ) 1344749 0960056TW 25362twf.doc/n ‘號第一可變電谷之第一端輕接第一可變電容之第二 端，其第二端耦接第一電感之第二端。其中，第一 LC ^ 振槽依據電抗控制信號調整其電抗值。 上述之注入鎖定除頻器，在一實施例中負阻產生單元 ⑽第-及第二開關。第—開關之第—端、第二端及控制 端分別麵接第-電壓、第-連接端及第二連接端。第二開 關之第、第一端及控制端分別輕接第一電壓、第二連 φ 接端及第一連接端。 亡述之注人鎖鎌頻器，在—實施例更包括第二壓控 振盪器、第二信號注入單元以及第一至第四開關，其中第 了壓控振Μ器產生包含第三振餘號及第四振盈信號之第 二差動振Μ賴，且第二壓控缝器包括第二LC共振槽 及第-負阻產生單元。第二LC共振槽調签該第二壓控振 盪器之電抗值，並共振產生該第二差動振齡號，第二lc f振槽具有第三連接端及第四連接端㈣輸㈣第三振盛 信號及該第四振盪信號。第二負阻產生單元耦接第二lc 鲁 共振槽之第三連接端及第四連接端，用以消除第二LC共 振7所產生之等效阻抗，使第二壓控振。^ ，信號注人單元減該第二壓控振盪器’用以接收注入信 號。第-開關之第-端及第二端分別耗接第—連接端及第 一電壓，其控制端接收第四振盪信號。第二開關之第一端 及第二端分別柄接第二連接端及第一電壓 第三振盪信號。第三開關之第一端及第二端分別=二 連接端及第-電壓，其控制端接收第一振盪信號。第四開 1344749 0960056TW 25362twf.doc/n 關之第-端及第二端分別輕接第四連接端及第一電壓，其 綱紐第二紐信號。其巾，匹配電路單元增強注入 • 信號，並傳送注入信號之第二信號注入單元。 本^明之注入鎖定除頻器為利用匹配電路單元來增 強注入信號，以補償注入信號因積體電路内部或者外部影 響所造成之損耗，進而擴大注入鎖定除頻器之注入鎖定範 圍。 φ 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉本發明之較佳實施例，並配合所附圖式， 作詳細說明如下。 【實施方式】 圖3A繪示為本發明之一實施例的注入鎖定除頻器之 架構圖。請參照圖3A，注入鎖定除頻器3〇〇包括壓控振盪 器310、信號注入單元32〇以及匹配電路單元33〇，其中壓 控振盪器310包括LC共振槽311及負阻產生單元312。壓 控振盪器310透過LC共振槽311，共振而產生包含第一振 盪信號Iout+及第二振盪信號Iout_之第一差動振盪信號 lout，且透過第一連接端N1及第二連接端N2分別輸出第 振盈彳§戒I〇\it+及第二振盈信號lout、。 負阻產生單元312耦接第一及第二連接端N1、N2， 用以消除LC共振槽312所產生之等效阻抗，使壓控振盪 器310持續振盪。信號注入單元320，耗接第一及第二連 接端N卜N2 ’用以接收一注入信號Vin。匹配電路單元= "Connected" so that the injection-locked frequency divider can be operated normally under AC voltage. Although the cross-connected transistors P4 to P5 can eliminate the equivalent impedance generated by the Lc resonant tank 22, the transistors p4 to P5 are generated. The parasitic capacitance 2 will also make the frequency of the fine-tuned reverberation of the injection-locked frequency divider lower than that of the injection of the frequency division If 1G0. Therefore, it is less suitable to lock the frequency divider in the UHF system. Figure! The injection lock frequency divider suffers from the same problem of attenuation of the injection signal Vinj. Therefore, how to solve the problem that the injection locking frequency divider injection locking range is insufficient and the (four) Vmj attenuation is extended to expand its applicable range has become one of the important topics of today. SUMMARY OF THE INVENTION The present invention provides an injection-locked frequency divider that compensates for the loss experienced by the injected signal □ to compensate for the injected signal and thereby expands the injection locking range. The invention provides an injection-locked frequency divider comprising a first voltage-controlled oscillation state, a first signal injection unit and a matching circuit unit, wherein the first voltage-controlled oscillation 1 § generates a first oscillation signal and a second oscillation signal a differential oscillation signal, and the first voltage controlled oscillator includes a first LC resonant tank and a first negative resistance unit. The first LC resonant tank adjusts a reactance of the first voltage controlled oscillator by 1344749 0960056TW 25362twf.doc/n, and Resonance generates a first differential oscillating signal, and the first LC resonant tank has a first connecting end and a second connecting end respectively outputting a first oscillating signal and a second oscillating signal. The first negative resistance generating unit is coupled to the first [〇 resonant tank The first connection end and the second connection end 'use (4) in addition to the -Lc reduction generated by the equalization and resistance, so that the first-voltage control reducer continues to oscillate. The first signal injection unit consumes the connection end and the second connection End, (4) receiving the injection signal. The matching circuit unit secret-letter unit, using the human signal and transmitting the injection signal to the first signal injection unit. The above-mentioned injection lock frequency divider, in the embodiment, the matching circuit single Include the first-capacitor and the first-inductor. The first-end of the first capacitor receives the injection', and the second end is connected to the first signal. The first end of the first-side inductor is switched to the second end of the capacitor. The second end depolarization is as described above. In the embodiment, the first resonant tank includes first and second inductors, first and second variable capacitors. The first end of the first inductor The first end is coupled to the first voltage, the second end of the second inductor is a second end, and the second end is coupled to the first voltage. The first end of the first variable capacitor is coupled The first end of the first inductor receives a reactance control signal, and the first end of the second variable capacitor is coupled to the second end of the second variable capacitor, and the second end of the second variable capacitor is coupled to the first end of the second inductor The first LC resonant tank adjusts its reactance value according to the reactance control signal. The above-described injection locking frequency divider, in one embodiment, the first LC resonant tank includes a first inductor, and first and second variable capacitors. The first and second ends of the first inductor are first and second terminals, respectively, and the first variable capacitor is first Coupling the first end of the first inductor, the second end receiving the reactance control 9 c S) 1344749 0960056TW 25362twf.doc/n 'the first variable electric valley first end is lightly connected to the second variable capacitor second The second end of the second inductor is coupled to the second end of the first inductor, wherein the first LC ^ tank adjusts its reactance value according to the reactance control signal. The above-described injection lock frequency divider, in one embodiment, the negative resistance generating unit (10) The first and second switches: the first end, the second end and the control end of the first switch are respectively connected to the first voltage, the first connection end and the second connection end. The first switch, the first end and the second switch The terminal is respectively connected to the first voltage, the second connection φ terminal and the first connection end. The discontinuity of the injection lock frequency converter, in the embodiment further comprises a second voltage controlled oscillator, a second signal injection unit and the first a fourth switch, wherein the first voltage controlled oscillator generates a second differential vibration signal including a third vibration number and a fourth vibration signal, and the second pressure control slitter includes a second LC resonance groove and - Negative resistance generating unit. The second LC resonant tank adjusts the reactance value of the second voltage controlled oscillator, and resonates to generate the second differential vibration age number, and the second lc f vibration groove has a third connection end and a fourth connection end (four) input (four) The three-vibration signal and the fourth oscillation signal. The second negative resistance generating unit is coupled to the third connection end and the fourth connection end of the second lclu resonant tank to eliminate the equivalent impedance generated by the second LC resonance 7, and to control the second voltage. ^, the signal injection unit minus the second voltage controlled oscillator ' is used to receive the injection signal. The first end and the second end of the first switch respectively consume the first connection end and the first voltage, and the control end receives the fourth oscillation signal. The first end and the second end of the second switch are respectively connected to the second connection end and the first voltage third oscillation signal. The first end and the second end of the third switch respectively have two terminals and a first voltage, and the control end receives the first oscillation signal. The fourth opening 1344749 0960056TW 25362twf.doc/n closes the first end and the second end respectively to the fourth connection end and the first voltage, and the second button signal. The towel, the matching circuit unit enhances the injection of the signal, and transmits a second signal injection unit that injects the signal. The injection locking frequency divider of the present invention uses a matching circuit unit to enhance the injection signal to compensate for the loss caused by the internal or external influence of the injection circuit, thereby expanding the injection locking range of the injection locking frequency divider. The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] FIG. 3A is a block diagram showing an injection locking frequency divider according to an embodiment of the present invention. Referring to FIG. 3A, the injection-locked frequency divider 3 includes a voltage-controlled oscillator 310, a signal injection unit 32A, and a matching circuit unit 33A, wherein the voltage-controlled oscillator 310 includes an LC resonance tank 311 and a negative resistance generation unit 312. The voltage-controlled oscillator 310 generates a first differential oscillation signal lout including the first oscillation signal Iout+ and the second oscillation signal Iout_ through the LC resonance tank 311, and transmits the first differential oscillation signal lout through the first connection terminal N1 and the second connection terminal N2, respectively. Output the first 彳 戒 戒 or I 〇 \ it + and the second vibration signal lout,. The negative resistance generating unit 312 is coupled to the first and second connecting ends N1 and N2 for eliminating the equivalent impedance generated by the LC resonant tank 312, so that the voltage controlled oscillator 310 continues to oscillate. The signal injection unit 320 consumes the first and second terminals Nb' to receive an injection signal Vin. Matching circuit unit
11 1344749 0960056TW 25362twf.doc/n 330輕^信號注入單元32〇,用以增強注入信號vin，並傳 主人L號Vin至彳s號注人單元MO。以下便詳細敘述各 功能方塊之運作。 圖3B繪示為本發明之一實施例圖3八的注入鎖定除頻 器之電路圖。請參照圖3B，匹配電路單元33〇包括電容 C1及電感L3。電容C1之第一端接收注入信號Vin，電容 ci之第二端耦接信號注入單元32〇。電感L3之第一端及 • ^二端分別耦接電容C1之第二端及偏壓Vbias。一般而 吕，焊墊(未繪示）為積體電路與外部信號或者元件電性連 接之"面菖/主入k號Vin經由焊整·及碎線(bonding wire) 傳送至注入鎖定除頻器300時，注入信號Vin必然會受其 材質影響而有所損耗’也因此造成實際傳送至鎖定除頻器 300之注入信號Vin較小。而本實施例利用電容匸丨及電感 1^3所組成之匹配單元電路33〇來增強注入信號Vin，以補 俏/主入彳§號Vin所受到的損耗及衰減’因此經增強之注入 信號Vin其振幅能較未補償之注入信號Vin來的大，進而 響 擴大注入鎖定除頻器3〇〇之注入鎖定範圍。 LC共振槽311具有第一及第二連接端Nl、>J2，且包 括電感L1〜L2以及可變電容CA1〜CA2。電感L1之第一端 為第一連接端N1 ’電感L1之第二端耦接電源電壓VDD。 電感L2之第一端為第二連接端N2，電感L2之第二端耦 接電感L1之第二端。可變電容CA1之第一端耦接電感L1 之第一端’其第二端接收電抗控制信號Vt。可變電容CA2 耦接可變電容CA1之第二端，其第二端耦接電感L2之第11 1344749 0960056TW 25362twf.doc/n 330 The light signal injection unit 32 is used to enhance the injection signal vin, and transmits the owner L number Vin to the 彳s number injection unit MO. The operation of each function block is described in detail below. 3B is a circuit diagram of the injection-locked frequency divider of FIG. 38 in accordance with an embodiment of the present invention. Referring to FIG. 3B, the matching circuit unit 33A includes a capacitor C1 and an inductor L3. The first end of the capacitor C1 receives the injection signal Vin, and the second end of the capacitor ci is coupled to the signal injection unit 32A. The first end of the inductor L3 and the second end of the ^2 are respectively coupled to the second end of the capacitor C1 and the bias voltage Vbias. Generally, the solder pads (not shown) are electrically connected to the external signals or components of the integrated circuit. The face/main entry k is transmitted to the injection lock through the soldering and bonding wires. At the time of the frequency converter 300, the injection signal Vin is inevitably damaged by its material', and thus the injection signal Vin actually transmitted to the lock frequency divider 300 is small. In this embodiment, the matching unit circuit 33A composed of the capacitor 匸丨 and the inductor 1^3 is used to enhance the injection signal Vin to compensate for the loss and attenuation of the 彳 号 V Vin. Therefore, the enhanced injection signal is enhanced. The amplitude of Vin can be larger than that of the uncompensated injection signal Vin, and the amplification is expanded to the injection locking range of the injection-locked frequency divider 3〇〇. The LC resonance groove 311 has first and second connection terminals N1, > J2, and includes inductances L1 to L2 and variable capacitances CA1 to CA2. The first end of the inductor L1 is the first terminal N1. The second end of the inductor L1 is coupled to the power supply voltage VDD. The first end of the inductor L2 is the second connection terminal N2, and the second end of the inductor L2 is coupled to the second end of the inductor L1. The first end of the variable capacitor CA1 is coupled to the first end of the inductor L1, and the second end thereof receives the reactance control signal Vt. The variable capacitor CA2 is coupled to the second end of the variable capacitor CA1, and the second end of the capacitor is coupled to the inductor L2
12 1344749 0960056TW 25362twf.doc/n 一端。LC共振槽311透過電感U〜L2及可變電容 CA1〜CA2交互運作，共振而產生包含第一及第二振盪信 號Iout+、lout-之第一差動振盪信號i〇ut，並透過第一及第 二連接端Nl、N2分別輸出第一及第二振盪信號1〇说+、 lout-，其中LC共振槽311透過電抗控制信號Vt(例如為一 直流電壓）改變LC共振槽311之電抗值，以調整第一差動 振盪信號lout之頻率。 另外，LC共振槽311更包括電晶體T2，其中電晶體 Τ2為一 Ρ型電晶體。電晶體Τ2之閘極及第一源/汲極耦接 電感L1之第二端，其第二源/汲極耦接電源電壓vdd。電 晶體Τ2可以視為一電流源，用以降低注入鎖定除頻器3〇〇 整體之電流，亦即所謂之電流限流，藉此降低注入鎖定除 頻器300之功率消耗。 信號注入單元320包括電晶體Τ1，其中電晶體τι為 一 Ν型電晶體。電晶體Τ1之閘極接收注入信號Vin，電 晶體T1之第一及第二源/汲極分別耗接第一及第二連接端 Nl、N2。信號注入單元320透過電晶體T1之切換，將注 入信號Vin與LC共振槽311所產生之第一差動振盪信號 lout混波。本實施例之注定鎖定除頻器300為一除二之除 頻器，因此當第一差動振盪信號lout之頻率接近注入信號 Vin之一半頻率時，注入鎖定除頻器300便鎖定且輸出第 一差動振盪信號lout。雖然在此假設電晶體T1為N型電 晶體，然非用以限定範圍，本領域具有通常知識者可以P 型電晶體替換之，或者採用一電流源將注入信號V i η注入。 13 < 5 ) 1344749 0960056TW 25362twf.doc/n 負阻產生單元3i2包括開關S1〜S2，其中開關Sl、S2 分別為- N型電晶體。開關S1之第一端、第二端及控制 端分別_接地電壓GND、第―及第二連翻N1、N2。 開關S2之第-端、第二端及控制端分別輕接接地電壓 GND、第一及第一連接端N2、m。負阻產生單元透 過將以N型電晶體實現之開關S1〜S2交絲合，產生負阻 抗來消除LC共振槽311所產生之等效阻抗，使壓控振盡 器310持續振盡。 值得一提的是，開關S1〜S2分別為以n型電晶體實現 之’因此開關S1、S2之第一端、第二端及控制端分別為N 型電晶體之第一源/汲極、第二源/汲極及閘極，而為使負 阻產生單元312能正常運作，N型電晶體需工作於飽和 區。在本實施例中，開關SI、S2之控制端及第二端之間 具有180度的相位差，亦即第一振盪信號I〇ut+與第二振盪 信號lout-之相位差為180度，也因此第一及第二振盪信號 I〇ut+、I〇ut-為互補式之信號，當開關S1、S2之第二端之 電壓上升時，開關SI、S2之控制端電壓隨之下降，使得 以N型電晶體實現開關si〜S2能有較長時間工作於飽和 區，並確保其轉導值為最大以抵消LC共振槽311所產生 之專效阻抗。 圖3C繪示為本發明之另一實施例圖3A的注入鎖定除 頻器之電路圖。請參照圖3B與圖3C ’實施例圖3C與實 施例圖3B不同之處在於，實施例圖3C之LC共振槽311 更加入了電感U5〜L16，其中電感L15之第一端及第二端 14 0960056TW 25362twf.doc/n 端及偏壓Vbias。本實施例為透過匹配電路單元43〇内元 件之運作，來增強注入信f虎Vin，以補償注入信號vin所 受到的損耗及或擴大注入鎖定範圍。 LC共振槽411包括電感L6及可變電容CA3〜CM。 電感L6之第-端及第二端分別為第—及第二連接端N卜 N2°可變電容CA3之第-端輕接電感16之第—端，其第 一端接收電抗控制#號Vt。可變電容CA4之第一端及第 ^端分別耦接可變電容CA3之第二端及電感L6之第二 端。其中，LC共振槽411透過電抗控制信號Vt改變可變 電容CA3、CA4之電容值’來調整LC共振槽411所產生 之第一差動振盈信號lout之頻率。 、另外，LC共振槽411更包括電晶體74,此電晶體T4 為了 Ρ型f晶體。電晶體Τ4之閘極减其第―源/没極， 其第一源/汲極耦接電感L6之第一端及第二端，其第二源/ $極耦接電源電壓VDD。電晶體Τ4具有電流限流之功 月t*，以實現低功率消耗之注入鎖定除頻器4〇〇。由於在交 流電廢運作下，第—及第二連接端N卜N2可以視為耦接 一，地電壓GND ’因此以並聯形式耦接之電感l6與可變 電谷CA3 CA4便無法共振產生第一差動振盈信號I〇ut。 在此’本實施例加入了負阻產生單元41沘，不僅可以消除 LC共振槽411之等效阻抗’更可藉此使LC共振槽411正 常運作。 本實施例之負阻產生單元412b包括開關S3〜S4,其中 開關S3〜S4為以p型電晶體實現之。開關幻之第一端、 1344749 0960056TW 25362twf.doc/n 第二端及控制端分別耦接電源電壓VDD、第一及第二連接 端N1、N2。開關S4之第一端、第二端及控制端分別耦接 電源電壓VDD、第二及第一連接端N2、N1。本實施例之 負阻產生單元412a、412b與實施例圖3B之負阻產生單元 312之運作相同，且信號注入單元42〇亦與實施例圖3B之 信號注入單元320之運作相同，故不加以贅述。 緩衝器441為以電晶體T4〜T5實現之一反相器，而緩 φ 衝器442為以電晶體Τ6〜Τ7實現之一反相器，其中電晶體 Τ4、Τ6分別為一 ρ型電晶體’且電晶體Τ5、Τ7分別為一 Ν型電晶體。緩衝器441、442為注入鎖定除頻器400之輪 出級，當注入鎖定除頻器4〇〇鎖定且輸出第一及第二振盪 信號Iout+、lout-時，可以透過緩衝器441、442增加第一 及第二振盪信號I〇ut+、I〇ut-的信號傳輸強度，避免信號受 負載效應影響而有誤差。值得注意的是，本領域具有通常 知識者可以透過本實施例之教示，將實施例圖4中匹配電 路單元430應用於上述實施例圖3B及實施例圖3C。 翁接著，將另舉一實施例說明如何實現一除四之注入鎖 定除頻益。圖5繪示為本發明之一實施例的注入鎖定除頻 器之電路圖。請參照圖5，注入鎖定除頻器5〇〇包括壓控 振盪器510、550、信號注入單元52〇、56〇、開關S15〜S18 以及匹配電路單元530’其中開關S15〜S18為以N型電晶 體實現之。壓控振盪器510產生包含第一及第二振盪信號 p〇ut+、p〇m-之第一差動振盪信號p〇ut，且壓控振盪器51〇 包括LC共振槽511及負阻產生單元512a、512b。壓控振 17 0960056TW 25362twf.doc/n 施例圖3B之匹配電路單元330或者實施例圖4之匹配電 路單元430。 開關S15之第一端及第二端分別耦接第一連接端N1 及接地電壓GND ’其控制端接收第四振盪信號Q〇ut_。開 關S16之第一端及第二端分別耦接第二連接端N2及接地 電壓GND ’其控制端接收第三振盪信號Q〇ut+。開關S17 之第一端及第二端分別耦接第三連接端N3及接地電壓 GND ’其控制端接收第一振盪信號p〇ut+。開關S18之第 一端及第二端分別耦接第四連接端N4及接地電壓gND , 其控制端接收第二振邊信號pout_。透過開關S15〜sig之 切換運作，可以產生分別具有〇。、9〇。、18〇。、27〇。相位之 第一〜第四振盪信號 P〇Ut+、P〇ut_、Q〇ut+、Q〇ut_。 在本發明另一實施例中，注入鎖定除頻器500可以如 冗施例圖4之說明於第一〜第四連接端N1〜N4分別加入緩 衝器，以增加第一〜第四振盪信號P〇ut+、p〇ut_、Q〇ut+、 Q〇m-之信號傳輸強度。另外，壓控振盪器51〇、55〇所分 別包括之LC共振槽511、551也可以如實施例圖3Β、圖4 之說明，加入電流限流之元件，以降低注入鎖定除頻器5〇〇 之功率消耗。 絲上所述，上述幾個實施例為利用匹配電路單元來增 強注入信號Vin，以補償注入信號Vin經焊墊及鎊線所^ 之損耗，進而擴大注入鎖定除頻器之注入鎖定範圍。又 —雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 1344749 0960056TW 25362twf.doc/n 脫離本發明之精神和範圍内’當可作些許之更動與潤飾， 因此本發明之保護範圍當祝後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 圖1纟會示為傳統注入鎖疋除頻益之電路圖。 圖2繪示為傳統注入鎖定除頻器之電路圖。12 1344749 0960056TW 25362twf.doc/n One end. The LC resonant tank 311 interacts through the inductors U1 to L2 and the variable capacitors CA1 to CA2 to generate a first differential oscillating signal i〇ut including the first and second oscillating signals Iout+, lout-, and transmits the first and second oscillating signals Iout+ The second connecting ends N1 and N2 respectively output first and second oscillating signals 1 + +, lout-, wherein the LC resonant tank 311 changes the reactance value of the LC resonant tank 311 through the reactance control signal Vt (for example, a DC voltage). To adjust the frequency of the first differential oscillation signal lout. In addition, the LC resonant tank 311 further includes a transistor T2, wherein the transistor Τ2 is a Ρ-type transistor. The gate of the transistor 及2 and the first source/drain are coupled to the second end of the inductor L1, and the second source/drain is coupled to the power supply voltage vdd. The transistor Τ2 can be regarded as a current source for reducing the current injected into the lock-up frequency divider 3, that is, the so-called current limit, thereby reducing the power consumption of the injection-locked multiplexer 300. The signal injection unit 320 includes an transistor Τ1, wherein the transistor τι is a Ν-type transistor. The gate of the transistor 接收1 receives the injection signal Vin, and the first and second sources/drains of the transistor T1 respectively consume the first and second connection terminals N1, N2. The signal injection unit 320 is switched by the transistor T1 to mix the injection signal Vin with the first differential oscillation signal lout generated by the LC resonance groove 311. The destined lock frequency divider 300 of the embodiment is a divide-by-two frequency divider, so when the frequency of the first differential oscillation signal lout is close to a half frequency of the injection signal Vin, the injection lock frequency divider 300 locks and outputs the first A differential oscillation signal lout. Although it is assumed here that the transistor T1 is an N-type transistor, it is not intended to limit the range, and those skilled in the art may replace the P-type transistor or use a current source to inject the injection signal V i η. 13 < 5 ) 1344749 0960056TW 25362twf.doc/n The negative resistance generating unit 3i2 includes switches S1 to S2, wherein the switches S1 and S2 are respectively -N type transistors. The first end, the second end, and the control end of the switch S1 are respectively _ ground voltage GND, first and second continuous turns N1, N2. The first end, the second end and the control end of the switch S2 are respectively connected to the ground voltage GND, the first and first connecting ends N2, m. The negative resistance generating unit eliminates the equivalent impedance generated by the LC resonance groove 311 by reciprocating the switches S1 to S2 realized by the N-type transistor to generate a negative impedance, so that the voltage-controlled vibrator 310 continues to be vibrated. It is worth mentioning that the switches S1 S S2 are respectively realized by an n-type transistor. Therefore, the first end, the second end and the control end of the switches S1 and S2 are respectively the first source/drain of the N-type transistor, The second source/drain and the gate, and in order for the negative resistance generating unit 312 to operate normally, the N-type transistor needs to operate in the saturation region. In this embodiment, the control terminal and the second end of the switches SI, S2 have a phase difference of 180 degrees, that is, the phase difference between the first oscillation signal I〇ut+ and the second oscillation signal lout- is 180 degrees, Therefore, the first and second oscillating signals I 〇 ut+ and I 〇 ut are complementary signals. When the voltage of the second ends of the switches S1 and S2 rises, the voltages of the control terminals of the switches SI and S2 are decreased, so that The N-type transistor realizes that the switches si to S2 can operate in the saturation region for a long time and ensure that the transduction value is maximum to offset the specific impedance generated by the LC resonator 311. 3C is a circuit diagram of the injection-locked frequency divider of FIG. 3A in accordance with another embodiment of the present invention. Referring to FIG. 3B and FIG. 3C, the embodiment of FIG. 3C differs from the embodiment of FIG. 3B in that the LC resonant tank 311 of the embodiment of FIG. 3C further includes inductors U5 L L16, wherein the first end and the second end of the inductor L15 are included. 14 0960056TW 25362twf.doc/n terminal and bias voltage Vbias. In this embodiment, the operation of the internal components of the matching circuit unit 43 is used to enhance the injection signal to compensate for the loss of the injected signal vin and to expand the injection locking range. The LC resonant tank 411 includes an inductor L6 and variable capacitors CA3 CMCM. The first end and the second end of the inductor L6 are respectively the first end of the first and second connecting ends N, and the first end of the variable capacitor CA3 is connected to the first end of the inductor 16, and the first end thereof receives the reactance control #Vt . The first end and the second end of the variable capacitor CA4 are respectively coupled to the second end of the variable capacitor CA3 and the second end of the inductor L6. Here, the LC resonance groove 411 adjusts the frequency of the first differential oscillation signal lout generated by the LC resonance groove 411 by changing the capacitance value of the variable capacitances CA3 and CA4 by the reactance control signal Vt. In addition, the LC resonant tank 411 further includes a transistor 74 for the f-type f crystal. The gate of the transistor Τ4 is reduced by its first source/no pole, and the first source/drain is coupled to the first end and the second end of the inductor L6, and the second source/$ is coupled to the power supply voltage VDD. The transistor Τ4 has a current limiting current of the current t* to achieve a low power consumption injection locking frequency divider 4〇〇. Since the first and second connection terminals Nb and N2 can be regarded as coupled one, the ground voltage GND' is thus coupled in parallel with the inductor l6 and the variable electric valley CA3 CA4 cannot resonate to generate the first Differential vibration signal I〇ut. Here, the negative resistance generating unit 41 is added to the present embodiment, and not only the equivalent impedance of the LC resonance groove 411 but also the LC resonance groove 411 can be normally operated. The negative resistance generating unit 412b of this embodiment includes switches S3 to S4, wherein the switches S3 to S4 are implemented by a p-type transistor. The first end of the switch, 1344749 0960056TW 25362twf.doc/n, the second end and the control end are respectively coupled to the power supply voltage VDD, the first and second terminals N1, N2. The first end, the second end, and the control end of the switch S4 are respectively coupled to the power supply voltage VDD, the second and first connection ends N2, N1. The negative resistance generating units 412a and 412b of the embodiment are the same as the negative resistance generating unit 312 of the embodiment of FIG. 3B, and the signal injection unit 42 is also operated in the same manner as the signal injection unit 320 of the embodiment FIG. 3B. Narration. The buffer 441 is an inverter implemented by the transistors T4 TT5, and the buffer 442 is an inverter implemented by the transistors Τ6 to Τ7, wherein the transistors Τ4 and Τ6 are respectively a p-type transistor. 'And the transistors Τ5 and Τ7 are respectively a Ν-type transistor. The buffers 441 and 442 are the round-out stages of the injection-locked frequency divider 400. When the injection-locked frequency divider 4 is locked and outputs the first and second oscillation signals Iout+, lout-, the buffers 441 and 442 can be increased. The signal transmission strengths of the first and second oscillating signals I〇ut+ and I〇ut- prevent the signal from being affected by the load effect and have errors. It should be noted that the matching circuit unit 430 of the embodiment of FIG. 4 can be applied to the embodiment FIG. 3B and the embodiment FIG. 3C through the teachings of the embodiment. Next, another embodiment will be described to explain how to implement a divide-and-four injection lock. Figure 5 is a circuit diagram of an injection-locked frequency divider in accordance with one embodiment of the present invention. Referring to FIG. 5, the injection locking frequency divider 5 includes a voltage controlled oscillator 510, 550, a signal injection unit 52A, 56A, switches S15 to S18, and a matching circuit unit 530', wherein the switches S15 to S18 are N-type. The transistor realizes it. The voltage controlled oscillator 510 generates a first differential oscillation signal p〇ut including first and second oscillation signals p〇ut+, p〇m−, and the voltage controlled oscillator 51 includes an LC resonance tank 511 and a negative resistance generation unit. 512a, 512b. Voltage Controlled Vibration 17 0960056TW 25362twf.doc/n The matching circuit unit 330 of the embodiment of FIG. 3B or the matching circuit unit 430 of the embodiment of FIG. The first end and the second end of the switch S15 are respectively coupled to the first connection end N1 and the ground voltage GND', and the control end thereof receives the fourth oscillation signal Q〇ut_. The first end and the second end of the switch S16 are respectively coupled to the second connection terminal N2 and the ground voltage GND', and the control terminal receives the third oscillation signal Q〇ut+. The first end and the second end of the switch S17 are respectively coupled to the third connection end N3 and the ground voltage GND', and the control end thereof receives the first oscillation signal p〇ut+. The first end and the second end of the switch S18 are respectively coupled to the fourth connection end N4 and the ground voltage gND, and the control end thereof receives the second vibration edge signal pout_. Through the switching operation of the switches S15 to sig, it is possible to generate 〇 respectively. 9, 〇. 18〇. 27〇. The first to fourth oscillation signals of phase P〇Ut+, P〇ut_, Q〇ut+, Q〇ut_. In another embodiment of the present invention, the injection-locked frequency divider 500 can be added to the buffers at the first to fourth connection terminals N1 to N4, respectively, as described in the description of FIG. 4 to increase the first to fourth oscillation signals P.信号ut+, p〇ut_, Q〇ut+, Q〇m- signal transmission strength. In addition, the LC resonant tanks 511 and 551 respectively included in the voltage controlled oscillators 51A and 55A may also be added with current limiting components as shown in FIG. 3A and FIG. 4 to reduce the injection locking frequency divider 5〇. The power consumption of 〇. As described above, in the above embodiments, the matching circuit unit is used to enhance the injection signal Vin to compensate for the loss of the injection signal Vin through the pad and the pound line, thereby expanding the injection locking range of the injection locking frequency divider. Further, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art, without departing from the spirit and scope of the present invention, is not limited to 1344749 0960056TW 25362 twf.doc/n. 'When a few changes and refinements are made, the scope of protection of the present invention is defined by the scope of the patent application. [Simple description of the diagram] Figure 1纟 shows the circuit diagram of the traditional injection lock. 2 is a circuit diagram of a conventional injection-locked frequency divider.
圖3A繪示為本發明之一實施例的注入鎖定除頻器之 架構圖。 Dl> 圖3B繪示為本發明之一實施例的注入鎖定除頻器 電路圖。 " 圖3C繪示為本發明之另一實施例圖3A的注入鎖定除 頰器之電路圖。 ’、 圖4繪示為本發明之一實施例的注入鎖定除頻器之電 路圖。3A is a block diagram of an injection-locked frequency divider according to an embodiment of the present invention. Dl> Figure 3B is a circuit diagram of an injection lock frequency divider in accordance with one embodiment of the present invention. " Figure 3C is a circuit diagram of the injection locking wiper of Figure 3A in accordance with another embodiment of the present invention. 4 is a circuit diagram of an injection lock frequency divider according to an embodiment of the present invention.
圖5繪示為本發明之一實施例的注入鎖定除續 路圖。 器之電 【主要元件符號說明】 VDD :電源電壓 GND :接地電壓 Vtune :控制信號 Vinj、Vin :注入信號 S1 :除頻信號 20 1344749 0960056TW 25362twf.doc/n vt:電抗控制信號 ‘ Iout、P0ut、Q〇ut:差動振盪信號 II〜13、L1〜L16 :電感FIG. 5 is a diagram showing an injection lock division process according to an embodiment of the present invention. Device power [main component symbol description] VDD: power supply voltage GND: ground voltage Vtune: control signal Vinj, Vin: injection signal S1: frequency division signal 20 1344749 0960056TW 25362twf.doc/n vt: reactance control signal 'Iout, P0ut, Q〇ut: Differential oscillation signal II~13, L1~L16: Inductance
Cvl〜Cv4、CA1〜CA8 :可變電容 C1〜C2 :電容 A、B:節點 N1〜N4 :連接端 P1〜P5、TKT9 :電晶體 S1〜S14 :開關 100、200、300、400、500 :注入鎖定除頻器 110、210、320、420、520、560 :信號注入單元 120、220、311、411、5U、551 : LC 共振槽 310、410、510、550 ··壓控振盪器 312、412a、412b、512a、512b、552a、552b :負阻產 生單元 330、430、530 :匹配電路單元 # 441〜442:缓衝器 21Cv1 to Cv4, CA1 to CA8: variable capacitors C1 to C2: capacitors A, B: nodes N1 to N4: connection terminals P1 to P5, TKT9: transistors S1 to S14: switches 100, 200, 300, 400, 500: Injection locking frequency dividers 110, 210, 320, 420, 520, 560: signal injection units 120, 220, 311, 411, 5U, 551: LC resonance slots 310, 410, 510, 550 · Voltage controlled oscillator 312, 412a, 412b, 512a, 512b, 552a, 552b: negative resistance generating unit 330, 430, 530: matching circuit unit # 441 to 442: buffer 21