TWI343529B - Method and apparatus for performing full transfer automation in a usb controller - Google Patents

Description

1343529 IX. Description of the invention: * [Technical field to which the invention pertains] This application relates to a general serial bus (USB) data transfer architecture and method. More specifically, the present application relates to a USB data transfer architecture and method for increasing the amount of data transferred in a peripheral device. [Prior Art] USB peripheral devices such as data storage devices containing non-volatile memory are commonly used in home and business computing environments for reliable data storage of compact and portable packages. The (10) peripheral device of this type may include a (10) controller that establishes an interface with a USB physical layer (PHY) device using a protocol f and a back-end circuit that communicates with the flash memory. When a host connected via a USB connector of a USB device wishes to write to or read from the USB device, the command and data are presented by an appropriate USB protocol and in an appropriate format according to an agreed standard. These USB standards are designed with a theoretical maximum data transfer rate. Although the USB standard will theoretically support these maximum data rates, due to limitations of the storage media and associated circuitry, the performance of the usb data storage device may not actually achieve the maximum data rate. The USB controller management data in the USB data storage device is transmitted to and from the USB data storage device. Typically, data is sent in batches of known length and exchanged messages are exchanged between the host and the U S B device to manage timing and error checking during data transfer. A method of processing USB peripheral devices for data exchange is to execute a plurality of firmware on an internal microprocessor in response to a processor interrupt generated by moving or moving the data from the buffer with each batch of data. instruction. However, the involvement of the firmware can significantly affect the throughput of the 127934.doc 1343529 material. Each interrupt will delay other actions that the internal microprocessor may participate in, or wake the microprocessor from any temporary sleep or idle mode, and will likely take time to identify, interpret, and act on the instruction for the interrupt. Therefore, the microprocessor operation in the USB controller can slow down the data transfer rate and increase the power consumption in the USB device. [Summary of the Invention]

To address the need for an improved USB controller architecture and method of transferring data, it is proposed to have a full transfer automation decommissioner that can reduce or avoid the use of firmware and microprocessors during certain data transfer functions.

According to the -th aspect, a method of implementing full transfer automation in the _universal serial bus (10) B) controller is disclosed. The method includes receiving, at the USB controller, a data transfer start message from the host and transmitting the data packet during the -USB mass data transfer operation. During a data transfer phase of the mass data transfer operation, a hardware generated logic signal is exchanged between the delete controller=a host interface module and the backend module for a data transfer state in the delete controller. . In the implementation, the parent switching hardware generates a logic signal, which may include generating a buffer in a backend module of the USB controller during the mass data transfer operation to indicate that the buffer memory is ready to transmit or transmit the data. (4) At least the back-end hardware logic signal of the storage medium. In addition, the switching hardware generates a logic signal to generate at least one host interface module hardware logic signal in one of the host interface modules of the USB controller, so that a large amount of data is transferred to read or write. During operation, the back-end module and host interface module can be configured with 127934.doc 1343529, and each other can carry out (4) the status of the USB controller (4). In the other-style sample towel, In the controller, the method of full transfer automation includes receiving the _Usb mass data transfer start message of the USB large transfer write operation at the delete controller, and initializing in the delete controller. Fully transmitting the automatic mode. During the deletion of the mass transfer write operation, at the (10) controller, the data packet is received from the host, and at the same time as receiving the data packet, the host interface module is deleted Between a back-end module, a hardware-generated logic signal is exchanged for the data transfer state in the controller. In the implementation of the generation, the method of fully transmitting the automation is disclosed in a controller. Pots In the t =! device 'self-host receiving, b mass transfer read operation: (four) transfer start message 'and the coffee controller in the coffee control (four) start a full transfer automation mode. In the mass transfer read During the operation period, the full transmission automation mode may include transmitting data packets from the coffee controller to the host, and transmitting the data packets while the USB control benefits the host interface module and a back module. Between the groups, the hardware generated logical information about the data transfer status in the (10) controller is disclosed in the other way as a general-purpose column bus (USB) controller for use in the Cong peripheral device. The delete controller may include a rear end module that is configured to transfer data or transfer a large amount of storage medium such as non-volatile memory. The module communicates with the backend module to configure H to communicate with the host 127934.doc 1343529. The backend module and the host interface module are also configured to be used during the "hulk data transfer read or write operation". Via hardware logic signals This performs communication regarding the state of delivery of the message within the brain controller. In another example, a universal serial bus (USB) peripheral device is described. The USB peripheral device may include, for example, non-volatile memory. A large amount of storage medium adapted to receive data from a host and a USB controller or to provide data to the host and the uSB controller.

The USB controller can include a buffer memory back module that is configured to transfer data to or from the mass storage medium. In addition, the controller may include a host interface module that communicates with the backend module and is configured to communicate with the host device, wherein during a large amount of data transfer read or write operations, the back end mode The group and host interface modules are configured to communicate with each other about a data transfer state within the USB controller via hardware logic signals.

Other features and advantages of the present invention will become apparent upon review of the appended claims. [Embodiment] FIG. 1 is a block diagram showing a universal serial bus (USB) peripheral device 10 connected to a host 12 via a USB communication line 14. The host computer 2 can be a USB port of a personal computer or any electronic component having USB capability such as an MP3 player, a mobile phone, etc. The USB communication line 14 can be a USB peripheral device 1 via a standard USB connector to the direct USB of the host 12 Connected, or may include an interventional USB function such as wire thief. As shown in Figure i, the USB peripheral device 1 can be a flash memory thumb drive (thumb 127934.doc • 9. 1343529 drive) configured for mass data storage. The USB peripheral device includes a USB controller 16 composed of a Host Interface Module (HIM) 8, a Buffer Management Unit (BMU) 20, a Flash Memory Interface Module (FIM) 22, and a Central Processing Unit (CPU) 24. The usb controller 16 communicates with the USB communication line 14 external to the USB peripheral device 10 and also with the flash memory % contained in the USB peripheral device 1A. Although one or more components of the usb controller 16 can be configured as discrete components, in one embodiment the 'HIM 18, BMU 20, FIM 22, and CPU 24 are all formed in a single special purpose integrated circuit (ASIC). on. Also, although flash memory is described, other non-volatile memories or mass storage media are contemplated. Referring now to Figure 2, the HIM is shown in more detail. The HIM 18 includes a physical layer interface 28, such as a USB 2® physical interface for bonding with a USB serial bus data line on one side and a UTMI interface on the other side. The physical layer interface 28 extracts clock information and data from the serial stream, checks received data for errors, performs NRZI decoding, bit extraction, serial to parallel conversion, and then sends the data to the USB device core. The layer interface 28 also performs the inverse function to translate the data received from the USB device core 30 in the UTMi column data format into a USB serial data format. In one implementation, the UTMI transmission can be a side-by-side 30 MHz 16-bit bus. In other implementations - any of a number of digital interface standards that can be used for USB applications - instead of UTMI - such as UTMI+ or ULPI - can implement a physical layer interface in any of a number of USB 2 〇 PHY IP core configurations 28, such as the configuration of Chipidea Microelect Mnica SA which can be constructed in Lisb〇n, Portugal. In addition, the physical layer interface 28 can support high speed (480 Mbps), full speed (12 Mbps) and low speed 127934.doc -10·1343529 (1·5 Mbps) data transfer rate conforming to the USB 2.0 specification. The USB device core 30 includes media storage. A control (MAC) controller 32 and a direct memory access (DMA) block 36 are taken. Each communicates with the CPU 24 via a microprocessor interface to allow the CPU 24 to read and write to the USB device core 30 registers to set and trigger USB transactions and to respond to the transaction events reported by the USB device core 30. And the status changes. The MAC controller 32 communicates with the physical layer interface 28 via the UTMI data path, parses all USB tokens received from the host, and generates response packets. In addition, the MAC controller 32 is responsible for all error checking, checking pad generation, USB handshake format, ping commands, and data response packets, as well as any signals that must be generated based on USB timing requirements. The DMA block 36 is in communication with the MAC controller 32 and is responsible for moving all of the flash memory 26 to be transferred to or from the USB peripheral device 1 between the USB device core and the buffer RAM (BRAM) in the BMU 20. data. In one implementation, when managing data transfers such as USB mass data input or output transfer (also referred to as mass data read or write transfer, respectively), DMA block 36 completely transfers the automation (FTA) interface to the USB peripheral via USB. The BMU 20 in device 10 communicates to exchange hardware logic to generate a handshake signal. A data bus connection such as the BVCI interface connects the DMA block 36 to the CPU 24. In addition, DMA block 36 maintains the content information and builds configurable FIFO buffers 42, 44 between MAC controller 32 and DMA block 36. These FIFOs decouple the system processor memory bus request from the tight timing required by the USB protocol itself and offset the internal clock frequency that affects the timing of data transfer between the DMA block 36 and the MAC controller 32. difference. 127934.doc 11 1343529 Multiple FIFO channels can be maintained for each of the active endpoints in the system. The size of the TX and RX FIFO buffers is determined based on the number of supported device endpoints, and the worst case latency for obtaining the bus and extracting a data block. In one implementation, the USB core 30 can be an IP core from Chipidea Microelectronica S.A, of Lisbon, Portugal. Any of a number of other 1{> cores from other USB IP core providers may also be used. The HIM 18 also includes an FTA register 46 and an FTA logic module 48. The FTA register 46 is configured to receive setup information for enabling the full transfer automation mode, wherein as described in more detail below, the USB controller 16 can utilize hardware to generate logic signals rather than interrupted CPU actions and firmware. Instructions to manage the movement of data blocks to and from BRAM. The FTA register also maintains information such as the current transfer status as the hardware generates a logic signal that is incremented by the expected number of data blocks transferred in the bulk data transfer. The fta module 48 contains hardware logic for generating an internal handshake signal when the USB controller 16 is operating in the FTA mode. The Auxiliary Interface 5 can contain a secondary scratchpad with firmware for the processor to handle various tasks such as CPU sleep or wake-up routines. 3 illustrates the remainder of the USB controller 16 and shows the flash memory 26 of the USB peripheral device 10 (collectively referred to herein as the USB peripheral device 1〇end 52) buffer management unit (BMU) 2〇 An automatic buffer manager (ABM) 54 that communicates with the bram % can be included. The BRAM 56 can be partitioned in a variety of ways, for example, to provide a bulk packet for transmitting or receiving a large amount of data transfer to or from the flash memory 26 (such as deleting a 512-bit block in a high speed application). The first buffer 58 and the second buffer. 127934.doc 12· 1343529 BMU 2〇 communicates with Flash Interface Module (FIM) 22 coordinated between BMU 2G and Flash Memory%. In order to implement full transfer automation in the edge device 1G and correspondingly assist in increasing data speed and power consumption, the peripherals include several modifications to the standard USB control architecture to provide additional hardware in the USB controller 16 using hardware logic. Internal grip. It can be implemented in the hardware logic of the controller, and the additional details of the verses 18 and (4) 52

The Ministry of Communication holds the message to eliminate the need for certain traditional mobile implementation steps involving the CPU 24. USB^ supports four types of transmission/endpoints ^: control transfer, interrupt transfer, isochronous transfer, and mass transfer. As referred to below as tH, mass transfer involves large bursts of data processed in fixed length blocks and can benefit most from the full transfer automation described herein. In the implementation, (10) the controller 调用 invokes the full transfer automation described herein only during a large number of data transfer tasks.

And the use of the cum; or the known cpu-based delivery mechanism for isochronous endpoints, control endpoints, or interrupt endpoints. Regarding the large amount of data transmission under the USB standard, a p&I described in the figure is provided, and the CBW (command block packet) is sent to the peripheral device 1 at the mth host 丨2, and the message is buffered. In the BRAM 46 of the management unit 20 (at step 62). The CBW message is 31 bytes and ζ_> includes information about the type of transmission that the USB peripheral device 1 will perform. After receiving the 4 CB W message, The USB peripheral device (for example, in the interest and write data to the HIM 18 device 46. In more detail on the 24 main RAM (MRAM) below) read the full transfer automation (FTA) temporary storage in this message 127934.doc -13· 1343529 The FTA register 46 includes information such as the start address, buffer size, and transfer direction in the BRAM 56. After the CBW phase, a large data transfer data phase occurs and the host 12 Sending a data packet to (either a large number of output transfer or write operations) the USB peripheral device 10 or receiving a data packet from it (a large number of input transfer or read operations) depending on the transfer direction indicated in the CBW message (steps 64, 66) The end of USB mass data transfer The segment is a csw (command state packet) message for ending the exchange between the host I2 and the USB peripheral device 1 (at step 68). Referring to FIG. 5, after receiving the CBW message from the host 12 in the first stage, the CPU executes the toughness. The body writes the data necessary to implement the FTA program to the FTA register 46. The register table 76 in FIG. 5 includes a memory unit address 78 representing the memory unit of the circular buffer (BRAM), and a circular buffer. The base address 80, the end address 82, and the word address of the brAM base address and the end address. The current address 84 is updated by the hardware when the FTA transfer is performed to point to the memory location currently involved in the transfer. The FTA register table % also includes the transfer size 86 (based on the total number of expected blocks (data packets) p current transfer size 88 is the block that is updated by the hardware during the ongoing FTA transfer, and the tracking data packet has been The number of transmitted descriptors. The transfer descriptor link list base address 90 contains the data transfer descriptor (dTD) link list of the word base address, and the transport (Tx) 92 and receive (RX) 94 automated transport automation controls contain endpoints based on Control transfer automatically Information of the feature, and the endpoint transfer completion register 96 indicates a large number of output transfers (data from the host output) or a large number of data input transfers (data input host) at the end state after all data packets have been transmitted. Endpoint MISC Control 98 Includes instructions for forcing the USB device core 30 to respond with an acknowledgment (ACK) token during the output of the 127934.doc • 14· 1343529. The stop transfer control 100 register includes a control bit to stop the full transfer. The automated process, and the transfer automation state 102 contains a state of hardware updates as each data transfer descriptor and data query header is set up. The Tx FIFO Low-Scale Configuration Register 1〇4 defines the threshold for pre-fetching of the TX FIFO register for the read (1) when the FTA mode of the USB controller 16 is enabled and When the data shown in the data table % of Figure 5 is loaded into the FTA register 46, the USB controller 16 also prepares the endpoint data transfer descriptor (dTD) and the endpoint data header (dQH) data structure. In the structure setup, as shown in FIG. 6, the USB controller 16 also generates FTA enablement data, and the FTA enablement data includes: an enable bit 7〇, which is a USB device that will enable full transfer automation for a specific data transfer data exchange. The flag of the core 3〇; and the xfer direction bit 72, which indicates the direction of the transmission. The packet length of the transaction 1〇6 and the total expected byte ι8 can also be combined with the BRAM required for each expected data packet. The DMA indicator 1缓冲器9 of the buffer address is recorded in the data structure. These data structures can be generated by the hardware logic in the FMA module 48 of the HIM 18, or by the firmware executed by the CPU 24. Implementation. Depending on the amount of data expected, more than one may be required Material structure to identify indicators 109 for processing each of the set of addresses required for a large number of data transfers. The dTD and dQH data structure information is written to the appropriate offset to accommodate the dTD and The size of the FTA temporary storage refers to the location pointed to by the key address 90. The dTD and dQH data structures inform the DMA block 36 in him 18 of the total transfer size, DMA source/destination address, and 127934. .doc •15· 1343529 Other transmission information. Once the CBW message has been processed, the dTD and dQH data have been set up and the initial information in the FTA register is generated, the USB controller 16 is ready to process the data transfer in the FTA mode and eliminate it. Or reduce the amount of data in the data transfer. As shown in Figure 7, 'a description of the use of the USB controller 162fTA mode of a possible speed device a large number of output transactions. This example shows that there are two buffers available in BRam for support When the data transfer starts, when the host 12 transmits the output of the data transfer 112 followed by a data block (also referred to as a data packet), a large number of output data transmission phases are opened. Assuming that the USB peripheral device 10 operates in the high speed mode, the data packet size can be 512 bytes. The USB peripheral device (7) receives the information at the output ^^ 18 and passes the message to the BMU 20 for storage in the configuration. One of the buffers 58, 60 in the BRAM 56. The ABM M in the BMU 2 provides hardware logic generation signals buf_rdyi II4 and buf_rdy2 II6 indicating that the buffers are ready to receive information. Data transfer, ABM "Buffer_bud and buf_rdy2 nickname based on the buffer counter counting the number of free buffers in the BRAM" can be used to generate buf_rdyl & buf - using any of a number of types of digital counter circuits. The buffer count II of the logical H of 2 digits. The buf-rdyl signal indicates the availability of at least one buffer state in the BRAM, and buf-rdy2 indicates the availability of two or more buffers in the BRAM. In this embodiment, the term "buffer" refers to a contiguous 512-bit location in the BRAM. After the transfer of the first data packet to the buffer is completed, since buf_rdy2 and bUf"dyl are both at the beginning of the transfer, Π (high), _ 18 is I27934.doc 16 1343529 triggers the MAC controller 32 to the host 1 2 Send a confirmation (ack) 11 6 message. At the same time, the FTA module 48 in the HIM 18 generates an "early release" signal pulse via the hardware. The signal pulse is communicated back to the BMU 20 to inform the BMU 20 that the transfer of the data packet has been completed. In response to this release signal, BMU 20 determines that buf_rdy2 is a lower representation of the fact that two or more buffers are unavailable. Again, the BMU can then instruct the FIM 22 to begin writing this data to the flash memory 26. An output token from the host is received at the USB peripheral device 1 and the accompanying data packet transfer places the data in a second buffer in two dedicated buffers in BRAM 56. The HIM 18 interprets the combination of buf_rdyl and buf-rdy2 in its status table at the beginning of the transfer, and sends a NYET parental grip § 120 to the host 12 (buf_rdy2 = 0, buf rdyl = l). At the same time, the HIM 18 sends another early release signal 122 (or equivalent final release signal) to the BMU 20 in the back end to cause the BMU 20 to know that the transfer has been completed. After notifying this release, the backend 52 sends a buf_rdyl low signal via the BMU 20 in addition to transmitting the already low buf-rdy2 signal to indicate to the HIM 18 that no buffers 58, 60 are currently available. The NYET message 120 conveys to the host 12 that the previous data transfer was received, but the host 12 may not send more information without first checking the status. In the case of FIG. 7, the host 12 transmits a piNG token 124 to the USB peripheral device 1. Note that both the buf_rdy2 and buf_rdyl signals are at logic low, indicating that no buffer is currently available, and the HIM 18 responds with a NAK response 126. When one of the buffers becomes available (represented by the logic high setting of buf_rdyl generated by the ABM 54 hardware logic), the USB peripheral device receives the subsequent PING from the host, and 127934.doc 17 1343529 HIM with ACK Response 128 responds to inform the host that it is ready to receive subsequent data. In the example of Figure 7, for a large number of output data transfers, the buffer ready signals (buf_rdy2 and buf_rdyl) are the hardware numbers generated by the automatic buffer manager 44 in the BMU 20. The hardware implementation signal may be based on basic digital logic responsive to data occupying the first buffer 48 and the second buffer 50, wherein buf_rdy2 may be from a counter in the BMU 20 that maintains a count of valid buffers present in the BRAM 56. Out. If the count value from the counter exceeds a threshold, the ABM will determine a buf_rdy2 high signal. This threshold value is configurable and can be set by firmware. In USB data transfer, the threshold is set to 2. When the counter value in the BMU is greater than or equal to 1, the additional hardware implementation logic in the ABM 54 generates a buf-rdyl high signal. Therefore, when both buffers are ready, the buf_rdy 1 and buf_rdy2 handshake signals generated by Abm and sent to the HIM are high. When both buffers are not ready, both handshake signals are low. And when only one buffer is available 'buf_rdy 1 is high and buf_rdy2 is low. In one implementation, the counters are used to generate buf_rdyl and buf_rdy2 signals to identify the number of free buffers in BRAM 56. The HIM 18 utilizes the buffer availability signals of buf_rdyl and buf-rdy2 to generate responses to the received and received PING tokens from the host 12. The state diagram 130 of the USB handshake packet generated by the USB controller 16 in response to the three valid combinations of the buf_rdyl and buf_rdy2 signals for the OUT token and the ping token is shown in FIG. When both buffers are ready (both availability signals are at logic high or 丨), HIM 18 answers the OUT or PING token to produce a 127934.doc 1343529 ACK response packet. When both buffers are unavailable (both availability signals are at logic low or zero), HIM 18 responds with a 0UT4PING token to generate a NAK response packet. When only one buffer is ready, the resulting response packet is different for the OUT token and the PING token. ACK is generated for piNG and NYET is generated for OUT. In the opposite direction, a handshake signal from the HIM 18 to the BMU 2〇 in the back end 52 is also generated. The early release signal and the final release signal are hardware generated by the digital logic in the FTA module 38 that can be implemented as the HIM 18. Logic signal. Depending on whether the USB controller 16 is processing a large amount of output data transfer (an example of the transfer seen in Figure 7) or a large amount of input data transfer (an example of the transfer shown in Figure 9), the FTA alone 38 early _ _ _ And the final release of the handshake message is based on different input information. For large output data transfers, the early release signal is equivalent to the final release signal. In the case where the A quantity output f material is transmitted, the FTA module 48 derives the early release signal from the success data packet transmission signal generated by the MAC controller 32 of the USB core. For high speed (10) large

The quantity output is transmitted, and a successful data packet transmission signal is triggered upon receiving a 512-bit packet. In the case where the data packet size can be 64-byte full-speed or low-speed USB mass output transmission, the MAC controller information is used to count 8 successful data packet transmissions before the early release/final release signal is triggered. Referring to Figure 9, the buffer availability (kiss and bufjdy2) discussed above and the buffered H release (early #release and final release) hardware generate a handshake message to illustrate a large number of input transmission scenarios. In a large number of input transmissions, the data is transferred from the flash memory in the peripheral device to the host. Similar to 127934.doc • 19· 1343529 A large number of output transfers, the CBW message is received by the HIM 18, which places the CBW message in the BRAM 56 of the BMU 20. The HIM 18 then notifies the CPU 24 that the CBW message has been received, and the CPU 24 then reads the message from the BRAM 56 and initializes the FTA register 48 in the HIM. The data transfer indicator and data headers necessary for the amount of data indicated in the CBW message are generated, and the FIM 22 begins reading the data packet from the flash memory 26 into the buffer of the BRAM 56. Again assuming that there are two buffer configurations in BRAM 46, once the data from the first buffer is transferred from the BMU to the HIM, the HIM 18 sends an early release logic pulse to the BMU 20.

The early release hardware signal is generated by the FTA module 48. In this example, the early release of the hardware signal and the final release of the hardware signal differ because the FTA module 48 derives the early release signal and the final release signal, respectively. The BMU 20 uses the early release signal to pre-fill the transmit (read) data to the TX FIFO 44 to check buffer availability. If the BMU receives an early release signal when the buffer in the BRAM is not ready, the BMU negates the buf_rdyl signal (i.e., the signal goes low) to prevent the HIM 18 from prefetching data from the buffer. In a large amount of input data transfer, when the HIM 18 initiates a read of data from the TX FIFO 44 to the host 12, the FTA module 48 generates an early release based on the logic signals generated in the MAC controller 32. The final release signal confirms the early release and sends a message to the BMU: since the ACK response has been received from the host, the packet can eventually be released. The FTA module 48 generates a final release signal based on a logic signal generated in the MAC controller 32 indicating that an ACK was received from the host. Since the signals from the MAC controller 32 are generated in a different frequency domain than that used by the FTA module 48, the FTA module also includes the MAC 127934.doc -20-1343529 controller 32 signal from the MAC. The controller's USB PHY clock domain is converted to the circuitry of the system clock domain through which the fta module operates. The first early release signal 丨32 in the bulk input transfer scenario of Figure 9 indicates to ΒΜϋ 20 that if the second BRAM buffer 50 is available, it is now suitable to fill the input read data into the buffer space of the buffer. Attributable to fast

The data transfer rate between flash memory 26 and BRAM buffers 58, 60 is typically slower than from BRAM buffers 58, 60 via HIM 18 to host 12, and HIM 18 will pre-populate from BRAM to TX FIFO register 44. The data is fetched and the data is simultaneously sent from the TX FIFO 44 register to the host 12. The final released hardware signal 134 is sent from the HIM 18 to the BMU 20 only after receiving an ACK message 136 from the host indicating that the previous data packet was successfully received. The second IN symbol 138 and the third IN symbol 140 and the data transfer packets 142, 144 are illustrated in FIG. Between the second transmission and the third transmission, there is a USB peripheral device 10 that is not generated from the host and is generated in the USB peripheral device.

The bus has a timeout of 146. Since no acknowledgment was received from the host, mM did not produce a final release signal and did not see an early release signal for the next transmission. This is because the same data from the second transmission must be resent in the absence of an acknowledgment that the first attempt was received correctly. The above example assumes that the buf_rdy 1 signal is always high, indicating that the flash memory % has completed a read operation and that valid data in the BRAM buffer is available. If the buffer is not ready for some reason, then buf-kiss! The signal can be kept low and _ 18 can transmit a nak handshake packet to the host based on this buf_rdyl low signal. At the end of the USB mass data input or output transfer, the engine 48 reaches the transfer size at 127934.doc •21 - ^43529 The transmission is automatically stopped. A request for a csw message is also received from the host at the end of a large number of transfers. In response, the object prepares the CSW and also sends it to the host at the end of the Af transfer. Prepare cs W as a response firmware and send it back to the host. While the data transfer is being carried out in the FTA enabled, this implementation does not hinder the transmission and delivery to other endpoints. The use of hardware signals generated in HIM 18 and BMU 20 to provide hardware handshake to increase the ability of USB peripherals to read and write data is illustrated in a number of output transfer scenarios and in a large number of input transfer scenarios. Each data burst is unused or requires a physical interrupt that requires CPU intervention. Transferring data into or out of flash memory (and, in general, USB peripherals) without the need for participation and interruption, avoids triggering, is read by the CPU, and acts on the time necessary for the interrupt. The logical result is that CPU activity will not be required during this data transfer phase, and thus the total power usage of USB peripherals can be saved. Another advantage of using hard-handed handshakes between the backend and him for buffer space-available communication is that 'the memory size in the buffer can be maintained at a lower level' and the release is otherwise planned for other uses. Buffer memory. In addition, the CPU overhead is reduced and the CPU clock speed can be reduced compared to the implementation that requires firmware tracking data transfer and management buffer space without interrupts and CPU intervention. Lower clock speed implementations based on lower CPU overhead can also contribute to additional power savings. Although an example of the rear end 52 in the USB controller 16 has been provided (in which the FTA mode has been allocated for implementing a large number of data transfer operations), 127934.doc -22. 丄州529 In other implementations, only 俅Use 罝― • Use the early buffer. The buffer can have a single data transfer block size. Alternatively, the USB controllers and methods described above can be adapted to use more than two buffers in the BRAM, each of which can have the same size as the data packet. In other implementations, such as when performing USB peripherals in full speed mode or low speed mode (12 million bits per second or 15 million bits per second, instead of 480 million bits per second in high speed mode) , fta operation mode can be adjusted to adapt to the full-speed mode or low-speed mode supported material tuple data = package large λ!... In other implementations, USB peripheral device 1 () can be configured to be opposite to a host and The same FTA mode is used for a large number of transfer operations as described. 'Although the specific data packet size is discussed, for example, 512 bytes for high speed and one byte for full speed and low speed, but can be selected for USB according to selection. The size of the data processed by the backend is set to other lengths by the type of flash memory in the rear end of the peripheral device. The following simultaneous application (December 31, 2006), co-owned US patent application (by US Patent Application Serial No. "USSN" cited) is incorporated herein by reference: "Selectively Powering Data

Interfaces" (with USSN 1 1/649, 325 and agent reference sdA-1076x); ‘‘Selectively Powered Data Interfaces’’ (with USSN 1 1/649, 326 and agent reference number SDA-1076y); "lnternaiiy

Protecting Lines at Power Island Boundaries" (with USSN 1 1/618, 874 and agent reference number SDA-1090x); "lntegrated Circuit with Protected Internal Isolation" (with USSN 1 1/618,875 and agent reference number SDA-1090y); "Updating Delay 127934.doc -23- 1343529

Trim Values" (with USSN 1 1/618, 897 and agent reference number 80 8-1091x); "Module with Delay Trim Value Updates on Power-Up" (with USSN 1 1/618, 898 and agent reference number 80-8-1091y "Limiting Power Island Inrush Current" (with USSN 1 1/618,855 and agent reference number SDA-1092x); "Systems and Integrated Circuits with Inrush-Limited Power Islands" (with USSN 1 1/618,854 and agents) Reference number SDA-1092y); "Method for Performing Full Transfer Automation in a USB Controller" (with USSN 1 1/618, 865 and agent reference number -10口八-1094x (105 19/201)); MUSB Controller with Full Transfer Automation" (with USSN 1 1/618, 867 and agent reference number 80 eight-1094y (10519/202); "Method for Configuring a USB PHY to Loopback Mode" (with USSN 1 1/618,849 and agent reference number SDA- 1095x (10519/203)); and "Apparatus for Configuring a USB PHY to Loopback Mode" (with USSN 1 1/61 8,852 and agent reference number SDA-1095y (10519/204)). A method and apparatus for implementing full transfer automation in a USB controller has been described. Four new hardware generated logic signals have been provided within the USB controller in the USB peripheral for the host interface module and The handshake between the back-end modules improves the data transfer speed and reduces the power consumption of the USB controller via hardware logic rather than through the use of the internal blade and microprocessor internal timing signals. The foregoing embodiments are to be considered as illustrative and not restrictive, and the scope of the claims BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a USB peripheral device connected to a host. 2 is a block diagram of a host interface module of a round rUSB peripheral device. Figure 3 is a block diagram of the rear end of a Usb controller suitable for use in the USB peripheral device of Figure 1. Figure 4 is a flow chart of a USB mass transfer operation. Figure 5 is a register table of data prepared to facilitate full transfer automation in the USB peripheral devices of Figures 1 through 3. Figure 6 is a data structure for a large amount of data transfer in the peripheral device of Figure 1; Figure 7 is an example of USB high speed mass output transaction using the USB peripheral device of Figure 1. Figure 8 is a state diagram illustrating the logic for generating a USB handshake packet in response to receipt of a plurality of data transfer tokens. Figure 9 is an example of a USB high speed mass input transaction using the liUSB peripheral device. [Main component symbol description] 10 USB peripheral device 12 Host 14 USB communication cable 16 USB controller 18 Host interface module (HIM) 20 Buffer management unit (BMU) I27934.doc -25- 1343529

22 24 26 28 30 32 36 38 40 42 44 46 48

50 52 Flash Memory Interface Module (FIM) Central Processing Unit (CPU) Flash Memory Physical Layer Interface USB Device Core Media Access Control (MAC) Controller Direct Memory Access (DMA) Block Full Transfer Automation (FTA) Module Microprocessor Interface Configurable FIFO Buffer Configurable FIFO Buffer/Automatic Buffer Manager/TX FIFO/TX FIFO Scratchpad Full Transfer Automation (FTA) Scratchpad Full Transfer Automation (FTA Logic Module / First Buffer / FTA Engine Auxiliary Interface / Second Buffer / Second BRAM Buffer Back End 54 Auto Buffer Manager (ABM) 56 BRAM 58 First Buffer / BRAM Buffer 60 Second Buffer /BRAM Buffer 70 &&_Enable Bit 72 xfer_* to Bit 76 Register Table / FTA Register Table / Data Table 127934.doc • 26- 1343529 78 Memory Unit Address 80 Cyclic Buffer Base Address 82 Circular Buffer End Address 84 Circular Buffer Current Address 86 Transfer Size 88 Current Transfer Size 90 Transfer Descriptor Link List Base Address 92 Transfer (Τχ) Transfer Automation Control 94 Receive (Rx) Transfer Automation Control 96 end Point Transfer Complete Register 98 Endpoint MISC Control 100 Stop Transfer Control 102 Transfer Automation Status 104 Tx FIFO Low Label Configuration Register 106 Packet Length 108 Total Bytes 109 DMA Indicator 110 Output Symbol 112 Data Transfer 114 Hardware Logic generates signal buf_rdy 1 116 hardware logic generates signal buf_rdy2 signal/acknowledgement (ACK) 120 NYET handshake message 122 another early release signal 124 PING symbol 127934.doc 27· 1343529 126 NAK response 128 ACK response 130 status table 132 An early release signal 134 finally releases the hardware signal 136 ACK message 138 a second IN token 140 a third IN token 142 a data transfer packet 144 a data transfer packet 146 a bus time 127934.doc -28-

Claims (1)

1343529 Patent Application No. 096151485^ Chinese Patent Application Substitution Replacement (December 99) Supplementary Coffee (10) X. Patent Application Range: 1·- Kind of implementation in a universal serial bus (USB) controller ^Transfer automation method, the method comprises: 'a host receives a USB mass data transmission at a USB controller to send a start message; transmits a data packet during a USB mass data transfer operation; and in the mass data transfer operation During a data transfer phase, between the host interface module of the USB controller and a back-end module, the hardware directly generates a logic signal for the data transfer state of the USB controller. The logic signal generated by the hardware is not stored as / intermediate data between the host interface module of the USB controller and the back end module. 2. The method of claim 1, wherein the switching hardware generates a logic signal comprising: generating at least one backend hardware logic signal in the backend module of the USB controller during the USB mass data transfer operation, The back end hardware logic signal indicates that a buffer memory is ready to transfer data into or out of a large amount of storage medium; and at least one host interface module hardware logic signal is generated in the host interface module of the USB controller. The backend module and the host interface module are configured to pass the backend hardware logic regarding the data transfer state in the USB controller during a USB mass transfer read or write operation The signal and the host interface module hardware logic signals communicate with each other. 3. The method of claim 2, wherein the USB mass data transfer reads or writes 127934-991221.doc «43529 operation includes data transfer of data in a plurality of discrete portions, each of the discrete portions having A fixed length, and wherein the at least one back end hardware logic signal includes the buffer memory to be ready to process one of the plurality of discrete portions. 4. The method of claim 3, wherein the buffer memory comprises at least one buffer having a buffer size equal to the fixed length. 5. The method of claim 3, wherein generating at least one back-end hardware logic signal comprises communicating to the host interface module During the incoming operation, at least one buffer is operable to receive one of the plurality of discrete portions. 6. The method of claim 3, wherein the buffer comprises a first buffer and a second buffer, each of the first buffer and the second buffer having a buffer equal to the fixed length And wherein generating at least one back end hardware logic signal comprises: during the USB mass data transfer write operation, only one of the first buffer and the second buffer is operable to receive the plurality of discrete One of the portions generates an I first buffer ready hardware logic signal, and at least two buffers are available to receive one of the plurality of tool segments during a USB bulk beacon write operation When 'generates a second buffer ready hardware logic signal. The method of claim 6, further comprising responding to receiving from the host, receiving the packet, and preparing the hardware logic signal and the second buffer based on the first buffer received from the backend module The hardware logic signal is ready to generate a USB handshake message. 127934-991221.do, 9. The method of month length item 4, further reading the operation period gate, / 纟 USB big data transfer part between the buffers can be used to receive the plurality of discrete-buffer crying 1 When the backend module transmits '' to the host interface module. . Prepare the hardware logic signal. The method of the second item 8 further includes responding to the transmission of the starting data from the FlF buffer of the main "face core group to the host== one-send read operation, from the host interface module The backend '^ early buffer releases the hardware logic signal. The method of item 9 further includes receiving, in response to receiving from the host, a true-to-hold note, transmitting from the host interface module to the back-end module during a bulk data transfer read operation - final buffering The device releases the hardware logic signal. The method of claim 9 further includes: transmitting a buffer ready hardware logic signal from the backend module to the host; the buffer is ready for the hardware logic signal indicating a large amount of USB During the data transfer capture period, the at least one buffer can be used to transmit the plurality of cutters. One of the P points; and if the early buffer release of the more limb Q number# is received at the back end, the buffer ready hardware signal indicates that the 4 buffer is ready, then a large amount of data is transmitted During the read operation, a data pre-fetch from the buffer memory to one of the FIF buffers is initiated. 12. A method of implementing full transfer automation in a universal contiguous bus (USB) controller, the method comprising: at the USB controller, receiving from a host for a USB mass transfer 127934-99I221.doc 1343529 sends a write operation - (10) a large amount of data transfer start message, and initializes a full transfer automation mode in the USB controller; during the USB mass transfer write operation, at the (10) controller, receives from the host Data packet; and receiving the data packet, and directly exchanging hardware generation information about a data transmission state in the (10) controller between the host interface module and the back end module of the coffee controller The logic signal, between the host interface module of the controller and the back end module, the logic signal generated by the hardware is not stored as intermediate data. The method of claim 12, wherein the receipt, the receipt of the packet includes receiving a plurality of data in the vertical portion, each of the discrete portions having a fixed length 'and wherein the exchange hardware A logic signal is generated from the backend mode and at least one buffer ready hardware logic signal is transmitted to the host interface module. #妙项13的方法, where the passer is at least one buffer ready 2 ft number contains: the backend two during the -(10) mass transfer write operation? There is a buffer that can be used to receive the plurality of discrete parts: two-two module transmission: the first buffer is ready for the back end to the USB to a large amount of shell material to convey the write #期, 'to V two The buffer may be configured to receive one of the plurality of discrete portions to send a second buffer to prepare a hardware logic signal to the host interface module. 15. If the request item is 14 * + The body logic signal further includes: when the 1st group has received the complete data packet, the master 127934-991221.doc 1343529 machine interface module transmits a buffer to the back module to release the hardware logic signal. The method of claim 15, wherein transmitting the buffer to release the hardware logic signal comprises transmitting the buffer to release a hardware logic signal after the host interface module receives a USB ACK handshake message. A method of implementing full transfer automation in a universal serial bus (USB) controller, the method comprising: receiving, at the USB controller, a large amount of USB data for a USB mass transfer read operation from a host Starting to send the message, and initializes a fully automatic mode of transfer in the USB controller; f01 transmitting a read operation of a large number of the USB, transmit data from the controller Cong packet to the host computer; and While transmitting the data packet, the hardware generation logic of the data transfer state of the (10) controller is directly exchanged between the host interface module and the back end module of the USB controller. The logic signal generated by the hardware is not stored as intermediate data between the host interface module of the coffee controller and the back end module. 18. The method of claim 17, wherein the transmission data packet comprises data in a plurality of portions of the transmission, each of the discrete portions having a solid 2 = and wherein the switching hardware generates a logic signal from the host The medium=group transmits at least one buffering and transferring hardware logic to the backend module. 19. The method of claim 18, wherein transmitting the at least one logic signal comprises: when the host interface module opens a buffer to release the hardware When transmitting a J27934-99I22I.doc 1343529 data packet to the host, transmitting a first it to the backend module, and releasing the hardware (4) and when the transmission of the data packet is completed, the n buffer Release the hardware logic signal. 20. 21. 22. 23. The method of claim 19, further comprising the backend module transmitting a buffer ready hardware logic signal to the host interface, the buffer ready for the hardware logic signal indication In the backend - when the buffer is ready to transfer data to the host interface unit. A USB controller for use in a universal serial bus (USB) peripheral device. The USB controller includes: a backend module having a buffer configured to transfer data into or out of a plurality of storage media And a host interface module in communication with the backend module and configured to communicate with a host, wherein the backend module and the USB data transfer read or write operation The host interface module is configured to communicate directly with each other via a hardware logic signal regarding a data transfer state within the USB controller, wherein the host interface module and the back end module are associated with the The hardware logic signal of the data transfer status is not stored as intermediate data. The USB controller of claim 2, wherein the USB mass data transfer read or write operation comprises data transfer of data in a plurality of discrete portions, each of the discrete portions having a fixed length, and wherein The data transfer status includes the buffer memory processing ready for processing one of the plurality of discrete portions. The USB controller of claim 22, wherein the buffer memory comprises at least l27934-991221.doc 1343529 a buffer having a buffer size equal to the fixed length. 24. The USB controller of claim 23, wherein the backend module includes hardware logic configured to communicate to the host interface module - the buffer is ready for a hardware logic signal, the buffer The ready-to-use hardware logic signal indicates that the at least one buffer is available to receive the plurality of discrete portions during a USB bulk data transfer write operation 25. The USB controller of claim 22, wherein the buffer memory comprises a first buffer and a second buffer, wherein each of the first buffer and the second buffer has a value equal to the fixed a buffer size of length, and wherein the backend module includes hardware logic configured to: communicate a first buffer ready hardware logic signal to the host interface module, the first buffer The hardware logic signal indicates that during the -USB mass data transfer write operation, only one of the first buffer and the second buffer, the buffer is operable to receive the plurality of "parts"; And communicating to the host interface module __Second buffer ready hardware logic signal 'The second buffer ready hardware logic signal means: during a USB mass data transfer write operation, at least two:: The device can be configured to receive one of the plurality of discrete portions. 26. The coffee controller of claim 25, wherein the host interface module includes a cryptographic logic signal in response to a punctured packet received from the host and in response to receipt from the backend module And the second buffer is ready for the USB handshake packet generation logic of the hardware logic signal to generate a USB handshake packet for transmitting to the host. 27. The controller of claim 21, wherein the host interface module comprises: 127934-991221.doc 1343529 A direct 6 memory access (DMA) block is configured to manage the transfer in and out of the Data transfer of the buffer; and a MAC controller in communication with the DMA block, the mac controller configured to format and generate a USB handshake and data response packet for communication to the host. 28' The USB controller of claim 23, wherein the backend module includes hardware logic configured to communicate a buffer ready hardware logic signal to the host interface module, the buffer The ready hardware logic signal indicates that the at least one buffer is available to receive one of the plurality of discrete portions during a USB bulk data transfer read operation. 29. The controller of claim 28, wherein the host interface module includes a FIFO buffer and is configured to transmit in response to data transfer from the buffer to the host. An early buffer release hardware logic signal is generated to the backend module during the read operation. 3. The controller of claim 29, wherein the host interface module L is configured to respond to receipt of a confirmation handshake from the host to the backend during a bulk data transfer read operation The module generates a final buffer to release the hardware logic signal. 31. The USB back control module of claim 29 includes hardware ό ^ ^ ^ ^ = the hardware logic is in a state (4) the host interface module communicates 1 ready hardware logic signal, the buffer is ready Hardware exhaustion: During the (10) mass data transfer read operation, the up to 4 buffers can be used for one of the discrete components of the value of 4 $. '· Progress is configured to receive the 127934.991221.do, 1343529 - period buffer at the back end, after the hardware logic signal is released, if the buffer is ready for the hardware logic signal to indicate that the buffer is ready, then During a large data transfer item fetch operation, a data pre-fetch from the buffer memory to the FIF buffer is initiated. 32. The USB controller of claim 25, wherein the fixed length of the buffer size is 5 1 2 bytes. 33. The USB controller of claim 25, wherein the first buffer and the second buffer comprise contiguous memory spaces. 34. A universal serial bus (USB) peripheral device, the USB peripheral device comprising: a plurality of storage media adapted to receive data from a host or provide data to the host; and a USB controller comprising: a back-end module having a buffer memory configured to transfer data into or out of the mass storage medium; and a host interface module that communicates with the back-end module and is configured to The host communicates, wherein during a USB mass data transfer read or write operation, the backend module and the host interface are modular and configured to communicate via a data transfer status with respect to one of the USB controllers The logic signals communicate directly with each other, wherein the hardware logic signal is not stored as intermediate data between the host interface module and the back end module. 35. The USB peripheral device of claim 34, wherein the USB mass data transfer read or write operation comprises one of a plurality of discrete portions of the data 127934-99l221.doc 1343529 transmitted, each of the discrete portions of the material The person has a fixed length, and wherein the data transfer status includes the buffer memory processing one of the plurality of discrete portions being ready. 36. The USB peripheral device of claim 35, wherein the buffer memory includes at least one buffer having a buffer size equal to the fixed length. 37. The USB peripheral device of claim 36, wherein the backend module includes hardware logic configured to communicate a buffer ready hardware logic signal to the host interface module, the buffer The device ready hardware logic signal indicates that the at least one buffer is available to receive one of the plurality of discrete portions during a USB data transfer write operation. 38. The USB peripheral device of claim 35, wherein the buffer memory includes a first buffer and a second buffer, each of the first buffer and the second buffer having one equal to the a fixed length buffer size, and wherein the back end module includes hardware logic, the hardware logic group can: communicate to the host interface module - the first buffer ready hardware logic (four), the first The buffer ready hardware logic signal indicates that during the deletion of a large data transfer write operation, only one of the first buffer and the third money buffer is operable to receive the plurality of discrete cutters; The host interface is ready for the hardware logic signal, the first...the younger, the friend of the family is ready for the hardware logic to transfer one of the first parts during the write operation. The peripheral device for receiving the last plurality of discrete As, such as the request item 38, the host interface module includes l27934-99122l.doc 1343529 in response to the USB token packet received from the host and responding to the backend The modulo, and the received first buffer ready hardware logic signal and the second buffer ready hardware logic signal USB handshake packet generation logic to generate a USB handshake packet for transmission to the host. 40. The USB peripheral device of claim 34, wherein the mass storage medium comprises a non-volatile memory. % 41 is the USB peripheral device of claim 40, wherein the non-volatile record. The 13⁄4 body contains flash memory. 127934-991221.doc