1343039 * » 九、發明說明： 【發明所屬之技術領域】 ' 本發明係有關於一種顯示裝置，其係尤指顯示裝置之時序控制電路及 : ' 時序控制方法。 m 【先前技術】 • 現今科技蓬勃發展’資訊商品種類推陳出新，滿足了大眾不同的需求。 早期顯示器多半為陰極射線管（Cathode Ray Tube，CRT)顯示器，由於其 φ 體積龐大與耗電量大，而且所產生的輻射線對於長時間使用顯示器的使用 者而言，有危害身體的疑慮，因此，現今市面上的顯示器漸漸將由液晶顯 示器（LiQuid Crystal Display，LCD)取代舊有的CRT顯示器。液晶顯示 器具有輕薄短小、低輻射與耗電量低等優點，也因此成為目前市場主流。 請參閱第一圖，其為習知液晶顯示器的方塊圖。如圖所示，習知液晶 顯示器包括一時序產生器10，、一垂直驅動電路2〇，以及一水平驅動電路 30 。時序產生器10係接收垂直同步訊號Vsync、水平同步訊號Hsync 以及主時脈訊號MCK作為輸入訊號，以產生兩組控制訊號以控制垂直驅動 電路20與水平驅動電路30，，使顯示區域45，依據垂直驅動電路2〇， φ 與水平驅動電路30’所傳送之訊號與資料顯示畫面。 上述兩組控制訊號分別為一垂直輸入時脈訊號vst、一垂直移位時脈訊 號VCK與一水平輸入時脈訊號HST、一水平移位時脈訊號HCK。垂直驅動電 路20’與水平驅動電路30’分別包括移位暫存器22，與移位暫存器 32’ 。垂直輸入時脈訊號VST係依據垂直同步訊號vsync所產生，並輸入 . 至垂直驅動電路20’之移位暫存_ 22，。移位暫存器22,依據垂直移位 時脈訊號vck依次產生複數個垂直選擇時脈訊號，以控制顯示區域45，顯 示畫面。水平驅動電路30，接收水平輸入時脈訊號HST並依據水平移位時 脈訊號HCK而產生取樣時脈訊號，以供水平驅動電路3〇，依據取樣時脈訊 號取樣一影像資料，以供顯示區域45，顯示畫面。 5 14，。第—，序f生器1〇，3包括一第-計數器12，與-第二計數器 _ 。十數器12用以計數時脈訊號之個數，當計數個數到達一門檻 批心—_數器12’ #會發送—時序控制訊號至水平驅動電路30’，以 j平驅動電路3〇,。例如，驅使水平驅動電路30,保持取樣影像資料 付之:樣資料’以傳送至一數位類比轉換器（圖未繪)轉換成一類比之 二訊'並輸出至顯示區域45，。同樣，第二計數器14，用以計數時脈 =之Γ數’料數個數到達—門雖時，第二計數器14，即會發送時序 工訊^至垂直媒動電路2〇’，以控制垂直驅動電路2〇，。 准若由於上述之方法須使用計數器’以產生時序控制訊號 ，如此在 電路上需要較多硬體電路而增加設計_度與側面積以及增加功率消 耗。 土於上述i)素’現今已提出如第—圖所示相關技術的改進方案，如令 華民國專利公告第535136號發明專利，其技術内容大致如下。如第二圖所 不’其與第—圖不同之處在於時序產生器1G，不需設置計數器，而可分別 藉由垂直驅動電路20,與水平驅動電路3〇，原有之移位暫存器怒與移位 暫存器32回傳一時序資料（timing data)至時序產生器1〇，。時序產 生器10雜時序資料產生時序控制峨並傳送至垂直驅動器2〇，與水平 驅動器30’ ，以控制垂直驅動器2〇,與水平驅動器3〇，。如此時序產生 器1〇,即可在不需設置計數器的情況下產生時序控制訊號。 惟若，在雙向掃描時，由於許多時序控制訊號必須在空白（blanking) 期間產生，若以典型的10%空白週期計算，對輸出的解析度是24〇χ32〇像素 之顯不器而言’如第三A圖所示，便需在水平驅動電路3Q，之移位暫存器 32之頭尾多加各約28級虛設(dummy)移位暫存器34’ ，以產生時序產生 器1〇所需之時序資料而產生時序控制訊號；垂直驅動電路2〇，之移位暫 存Is 22亦是如此。 此種方式將使垂直驅動電路20’與水平驅動電路3〇’之移位暫存器 22與移位暫存器32’所佔用之長度增加許多，而超出顯示面板肋，上 左右之長度，且增加功率消耗。現今對於顯示面板40，上下左右之架框的 寬度大小要求日益嚴格，如此設計方式不符合現今要求◊再者，如第三B 圖所示，若將28級虛設移位暫存器34,分別設置於顯示面板4〇，的其他 地方，便會使訊號傳遞發生延遲，如此容易發生問題，而無法順利進行雙 向掃描，造成雙向切換困難。 因此，本發明針對上述問題提出一種顯示裝置之時序控制電路及時序 控制方法，不僅可改善垂直驅動電路與水平驅動電路原有之移位暫存器之 級數過長、增加設計之複雜度與増加功率消耗之缺點，又可解決在進行雙 向掃描時的雙向切換困難的問題。 【發明内容】 本發明之一目的在於提供一種顯示裝置之時序控制電路及時序控制方 法，其藉由對應垂直驅動電路與水平驅動電路另外設置移位暫存器，以避 免垂直驅動電路與水平驅動電路原有之移位暫存器之級數過長，而增加設 計之複雜度，且可順利進行雙向掃描。 本發明之另一目的在於提供一種顯示裝置之時序控制電路及時序控制 方法，其藉由對應垂直驅動電路與水平驅動電路另外設置移位暫存器，而 使用低頻率之時脈訊號產生時序資料，以達降低消耗功率之目的。 本發明之顯示裝置之時序控制電路及時序控制方法，用於具有一水平 驅動電路之一顯示裝置，且水平驅動電路具有一第一水平移位暫存器。本 發明之時序控制電路包含一時序產生器與一第二水平移位暫存器。本發明 之控制方法係由時序產生器，接收一水平同步訊號以及—㈣脈訊號，產 生一水平輸入時脈訊號、一第一水平移位時哌訊號以及一第二水平移位時 脈訊號，水平輸入時脈訊號與第一水平移位時脈訊傳送至第一水平移位暫 存器，而產生一取樣時脈訊號，用於取樣一影像資料，以顯示影像於顯示 裝置之一顯示區域，此外亦傳送水平輸入時脈訊號與第二水平移位時脈訊 傳送至第二水平移位暫存器，而產生一時序資料並傳送至時序產生器，以 1343039 依據該時序資料，產生-時序控制城並傳送至水平购電路，以控制水 平驅動電路。 再者，本發明之顯示裝置之時序控制電路亦可用於控制顯示裝置之一 垂直驅動電路，且垂直㈣電路具有H直移位暫存^，此用於控制 垂直驅動f路之時序控織路·包含時序產生器並有—第二垂直移位暫 存器。本發明之時序控制方法係由時序產生器接收一垂直同步訊號以及主 時脈訊號，產生-垂直輸人時脈訊m直移位時脈訊號以及一第 二垂直移位時脈訊號；之後，傳送垂直輸入時脈訊號與第—垂直移位時脈 訊號至第一垂直移位暫存器，以產生複數選擇時脈訊號，用於控制顯示裝 置之-顯示區域ί此外，傳送垂j[輸人時脈峨與第二垂直移位時脈訊號 至第一垂直移位暫存器，以產生一時序資料並傳送至時序產生器，時序產 生器依據時序資料，產生一時序控制訊號並傳送垂直驅動電路，以控制垂 直驅動電路。 【實施方式】 請參閱第四圖，其為本發明之一較佳實施例之方塊圖。本發明之時序 產生裝置用於顯示裝置；如圖所示，顯示裝置1包含有一時序產生器1〇、 一水平驅動電路20、一垂直驅動電路30,而皆設置於一玻璃基板（圖未繪）， 即為顯示面板（圖未繪）。水平驅動電路20與垂直驅動電路3〇皆耗接顯示 面板之一顯示區域45。本發明之時序產生器10係接收外部裝置（例如電腦 系統）所供給之垂直同步訊號Vsync、水平同步訊號Hsync以及主時脈訊號 MCK，以產生垂直輸入時脈訊號VST、第一垂直移位時脈訊號vcKl、第二垂 直移位時脈訊號VCK2、水平輸入時脈訊號HST、第一水平移位時脈訊號HCK1 與弟二水平移位時脈訊號HCK2。時序產生器10依據水平同步訊號Hsync產 生水平輸入時脈訊號HST’並依據主時脈訊號MCK產生第一水平移位時脈訊 號HCK1與第二水平移位時脈訊號HCK2。時序產生器1〇亦依據垂直同步訊 號Vsync產生垂直輸入時脈訊號VST ’且依據主時脈訊號MCK產生第一垂直 8 移位時脈訊號VCK1與第二垂直移位時脈訊號vck2 另外，第二水平移位時脈訊號HCK2之頻率可小於鱗於第 時脈訊號腿之鮮。第二垂直移辦脈訊號體之解村小== 於第一垂直移位時脈之頻率VCK1。 、攻等 水平驅動電路20具有第-水平移位暫存器22。第一水平移位 22接收水平輸入時脈訊號HST鮮一水平移位時脈訊號mi。第 ^ 位暫存器22 _第-水平雜時脈峨騰賴水平.時脈訊號财 而產生-取樣雜職’聽取斜㈣置哺送之—影料料^本明 之時序控織路減於水平_桃2〇設置有第三水平移靖存器… 接收水平輸入時脈訊號HST與第二水平移位時脈訊號HCK2，並依據第二水 平移位時脈訊號腿移位水平輸入時脈訊號HST而產生一時序時脈訊 且依據時序時脈訊號傳送一時序資料至時序產生器1〇。時序產生器依據 時序資料，產生-時序控制訊號並傳送至水平驅動電路2G，以控制水平驅 動電路20。 _ 水平驅動電路20另包括-閃鎖模組26 «及-數位類比轉換電路28。 閂鎖模組26包括一取樣閂鎖電路260與一保持閂鎖電路26h取樣閂鎖電 路260依據第一水平移位暫存器22所產生之取樣時脈訊號取樣影像資料， 產生複數取樣資料。保持閃鎖電路262依據時序控制訊號’保持取樣閃鎖 電路260之該些取樣資料。數位類比轉換器28係將保持的取樣資料轉換為 類比顯示訊號，並傳送至顯示區域45之資料線（圖未繪），以顯示影像。 顯示裝置1之垂直驅動電路30具有一第一垂直移位暫存器32 ^第一 垂直移位暫存器32接收垂直輸入時脈訊號VST與第一垂直移位時脈訊號 VCK1。第一垂直移位暫存器32如同前述第一水平移位暫存器22，係依據第 —垂直移位時脈訊號VCKi延遲垂直輸入時脈訊號VST而產生一選擇時脈訊 號’用於選擇顯示區域45之垂直掃描線（圖未繪），即控制顯示區域45之 垂直掃描線（圖未繪）。此外，本發明之時序控制電路相對於垂直驅動電路 30設有一第二垂直移位暫存器34，其依據第二垂直移位時脈訊號VCK2，延 1343039 遲垂直輸入時脈訊號VST而產生一時序時脈訊號，並依據此時序時脈訊號 傳送一時序資料至時序產生器10,時序產生器10依據時序資料產生時序控 制訊號並傳送至垂直驅動電路3〇，以控制垂直驅動電路3〇。例如，在某一 期間進行局部顯示模式時，即可利用時序控制訊號控制垂直驅動電路3〇在 此某一期間進行局部顯示模式。 由於水平驅動電路2〇與垂直驅動電路30有多種不同設計方式，所以 用於控制水平驅動電路20與垂直鶴電路30之時雜制訊號並不只用於 上述之兩種情形’上述用於控制保持問鎖電路262與進行局部顯示模式僅1343039 * » IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a display device, particularly a timing control circuit for a display device and a 'timing control method'. m [Prior technology] • Today's technology is booming. The variety of information products has been updated to meet the different needs of the public. Most of the early displays were cathode ray tube (CRT) displays. Due to their large volume and large power consumption, the radiation generated was harmful to the user for long-term use of the display. Therefore, the display on the market today will gradually replace the old CRT display with a liquid crystal display (LCD). The liquid crystal display has the advantages of being thin and light, low in radiation, and low in power consumption, and thus has become the mainstream in the current market. Please refer to the first figure, which is a block diagram of a conventional liquid crystal display. As shown, the conventional liquid crystal display includes a timing generator 10, a vertical driving circuit 2A, and a horizontal driving circuit 30. The timing generator 10 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the main clock signal MCK as input signals to generate two sets of control signals to control the vertical driving circuit 20 and the horizontal driving circuit 30, so that the display area 45 is based on The vertical drive circuit 2〇, φ and the signal and data display screen transmitted by the horizontal drive circuit 30'. The two sets of control signals are a vertical input clock signal vst, a vertical shift clock signal VCK and a horizontal input clock signal HST, and a horizontal shift clock signal HCK. The vertical drive circuit 20' and the horizontal drive circuit 30' respectively include a shift register 22 and a shift register 32'. The vertical input clock signal VST is generated based on the vertical sync signal vsync and is input to the shift register _ 22 of the vertical drive circuit 20'. The shift register 22 sequentially generates a plurality of vertically selected clock signals according to the vertical shift clock signal vck to control the display area 45 to display a picture. The horizontal driving circuit 30 receives the horizontal input clock signal HST and generates a sampling clock signal according to the horizontal shift clock signal HCK for the horizontal driving circuit 3 to sample an image data according to the sampling clock signal for the display area. 45, display the screen. 5 14,. First, the sequencer 1〇, 3 includes a first-counter 12, and a second counter _. The decimator 12 is used to count the number of clock signals. When the number of counts reaches a threshold, the _number 12' will send a timing control signal to the horizontal drive circuit 30' to drive the circuit 3 ,. For example, the horizontal driving circuit 30 is driven to hold the sampled image data and the sample data is transferred to a digital analog converter (not shown) to be converted into an analogy and output to the display area 45. Similarly, the second counter 14 is used to count the number of turns of the clock = the number of the number of arrivals - the gate, although the second counter 14, will send the timing signal to the vertical medium circuit 2 〇 ' to control Vertical drive circuit 2〇. If the counter is used to generate timing control signals due to the above method, more hardware circuits are required on the circuit to increase the design_degree and side area and increase power consumption. The above-mentioned i) prime has now proposed an improvement of the related art as shown in the first figure, such as the invention patent of the Chinese Patent Publication No. 535136, the technical contents of which are roughly as follows. As shown in the second figure, it differs from the first figure in that the timing generator 1G does not need to set a counter, but can be temporarily shifted by the vertical driving circuit 20 and the horizontal driving circuit 3, respectively. The anger and shift register 32 returns a timing data to the timing generator 1 . The timing generator 10 generates timing control and transmits it to the vertical driver 2'', and the horizontal driver 30' to control the vertical driver 2'' and the horizontal driver's 3''. With this timing generator, the timing control signal can be generated without setting a counter. However, in the case of bidirectional scanning, since many timing control signals must be generated during blanking, if the calculation is performed with a typical 10% blank period, the resolution of the output is 24 〇χ 32 〇 pixels. As shown in FIG. 3A, about 28 stages of dummy shift register 34' are added to the horizontal drive circuit 3Q, and the shift register 32 is added to the head of the shift register 32 to generate the timing generator 1〇. The timing information is generated by the required timing data; the vertical drive circuit 2 is also the same as the shift register Is 22 . In this way, the length occupied by the vertical drive circuit 20' and the horizontal drive circuit 3''s shift register 22 and the shift register 32' is increased a lot, beyond the length of the display panel ribs, up and down, And increase power consumption. Nowadays, for the display panel 40, the width of the frame of the upper, lower, left and right frames is increasingly strict, and the design method does not meet the requirements of today. Furthermore, as shown in the third B, if the 28-level dummy shift register 34, respectively When it is placed in the other part of the display panel 4, the signal transmission is delayed, which is easy to cause problems, and the two-way scanning cannot be performed smoothly, which makes the two-way switching difficult. Therefore, the present invention provides a timing control circuit and a timing control method for a display device according to the above problems, which can not only improve the length of the original shift register of the vertical drive circuit and the horizontal drive circuit, but also increase the complexity of the design and The disadvantage of increasing power consumption can solve the problem of two-way switching when performing bidirectional scanning. SUMMARY OF THE INVENTION An object of the present invention is to provide a timing control circuit and a timing control method for a display device, which are additionally provided with a shift register by a corresponding vertical driving circuit and a horizontal driving circuit to avoid vertical driving circuit and horizontal driving. The original shift register of the circuit is too long, which increases the complexity of the design and can perform two-way scanning smoothly. Another object of the present invention is to provide a timing control circuit and a timing control method for a display device, which use a low frequency clock signal to generate timing data by additionally providing a shift register corresponding to the vertical driving circuit and the horizontal driving circuit. In order to reduce the power consumption. The timing control circuit and the timing control method of the display device of the present invention are used for a display device having a horizontal driving circuit, and the horizontal driving circuit has a first horizontal shift register. The timing control circuit of the present invention includes a timing generator and a second horizontal shift register. The control method of the present invention is a timing generator that receives a horizontal sync signal and a - (four) pulse signal to generate a horizontal input clock signal, a first horizontal shift clock signal, and a second horizontal shift clock signal. The horizontal input clock signal and the first horizontal shift pulse are transmitted to the first horizontal shift register, and a sampling clock signal is generated for sampling an image data to display the image in one display area of the display device. In addition, the horizontal input clock signal and the second horizontal shift pulse are transmitted to the second horizontal shift register, and a time series data is generated and transmitted to the timing generator, according to the timing data, 1343039 generates - The timing control is transmitted to the horizontal purchase circuit to control the horizontal drive circuit. Furthermore, the timing control circuit of the display device of the present invention can also be used to control one of the vertical driving circuits of the display device, and the vertical (four) circuit has a H-shift temporary storage, which is used to control the timing control of the vertical driving f-path • Contains a timing generator and has a second vertical shift register. The timing control method of the present invention receives a vertical sync signal and a main clock signal from the timing generator, generates a vertical shift pulse signal and a second vertical shift clock signal in a vertical input mode; Transmitting the vertical input clock signal and the first-vertically shifting the clock signal to the first vertical shift register to generate a plurality of selected clock signals for controlling the display device - the display area ί The human clock and the second vertical shift clock signal to the first vertical shift register to generate a timing data and transmitted to the timing generator, the timing generator generates a timing control signal according to the timing data and transmits the vertical A drive circuit to control the vertical drive circuit. [Embodiment] Please refer to the fourth figure, which is a block diagram of a preferred embodiment of the present invention. The timing generating device of the present invention is used for a display device; as shown, the display device 1 includes a timing generator 1A, a horizontal driving circuit 20, and a vertical driving circuit 30, all of which are disposed on a glass substrate (not shown) ), that is, the display panel (not shown). Both the horizontal drive circuit 20 and the vertical drive circuit 3 are consuming one display area 45 of the display panel. The timing generator 10 of the present invention receives the vertical sync signal Vsync, the horizontal sync signal Hsync and the main clock signal MCK supplied by an external device (for example, a computer system) to generate a vertical input clock signal VST and a first vertical shift. The pulse signal vcKl, the second vertical shift clock signal VCK2, the horizontal input clock signal HST, the first horizontal shift clock signal HCK1 and the second horizontal shift clock signal HCK2. The timing generator 10 generates a horizontal input clock signal HST' according to the horizontal synchronization signal Hsync and generates a first horizontal shift clock signal HCK1 and a second horizontal shift clock signal HCK2 according to the main clock signal MCK. The timing generator 1〇 also generates a vertical input clock signal VST′ according to the vertical synchronization signal Vsync and generates a first vertical 8 shift clock signal VCK1 and a second vertical shift clock signal vck2 according to the main clock signal MCK. The frequency of the two horizontal shifting clock signal HCK2 may be less than the scale of the first clock signal leg. The second vertical shifting pulse signal body solution village == the frequency VCK1 of the first vertical shift clock. The horizontal drive circuit 20 has a first-horizontal shift register 22. The first horizontal shift 22 receives the horizontal input clock signal HST freshly horizontally shifting the clock signal mi. The first bit register 22 _ first-level miscellaneous clock 峨 赖 . level. Clock signal generated - sampling miscellaneous 'listening oblique (four) feeding to send - shadow material ^ Ben Ming's timing control weaving road minus The horizontal _ peach 2 〇 is provided with a third horizontal shift register... receiving the horizontal input clock signal HST and the second horizontal shift clock signal HCK2, and according to the second horizontal shift clock signal leg shift level input clock The signal HST generates a timing time pulse and transmits a timing data to the timing generator 1 according to the timing clock signal. The timing generator generates a timing control signal based on the timing data and transmits it to the horizontal driving circuit 2G to control the horizontal driving circuit 20. The horizontal drive circuit 20 further includes a - flash lock module 26 « and - digital analog conversion circuit 28. The latch module 26 includes a sample latch circuit 260 and a hold latch circuit 26h. The sample latch circuit 260 generates sampled sample data according to the sampled clock signal sample data generated by the first horizontal shift register 22. The hold flash lock circuit 262 holds the sample data of the sample flash lock circuit 260 in accordance with the timing control signal '. The digital analog converter 28 converts the held sample data into an analog display signal and transmits it to the data line of the display area 45 (not shown) to display the image. The vertical drive circuit 30 of the display device 1 has a first vertical shift register 32. The first vertical shift register 32 receives the vertical input clock signal VST and the first vertical shift clock signal VCK1. The first vertical shift register 32 is like the first horizontal shift register 22, and generates a selective clock signal 'selected according to the first vertical shift clock signal VCKi delaying the vertical input clock signal VST. A vertical scan line (not shown) of the display area 45, that is, a vertical scan line (not shown) that controls the display area 45. In addition, the timing control circuit of the present invention is provided with a second vertical shift register 34 for generating a temporary time according to the second vertical shift clock signal VCK2, delaying the vertical input clock signal VST according to the second vertical shift clock signal VCK2. The clock signal is sequenced, and a timing data is transmitted to the timing generator 10 according to the timing clock signal. The timing generator 10 generates a timing control signal according to the timing data and transmits the timing control signal to the vertical driving circuit 3 to control the vertical driving circuit 3〇. For example, when the partial display mode is performed in a certain period, the vertical drive circuit 3 can be controlled by the timing control signal to perform the partial display mode for a certain period of time. Since the horizontal driving circuit 2 and the vertical driving circuit 30 have different design manners, the time for controlling the horizontal driving circuit 20 and the vertical crane circuit 30 is not only used in the above two cases. Asking the lock circuit 262 and performing the partial display mode only
為本發明之《%實制。本剌之時雜綱餅依據斜驅純路洲與垂 直驅動電路30之設計方式所需而用於不同情形，而本發明之第二水平移位 暫存器24料二垂直雜暫钟34卿絲時序纽· 1()㈣序資料即 依據時序控制訊號之時相騎職之時序資料，以供時序I生^⑺產生 時序控制訊號。 ' 由上述可知，本發明之時序控制電路藉由第二水平移位暫存器以或是 第二垂直移位暫存H 34產生時序控制訊號，即不需如第圖與第三” 所不習知水平驅動電路或是垂直㈣電路之虛設移位暫存如傳時序資 料’而產生時序控制訊號，此，水平驅動· 2G或是垂直驅動電路3〇It is the "% system" of the present invention. The present invention is used in different situations according to the design of the oblique drive pure road continent and the vertical drive circuit 30, and the second horizontal shift register of the present invention is a second vertical miscellaneous clock. The silk timing New 1 () (four) sequence data is based on the timing data of the time phase riding signal of the timing control signal, for the timing I generation ^ (7) to generate the timing control signal. As can be seen from the above, the timing control circuit of the present invention generates a timing control signal by using the second horizontal shift register or the second vertical shift register H 34, that is, no need to be as shown in the figure and the third The conventional horizontal driving circuit or the vertical (four) circuit of the dummy shift temporary storage, such as the transmission timing data, generates a timing control signal, and thus, the horizontal driving · 2G or the vertical driving circuit 3
之第-水平移位暫存ϋ 24與第—垂直移位暫存器34的長度將不會超出顯 不面板的上下左右之長度，亦不會發生訊號傳輸延遲的問題，故可提 示器之顯示效能。 ” 請參閱第五圖，其為本發明與習知之時序時脈訊號之時序圖。由於習 知技術係在水平驅動電路與垂直驅動電路之原有移位暫存器多設置 位暫存器，如此虛郷位暫存騎產生之時料脈訊號之週誠狀水平 触直驅動電路之原有移位暫存器所產生之時脈峨，所以虛設 移位暫存ϋ之級數會較高’而個面積且增加功率消耗。 U43039 序產生器10,供時序產生器10依據時序資料產生所需要之時序控制訊號。 然而，本發明增設之移位暫存器所產生之時序時脈訊號的週期不需和原有 移位暫存n所產生之雜峨的聊—樣，所以本發明增設之移位暫存器 之級數在小㈣賴設移㈣存H的情訂，就可產靖需之時序控制訊 唬。如圖所示，本發明增設之移位暫存器只需4級，即可在時間T1產生高 準位之時序控制訊號。由於本發明增設之時序時脈訊號之頻率小於習知虛 2移位暫存器之時序時脈訊號的鮮，即可產生時序控制訊號如此移位The length of the first-horizontal shift register ϋ 24 and the first-vertical shift register 34 will not exceed the length of the upper, lower, left and right of the panel, and the signal transmission delay will not occur, so the prompter can be Display performance. Please refer to the fifth figure, which is a timing diagram of the timing clock signal of the present invention and the conventional one. Since the prior art is to set a bit register in the original shift register of the horizontal driving circuit and the vertical driving circuit, When the virtual position is temporarily stored, the Zhou Cheng-like horizontal touch-pull drive circuit generates the clock pulse generated by the original shift register, so the number of dummy shift temporary storage will be higher. The area is increased by the power consumption. The U43039 sequence generator 10 is used by the timing generator 10 to generate the required timing control signals according to the timing data. However, the timing pulse signal generated by the shift register provided by the present invention is The cycle does not need to be chatted with the original shifting temporary n, so the number of stages of the shift register added by the present invention can be produced in the case of a small (four) shift (four) deposit H. As shown in the figure, the shift register provided by the present invention only needs 4 stages, and can generate a high-level timing control signal at time T1. The timing pulse signal added by the present invention is added. The frequency is less than the timing of the conventional virtual 2 shift register Fresh signals, timing control signals can be generated so displaced
^存器之級數可大幅減低進崎低辨，且可改善因移位暫存器之級數過 長而影響顯示面板之設計面積Q 此外，本發明之顯示裝置！的時序控制電路所產生之時序控制訊號並 不揭限於使用在水平驅動電路2Q及垂直驅動電路3Q，亦可顧於其他電 .如第六圖所示’其為本發明之另一較佳實施例之方塊圖。在全整合⑽ integrat咖)的顯示面板中，通常包含有一電顯換電路5〇。電壓轉換電 路50粞接有-參考電壓、—共同電顯—介面（㈣伽& ι/ρ)，以轉 換外部輸入的-個直流電壓而輸出較高之正電壓或負電壓，例如將一個抓 電廢轉換成6V電壓及—3V電壓以供其他電路使用。然而，接收此電麼之立 =路iM卜直在動作，為了節省神，可在其他電路未動作綱將電壓 ^電路50暫時關閉。本發明之第二水平移位暫存器24或第二垂直移位 34可提供時脈訊號至電塵轉換電路5〇作為時序控制訊號，而控制 電壓轉換電路50 ’並改變時序控制峨電壓準位後將時序控制訊號輸出至 2平驅動電路20 ’以控制水平驅動電路2()。此外，亦可由第二水平移位暫 ^器24或第二垂直移靖姑34提供時序諸至轉產生^ iq，而對應 產生序控制訊號並傳送至電_換電路5Q，以控制電壓轉換電路5〇。 4上所述，本發明之顯示裝置之時序控制電路包含時序產生器以及第 存ϋ與第二垂直移位暫存器。本發明之時序控制方法藉由時 序^器產生水平輸入時脈訊號以及第二水平移位時脈訊號。第二水平移 位暫存減據水平輸人時脈峨與第二水平移位時脈訊號，產生時序資料 1343039 f傳送至時序產生[時序產生雜據時序麟，產生時序控做號 送水平驅動電路以控制水平㈣電路。第二垂直移位暫存器同樣依據時序 產生器所產生之垂直輸人時脈訊號以及第二垂直移位時脈訊號，而產 序資料供時序產生驗斜序資料，產生時序控制訊號並傳送至垂直驅動 電路，以控繼直驅動電路，如此可降低功率雜，且可順利進行雙向掃 描。 以上所述僅為本發明之雌實施例，並細総定本發衝涵蓋之範 圍，舉凡依本發明所述之形狀、構造及/或特徵所為之均等變化與修飾， 均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 第一圖為習知液晶顯示器之方塊圖； 第二圖為另一習知液晶顯示器之方塊圖； 第二A圖為習知移位暫存器設置於顯示面板之位置示意圖； 第三8圖為習知移位暫存器設置於顯示面板之另—位置示意圖； 第四圖為本發明之一較佳實施例之方塊圖； 第五圖為本發明與習知之時序時脈訊號之時序圖 ;以及 第六圖為本發明之另一較佳實施例之方塊圖。 【主要元件符號說明】 1 顯示裝置 10, 時序產生器 12’ 第一計數器 i4’ 第二計數器 20’ 垂直驅動電路 22, 移位暫存器 30, 水平驅動電路 12 1343039 32’移位暫存器 34’虛設移位暫存器 40 顯示面板 45 顯示區域 10 時序產生器 20 水平驅動電路 22 第一水平移位暫存器 24 第二水平移位暫存器 26 閃鎖模組 260取樣問鎖電路 262保持閂鎖電路 28 數位類比轉換器 30 垂直驅動電路 32 第一垂直移位暫存器 34 第二垂直移位暫存器 45 顯示區域 50 電壓轉換電路The number of stages of the memory can be greatly reduced, and the design area of the display panel can be improved due to the excessive number of stages of the shift register. Furthermore, the display device of the present invention! The timing control signal generated by the timing control circuit is not limited to use in the horizontal driving circuit 2Q and the vertical driving circuit 3Q, and may also be used in other electric power. As shown in the sixth figure, it is another preferred embodiment of the present invention. Example block diagram. In a fully integrated (10) integrated display panel, an electrical display circuit 5 is typically included. The voltage conversion circuit 50 is connected with a - reference voltage, a common electrical display - interface ((4) gamma & ι / ρ) to convert an externally input - DC voltage and output a higher positive or negative voltage, for example, a The electric waste is converted into 6V voltage and -3V voltage for use in other circuits. However, if you receive this power, the path iM is in motion, and in order to save God, the voltage ^ circuit 50 can be temporarily turned off in other circuits. The second horizontal shift register 24 or the second vertical shift 34 of the present invention can provide the clock signal to the electric dust conversion circuit 5 as a timing control signal, and control the voltage conversion circuit 50' and change the timing control voltage level. The bit timing control signal is output to the 2-flat drive circuit 20' to control the horizontal drive circuit 2(). In addition, the second horizontal shifting device 24 or the second vertical shifting device 34 may also provide timing conversion to generate iq, and correspondingly generate the sequence control signal and transmit to the power-switching circuit 5Q to control the voltage conversion circuit. 5〇. As described above, the timing control circuit of the display device of the present invention includes a timing generator and a first and second vertical shift register. The timing control method of the present invention generates a horizontal input clock signal and a second horizontal shift clock signal by a sequencer. The second horizontal shift temporary storage subtraction level input clock pulse and the second horizontal shift clock signal generate timing data 1343039 f is transmitted to the timing generation [timing generation noise timing Lin, generating timing control number to send horizontal drive The circuit is controlled by a level (four) circuit. The second vertical shift register is also based on the vertical input clock signal generated by the timing generator and the second vertical shift clock signal, and the sequence data is used for timing generation of the oblique sequence data, generating the timing control signal and transmitting To the vertical drive circuit to control the direct drive circuit, which can reduce power miscellaneous and smoothly perform bidirectional scanning. The above description is only for the female embodiment of the present invention, and the scope and the features of the present invention are included in the scope of the present invention. Within the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a block diagram of a conventional liquid crystal display; the second figure is a block diagram of another conventional liquid crystal display; the second A is a position where the conventional shift register is disposed on the display panel 3 is a block diagram of a conventional shift register placed on a display panel; the fourth diagram is a block diagram of a preferred embodiment of the present invention; A timing diagram of a clock signal; and a sixth diagram is a block diagram of another preferred embodiment of the present invention. [Main component symbol description] 1 Display device 10, timing generator 12' First counter i4' Second counter 20' Vertical drive circuit 22, shift register 30, horizontal drive circuit 12 1343039 32' shift register 34' dummy shift register 40 display panel 45 display area 10 timing generator 20 horizontal drive circuit 22 first horizontal shift register 24 second horizontal shift register 26 flash lock module 260 sample lock circuit 262 hold latch circuit 28 digital analog converter 30 vertical drive circuit 32 first vertical shift register 34 second vertical shift register 45 display area 50 voltage conversion circuit