200834508 九、發明說明： • 【發明所屬之技術領域】 , 本發明係有關於一種顯示裝置，其係尤指顯示裝置之時序控制電路及 時序控制方法。 ' 【先前技術】 ^ 現今科技蓬勃發展，資訊商品種類推陳出新，滿足了大眾不同的需求。 早期顯示器多半為陰極射線管（Cathode Ray Tube，C^T)顯示器，由於其 φ 體積龐大與耗電量大，而且所產生的輻射線對於長時間使用顯示器的使用 者而言，有危害身體的疑慮，因此，現今市面上的顯示器漸漸將由液晶顯 丨示器（Liquid Crystal Display，LCD)取代舊有的CRT顯示器。液晶顯示 器具有輕薄短小、低輻射與耗電量低等優點，也因此成為目前市場主流。 ! 請參閱第一圖，其為習知液晶顯示器的方塊圖。如圖所示，習知液晶 顯示器包括一時序產生器10’ 、一垂直驅動電路20，以及一水平驅動電路 30’ 。時序產生器10’係接收垂直同步訊號Vsync、水平同步訊號Hsync 以及主時脈訊號MCK作為輸入訊號，以產生兩組控制訊號以控制垂直驅動 | · ' 電路20’與水平驅動電路30，，使顯示區域45’依據垂直驅動電路20， 0 與水平驅動電路30’所傳送之訊號與資料顯示畫面。 上述兩組控制訊號分別為一垂直輸入時脈訊號VST、一垂直移位時脈訊 ： 號VCK與一水平輸入時脈訊號HST、一水平移位時脈訊號HCK。垂直驅動電 路20’與水平驅動電路30’分別包括移位暫存器22’與移位暫存器 32 。垂直輸入時脈訊號VST係依據垂直同步訊號Vsync所產生，並輸入 ; 至垂直驅動電路20’之移位暫存器22，。移位暫存器22’依據垂直移位 i 時脈訊號vc【依次產生複數個垂直選擇時脈訊號，以控制顯示區域45，顯 示畫面。水平驅動電路30’接收水平輸入時脈訊號HST並依據水平移位時 脈訊號HCK而產生取樣時脈訊號，以供水平驅動電路3〇，依據取樣時脈訊 號取樣一影像資料，以供顯示區域45，顯示晝面。 200834508 14,再產生器1〇,另包括一第一計數器12,與一第二計數器 斤》十數器12肋計數時脈訊號之個數，當計數個數到達 值時’第-计數器12’即會發送一時序控制訊號至水平驅動電路加，，^ 控^水平鶴電路3G，。例如，驅使斜鶴電路3G，保持取樣影像資料 :斤传之取樣資料’以傳送至—數位類比轉換器（圖未繪）轉換成—類比之 ‘知峨，並輸丨至_輯45，。囉，第坤數㈣，㈣ 訊號之個數，當計數個數猶值時，第三計數器14，即會時1 控制訊號至垂直驅動電路2〇，，以控繼直驅動電路2{)、x、 φ惟若，由於上述之方法須使用計數It，以產生時序控制訊號，如此在 :路上需要财硬體電路而增純計複雜度與侧面積崎增加功率 基於上義素，現今已提出如第—騎示細技術敝進方案，如中 華民國專利公告第535136號發明專利，其技術内容大致如下。如第二圖所 =，其與第-圖不同之處在於時序產生㈣，不f設置計數器，而可:別 2垂直驅動電路20,與水平驅動電路30，原有之移位暫存器22,與移位 暫存器，32,畴一時序資料（timing data)至時序產生110，。時序產 生器爪依據時序資料產生時序控制訊號並傳送至垂直驅動器2〇，與水平 驅動器3〇’ ，以控制垂直驅動器20,與水平驅動器30，。如此，時^產生 器10即可在不需設置計數器的情況下產生時序控制訊號。 至惟右，在雙向掃描時，由於許多時序控制訊號必須在空白（blanking) 期間產生，若以典型的空白週期計算，對輸出的解析度是240x320像素， ^顯不器而言，如第三A圖所示，便需在水平驅動電路3〇，之移位暫存器 '之頭尾多加各約28級虛設(dummy)移位暫存器34,，以產生時序產生 器1〇所需之時序資料而產生時序控制訊號；垂直驅動電路20，之移位暫 存器22’亦是如此。 ,此種方式將使垂直驅動電路20，與水平驅動電路30，之移位暫存器 -、移位暫存器32所佔用之長度增加許多，而超出顯示面板仙，上下 200834508 左右之長度’且增加功率雜。現今對於顯示面板4G，上下左右之 寬度大小要求日盈嚴格’如此設計方式不符合現今要求。再者，如第'三^ 圖所不’若將28級虛設移位暫存器34，分別設置於顯示面板仙 地方，便會使職傳遞發生延遲’如此料發生問 ς 向掃描，絲城_。 ”、、而_進仃雙 因此，本發明針對上述問題提出一種顯示裝置之時序控制電路及時 控制方法，不僅微善垂直鶴電路與水平骑電路原有之輸暫存器之200834508 IX. Description of the Invention: • The technical field to which the invention pertains relates to a display device, which is particularly a timing control circuit and a timing control method for a display device. '[Previous technology] ^ Today's technology is booming, and the variety of information products is new and meets the different needs of the public. Most of the early displays were cathode ray tube (C^T) displays, which were cumbersome and consume large amounts of electricity, and the radiation generated was harmful to the user who used the display for a long time. Concerns, therefore, the display on the market today will gradually replace the old CRT display with a liquid crystal display (LCD). The liquid crystal display has the advantages of being thin and light, low in radiation, and low in power consumption, and thus has become the mainstream in the current market. Please refer to the first figure, which is a block diagram of a conventional liquid crystal display. As shown, the conventional liquid crystal display includes a timing generator 10', a vertical driving circuit 20, and a horizontal driving circuit 30'. The timing generator 10' receives the vertical sync signal Vsync, the horizontal sync signal Hsync, and the main clock signal MCK as input signals to generate two sets of control signals to control the vertical drive, the 'circuit 20' and the horizontal drive circuit 30, so that The display area 45' is based on the signal and data display screen transmitted by the vertical drive circuit 20, 0 and the horizontal drive circuit 30'. The two sets of control signals are a vertical input clock signal VST, a vertical shift pulse signal: a number VCK and a horizontal input clock signal HST, and a horizontal shift clock signal HCK. The vertical drive circuit 20' and the horizontal drive circuit 30' respectively include a shift register 22' and a shift register 32. The vertical input clock signal VST is generated based on the vertical sync signal Vsync and input to the shift register 22 of the vertical drive circuit 20'. The shift register 22' sequentially generates a plurality of vertically selected clock signals according to the vertical shift i clock signal vc to control the display area 45 to display a picture. The horizontal driving circuit 30' receives the horizontal input clock signal HST and generates a sampling clock signal according to the horizontal shift clock signal HCK for the horizontal driving circuit 3 to sample an image data according to the sampling clock signal for the display area. 45, showing the face. 200834508 14, the regenerator 1 〇, further includes a first counter 12, and a second counter tens of 12 ribs count the number of clock signals, when the number of counts reaches the value of the 'first counter 12' will send a timing control signal to the horizontal drive circuit plus, ^ control level horizontal crane circuit 3G. For example, the slanting crane circuit 3G is driven to keep the sampled image data: the sampled data transmitted by the jin is converted into an analogy to the analog-to-digital analog converter (not shown), and is transmitted to _ series 45.啰, 坤 (4), (4) The number of signals, when the number of counts is still, the third counter 14, that is, 1 control signal to the vertical drive circuit 2〇, to control the direct drive circuit 2{), x, φ, if, because the above method must use the count It to generate the timing control signal, so on the road: the need for financial hardware circuit and the increase of the complexity of the meter and the side area of the increase in power based on the upper element, has been proposed For example, the first-party riding technology-introducing scheme, such as the invention patent of the Republic of China Patent Bulletin No. 535136, is substantially as follows. As shown in the second figure, it differs from the first picture in that the timing is generated (four), and the counter is not set, but the second vertical driving circuit 20, the horizontal driving circuit 30, and the original shift register 22 can be used. And shift register, 32, domain-timing data to timing generation 110. The timing generator jaw generates timing control signals based on the timing data and transmits them to the vertical driver 2'', and the horizontal driver 3'' to control the vertical driver 20 and the horizontal driver 30. In this way, the time generator 10 can generate a timing control signal without setting a counter. To the right, in the two-way scanning, since many timing control signals must be generated during blanking, if the calculation is performed in a typical blank period, the resolution of the output is 240x320 pixels, and the third is the third. In the figure A, it is necessary to add about 28 stages of dummy shift registers 34 to the head of the horizontal drive circuit 3, shift register, to generate the timing generator 1 The timing information is generated by the timing data; the vertical drive circuit 20, the shift register 22' is also the same. In this way, the length of the vertical drive circuit 20, the horizontal drive circuit 30, the shift register, and the shift register 32 is increased a lot, and the display panel is beyond the length of the display panel, and the length of the upper and lower 200834508' And increase power miscellaneous. Nowadays, for the display panel 4G, the width of the upper and lower left and right sides is required to be strict. This design method does not meet the requirements of today. Furthermore, if the 'three-figure map does not', if the 28-level dummy shift register 34 is set in the display panel fairy place, the job transfer will be delayed. _. Therefore, the present invention provides a timing control circuit timely control method for a display device in view of the above problems, and not only the micro-good vertical crane circuit and the horizontal riding circuit original transmission register
級數過長、增純計之複雜與增加辨雜之缺點，又可軸在進行雜 向掃描時的雙向切換困難的問題。 、又 【發明内容】 、本發明之-目的在於提供-麵稀置之時序㈣電路及時序控制方 法，其藉由對應垂直驅動電路與水平驅動電路另外設置移位暫存器，以避 免垂直驅動電路與水平驅動電路原有之移位暫存器之級數過長，㈣加設 計之複雜度，且可順利進行雙向掃描。曰 、本發，之另-目的在於提供—種顯示裝置之時序控制電路及時序控制 方法，其藉由騎ϋ鶴電路與水平鶴電路另外設置移位暫存器，而 使用低頻率之雜峨產生時序倾，以達降低雜功率之目的。 本發明之顯示裝置之_控制電路及時序㈣方法，胁具有一水平 驅動電路《顯示裝置，且水平驅動電路具有—第—水平移位暫存器。本 發明之時序控魏路包含-時序產生難_第二水平移位暫翻。本發明 之控制方法係鱗序產生H，接收_水平同步訊纽及—主時脈訊號，產 生一水平輸人時脈峨、_第—水平雜時脈峨以及—第二水平移位時 脈訊號，水平輸入時脈訊號與第一水平移位時脈訊傳送至第一水平移位暫 存器，而產生-取樣時脈訊號，麟取樣—影像資料，以顯示影像於顯示 裝，之二齡區域，此外亦傳送水平輸人時脈域鄕二水平移位時脈訊 傳达至第二水平移位暫存器，喊生_時序將並傳送至時序產生器，以 200834508 ^資料’產生—時序控制訊號並傳送至水平驅動電路，以控制水 垂直驅動電路不裝置之時序控制電轉可胁控綱示裝置之-垂直驅動電路之時動電路具有—第—垂直移位暫存器，此用於控制 存器。本發明之=rm麵樣包含時序產生器並有—第二《移位暫 時脈訊號，產生方，由時序產生器接收—垂直同步訊號以及主 二垂直移辦脈峨；峨、H直移辦脈魏以及一第 訊號至第一垂直二塹在：达垂直輸入時脈訊號與第-垂直移位時脈 至第二垂直移位暫存器，：一=:;==直_訊號 生器依櫨眸庄次刺. 生呀序貝科並傳送至時序產生器，時序產 直驅動電路。f 生—時序控舰餘傳送垂細動電路，以控制垂 【實施方式】 明乡閱第四圖’其為本發日月之一較佳實施例之方塊圖。本發明之時序 一生裝置用於顯示裝置；如圖所示，顯示裝置丨包含有—時序產生器10、 •—水平驅動電路20、一垂直驅動電路30,而皆設置於-玻璃基板（圖未繪）， P為顯示面板(圖未繪）。水平驅動電路20與垂直驅動電路3〇賴接顯示 s板之-顯示區域45。本發明之時序產生關係接收外部裝置（例如電腦 系統）所供給之垂直同步訊號Vsync、水平同步峨Hsync以及主時脈訊號 «，以產生垂直輸入時脈訊號縱、第一垂直移位時脈訊號腿、第二垂 直移位時脈訊號VCK2、水平輸入時脈訊號HST、第-水平移位時脈訊號腿 與第二水平移位時脈訊號HCK2。時序產生器1 〇依據水平同步訊號Hsync產 生水平輸入時脈訊號HST，並依據主時脈訊號MCK產生第一水平移位時脈訊 號HCK1與第二水平移位時脈訊號HCK2。時序產生器1〇亦依據垂直同步訊 號Vsync產生垂直輸入時脈訊號VST，且依據主時脈訊號MCK產生第一垂直 200834508 移位時脈訊號VCK1與第二垂直移位時脈訊號VCK2。 1 ’帛二水平練義域聰之鮮可小域雜帛-水平移位 M1之鮮。第二垂直移位時脈訊號咖之鮮亦可小於或等 於弟一垂直移位時脈之頻率VQQ。 22接具有第一水平移位暫存器22。第一水平移位暫存器 22接收斜輸人輕職鄕—水平移辦脈峨_。第一水 22_f-水平餘報峨™稍斜輸人時脈訊號HST，The problem that the number of stages is too long, the complexity of the purening meter is increased, and the disadvantage of increasing the number of miscellaneous, and the two-way switching of the axis during the miscellaneous scanning is difficult. Further, the present invention aims to provide a timing (4) circuit and a timing control method for thin-faced thinning, which additionally provides a shift register by corresponding vertical driving circuit and horizontal driving circuit to avoid vertical driving. The number of stages of the original shift register of the circuit and the horizontal drive circuit is too long, (4) the complexity of the design is added, and the two-way scan can be smoothly performed.曰, 本发,其其他- The purpose is to provide a timing control circuit and a timing control method for a display device, which use a low frequency chimney by additionally setting a shift register by riding a crane circuit and a horizontal crane circuit. Timing is generated to reduce the power of the hybrid. The control circuit and the timing (4) method of the display device of the present invention have a horizontal driving circuit "display device, and the horizontal driving circuit has a - horizontal shift register. The timing control of the present invention includes - the timing generation is difficult - the second horizontal shift is temporarily turned over. The control method of the present invention generates H in a scale, receives a horizontal sync signal and a main clock signal, and generates a horizontal input clock, a _th-horizontal clock, and a second horizontal shift clock. a signal, a horizontal input clock signal and a first horizontal shift pulse are transmitted to the first horizontal shift register, and a -sample clock signal, a sampling image data is displayed to display the image in the display device, and the second The age area, in addition, also transmits the horizontal input time domain 鄕 two horizontal shifts when the pulse is transmitted to the second horizontal shift register, and the _ timing is transmitted to the timing generator to generate the data of 200834508 - the timing control signal is transmitted to the horizontal driving circuit to control the timing control of the water vertical driving circuit without the device. The timing circuit of the vertical driving circuit has a -first vertical shift register, Used to control the register. The =rm surface of the present invention includes a timing generator and has - a second "shift temporary pulse signal, a generating side, which is received by the timing generator - a vertical synchronization signal and a main two vertical shifting pulse; The pulse Wei and a first signal to the first vertical two-way are: the vertical input clock signal and the first-vertical shift clock to the second vertical shift register, one::;== straight_signal generator According to the 次 次 次 . . 生 生 生 生 生 生 生 生 生 生 生 生 生 生 生 生 生 生. f--Sequence-controlled ship-to-ship transmission fine-motion circuit to control vertical [Embodiment] The fourth picture of Mingxiang is a block diagram of a preferred embodiment of the present day and month. The timing lifetime device of the present invention is used for a display device; as shown, the display device 丨 includes a timing generator 10, a horizontal driving circuit 20, and a vertical driving circuit 30, all of which are disposed on a glass substrate (not shown) Painted), P is the display panel (not shown). The horizontal drive circuit 20 and the vertical drive circuit 3 are connected to display the display area 45 of the s-board. The timing generation relationship of the present invention receives a vertical sync signal Vsync, a horizontal sync 峨Hsync, and a main clock signal « supplied by an external device (for example, a computer system) to generate a vertical input clock signal vertical and a first vertical shift clock signal. The leg, the second vertical shift clock signal VCK2, the horizontal input clock signal HST, the first-level shift clock signal leg and the second horizontal shift clock signal HCK2. The timing generator 1 generates a horizontal input clock signal HST according to the horizontal synchronization signal Hsync, and generates a first horizontal shift clock signal HCK1 and a second horizontal shift clock signal HCK2 according to the main clock signal MCK. The timing generator 1 also generates a vertical input clock signal VST according to the vertical synchronization signal Vsync, and generates a first vertical 200834508 shift clock signal VCK1 and a second vertical shift clock signal VCK2 according to the main clock signal MCK. 1 帛 水平 水平 练 练 练 聪 聪 聪 聪 聪 聪 聪 聪 聪 聪 聪 聪 聪 聪 聪 帛 帛 帛The second vertical shift clock signal can also be less than or equal to the frequency VQQ of the vertical shift clock. 22 has a first horizontal shift register 22. The first horizontal shift register 22 receives the oblique input 鄕 水平 水平 水平 水平. The first water 22_f-level residual report 峨TM slightly oblique input clock signal HST,
產生-取樣時脈訊號’用於取樣外部裝置所傳送之—影像資料。本發明 之時序控制電軸水平鶴魏2G設置#第二水平雜暫麵^其 接收水平輸入時脈訊號HST與第二水平移位時脈訊號M2，並依據第二^ 平移位時脈峨腿_水平輸人輕訊號HST而產生__鱗時脈訊號， =據時料脈訊號傳送-時騎料至時序產生器1(μ時序產生器ι〇依據 時序身料，產生-時序控舰號並傳送至水平驅動電路2G，以控制水平驅 動電路20 〇 ^平驅動電路20另包括-閃鎖模組26 U及一數位類比轉換電路28。 問鎖模組26包括_取樣_電路26〇與一保持問鎖電路·。取樣閃鎖電 路260依據第一水平移位暫存器烈所產生之取斜脈訊號取樣影像資料， 產生複數取樣資料。保持_電路262依據時序控制訊號，保持取樣閃鎖 電路細之該些取樣資料。數位類比轉換器㈤係將保持的取樣資料轉換為 類比顯示職，並傳送賴示賊45之#料線（圖未繪），糊示影像。 顯不裝置1之垂直驅動電路30具有一第一垂直移位暫存器32。第一 垂直移位暫存H 32接收垂直輸入時脈訊號VST與第_垂直移位時脈訊號 XK1第垂直移位暫存器32如同前述第一水平移位暫存器22，係依據第 一垂直移位時脈訊號VCK1延遲垂直輸入時脈訊號VST而產生一選擇時脈訊 號’用於選擇顯示區域45之垂直掃描線（圖未繪），即控麵示區域45之 垂直掃描線（圖未繪）。此外，本發明之時序控制電路相對於垂直驅動電路 30汉有一第二垂直移位暫存器34，其依據第二垂直移位時脈訊號vck2，延 200834508 遲垂直輸入時脈訊號VST而產生一 傳送一時序資料至時序產生 時序《说號’並依據此時序時脈訊號 制訊號並傳直轉電路n、產生11()絲時序轉產生時序控 此某一期間進行局部顯示模式。用時序控制訊號控制垂直驅動電路3〇在 上述之兩種情形，匕f爾綠 動電路30之時序控制訊號並不只用於The generated-sampling clock signal is used to sample the image data transmitted by the external device. The timing control electric axis horizontal Hewei 2G setting of the present invention #second horizontal miscellaneous surface ^ receives the horizontal input clock signal HST and the second horizontal shift clock signal M2, and according to the second flat shift clock pulse _ horizontal input light signal HST and __scale clock signal, = according to the time pulse signal transmission - when riding to the timing generator 1 (μ timing generator ι 〇 according to the timing body, generate - timing control ship number And transmitted to the horizontal driving circuit 2G to control the horizontal driving circuit 20, the driving circuit 20 further includes a flash lock module 26 U and a digital analog conversion circuit 28. The question lock module 26 includes a _sampling circuit 26 A hold lock circuit 260. The sample flash lock circuit 260 generates a plurality of sampled data according to the oblique pulse signal sampled image data generated by the first horizontal shift register, and the hold_circuit 262 maintains the sample flash according to the timing control signal. The lock circuit is fine for the sampling data. The digital analog converter (5) converts the held sample data into an analog display job, and transmits the #料线 of the thief 45 (not shown), and pastes the image. The vertical drive circuit 30 has a a vertical shift register 32. The first vertical shift register H32 receives the vertical input clock signal VST and the first vertical shift clock signal XK1, the vertical shift register 32 is as the first horizontal shift described above. The register 22 generates a selective clock signal according to the first vertical shift clock signal VCK1 to delay the vertical input clock signal VST. The vertical scanning line for selecting the display area 45 (not shown), that is, the control surface The vertical scanning line of the display area 45 (not shown). In addition, the timing control circuit of the present invention has a second vertical shift register 34 with respect to the vertical driving circuit 30, which is based on the second vertical shift clock signal vck2. , 200832508 delay vertical input clock signal VST to generate a transmission of timing data to the timing generation timing "speaking number" and according to the timing clock signal signal and pass the circuit to n, generate 11 () wire timing conversion timing The local display mode is controlled during a certain period. The vertical driving circuit is controlled by the timing control signal. In the above two cases, the timing control signal of the green circuit 30 is not only used.
為本發明之崎_ 262細湖顯示模式僅 直驅動電路％ + 之時序控制訊號係依據水平驅動電路2〇與垂 2動·30之料方式所需洲於不同情形 j 鮮二垂直移㈣存器34所轉歸序產生㈣^序 序控軌號之時序_所對應之時 產 時序控制訊號。 座王益iU產生 第二垂由本發狀時雜魏路藉岭二水伟位键1124或是 所:習ft 產生時序控制訊號，即不需如第a圖與第U圖 料不LtZr動電路或㉞直軸f路之倾移位雜11轉時序資 ’產生時序控制訊號。如此’水平驅動電路20或是垂直驅動電路邪 之第一水平移位暫存器24與第—垂直餘暫存器34的長度將不會超出顯 :面板的^下左右之長度，林會發生訊號傳輸延遲賴題，故可提升顯 不器之顯不效能。 請參閱第五圖，其為本發明與習知之時序時脈訊號之時序圖。由於習 知技術係在料絲與妓鶴·之原有移_抑纽置虛設移 位暫存器，如此虛設移位暫存麟產生之時料觀號之週賊同於水求 驅動電路_直赖電路之縣雜暫存騎產生之雜減，所以虛設 移位暫存器之級數會較高，而佔用面積且增加功率消耗。 如第五圖麻’若要在_ T1產生高準敗時序控制峨，f知虛設 移位暫存器必社少有20級，以便在第3級及第19級回傳時序資料至時 200834508 序產生器ίο，供時序產生器10依據時序雜產生所需要之時序控制訊號。 細’本發明增設之移位暫存H所產生之時料脈職的週期不需和原有 ' _暫存骑產生之時脈訊號的聊-樣，所以本發明增設之移位暫存器 找數在小於習賴設移位暫存㈣情況τ，就可產生所需之時序控制訊 號。如圖所示’本發明增設之移位暫存器只需4、級，即可在時間T1產生高 準位之時序控制訊號。由於本發明增設之時序時脈訊號之頻率小於習知2 設移位暫抑之時料脈職的辭，即可產辦序㈣赠，如此移ς 暫存紅城可大贼健崎低神，且微善目雜暫柿之級數過 _ 長而影響顯示面板之設計面積。 此外，本發明之顯示裝置i的時序控制電路所產生之時序控制訊號並 不侷限於使用在水平驅動電路2G及垂直鶴電路3Q，亦可使祕其他電 路。如第六圖所示’其為本發日月之另一較佳實施例之方塊圖。在全整;^— integration)·示硫巾’通常包含有—電壓轉換電路5Q。電壓轉換電 路50輕接有-參考電麼、一共同電壓與一介面（时咐咖，ι/ρ)，以轉 換外部輸入的-個直流電壓而輸出較高之正電壓或負電壓，例如將一個抓 電壓轉換成6V «及-3V電壓以供其他電路使用。然而，接收此電壓之其 他電路並非-直在動作，為了㈣、功率，可在其他電路未動作期間將電壓 • 轉換· 50暫時關閉。本發明之第二水平移位暫存胃24或第二垂直移位 暫存器34可提供時脈訊號至電壓轉換電路5〇作為時序控制訊號，而控制 電壓轉換電路50，並改Μ雜觀號籠準倾料雜舰號輸出至 水平驅動電路20，以控制水平驅動電路20。此外，亦可由第二水平移位暫 存器24或第二垂直移位暫存器34提供時序資料至時序產生器，而對應 產生時序控制訊號並傳送至電壓轉換電路5〇，以控制電壓轉換電路5〇。 綜上所述，本發明之顯示裝置之時序控制電路包含時序產生器以及第 二水平移位暫存贿第二絲移位暫辆。本發明之時序控制方法藉由時 序產生器產生水平輸入時脈訊號以及弟一水平移位時脈訊號。第二水平移 位暫存器依據水平輸入時脈訊號與弟二水平移位時脈訊號，產生時序資料 11 200834508 並傳送至時序產生器。時序產生賊_序資料，產辦雜制訊號並傳 送水平驅誠路雜躲平輔。第二垂直移位暫存關樣依據時序 產生器職生之爐錢紅妓錄雜喊，而產 序資料供時序產生n依據時序資料，產生時雜做號麟送至垂直 電路，以控繼直驅動電路，如此可降低功率消耗，且可糊進行雙 描0 ^ 以上所述僅為本發明之較佳實施例，並非用來限定本發明所 ，，舉凡依本發明所述之形狀、構造及/或特徵所為 化轉 均應包括於本發明之申請專利範圍内。 寻炱化飾， 【圖式簡單說明】 弟一圖為習知液晶顯示器之方塊圖； 第二圖為另一習知液晶顯示器之方塊圖； 柯板之錢示意圖； 第習知移鱗存^設置於顯示蛛之另— 第四圖林發明之-較佳實補之方細；。β ’ 第五圖為本發贿f知之時料脈峨之時 第六圖為本發明之另—較佳實施例之方侧。 【主要元件符號說明】 1 顯示裝置 10, 時序產生器 12, 第一計數器 14, 第二計數器 20, 垂直驅動電路 22, 移位暫存器 30, 水平驅動電路 12 200834508 32’移位暫存器 34’虛設移位暫存器 40 顯示面板 45 顯示區域 10 時序產生器 20 水平驅動電路 22 第一水平移位暫存器 24 第二水平移位暫存器 26 閂鎖模組 260取樣閂鎖電路 262保持閂鎖電路 28 數位類比轉換器 30 垂直驅動電路 32 第一垂直移位暫存器 34 第二垂直移位暫存器 45 顯示區域 50 電壓轉換電路For the invention of the saki _ 262 fine lake display mode only direct drive circuit % + timing control signal is based on the horizontal drive circuit 2 〇 and vertical 2 movement · 30 material mode required in different situations j fresh two vertical shift (four) The sequence of the device 34 is generated by (4) the timing of the sequence control track number _ corresponding to the time production timing control signal. The seat of Wang Yi iU produces the second hanging from the hairline when the Wei Wei Road borrows the Lingshui Weiwei key 1124 or the: ft to generate the timing control signal, ie does not need to be the LtZr moving circuit as the first picture and the U picture Or 34 straight-axis f-way tilt shift miscellaneous 11-turn timing to generate timing control signals. Thus, the length of the horizontal drive circuit 20 or the vertical drive circuit of the first horizontal shift register 24 and the first vertical residual register 34 will not exceed the length of the panel: The signal transmission delay depends on the problem, so it can improve the display performance of the display. Please refer to the fifth figure, which is a timing diagram of the timing clock signal of the present invention and the prior art. Because the conventional technology is in the original shift of the wire and the crane, and the dummy shift register is used, so the dummy shift is temporarily stored in the thief. It is directly dependent on the miscellaneous reduction of the county's temporary storage, so the number of stages of the dummy shift register will be higher, occupying the area and increasing the power consumption. As shown in the fifth figure, if you want to generate high-definition timing control in _T1, you will have 20 levels in the virtual shift register, so that the timing data will be returned at the 3rd and 19th levels until 200834508. The sequence generator ίο is used by the timing generator 10 to generate timing control signals according to timing. The cycle of the time pulse generated by the shift temporary storage H added by the present invention does not need to be compared with the original pulse signal generated by the temporary storage, so the shift register provided by the present invention is added. Finding the number in less than the Xi's shift temporary storage (4) case τ, can generate the required timing control signal. As shown in the figure, the shift register provided by the present invention only needs 4 stages, and a timing control signal of a high level can be generated at time T1. Since the frequency of the time-series signal signal added by the present invention is smaller than that of the conventional 2 set shift temporary suppression, the order can be produced (4), so the temporary storage of the red city can be a big thief Jianqi low god And the number of grades of the persimmons is too long and affects the design area of the display panel. Further, the timing control signal generated by the timing control circuit of the display device i of the present invention is not limited to use in the horizontal driving circuit 2G and the vertical crane circuit 3Q, and other circuits can be made secret. As shown in the sixth figure, it is a block diagram of another preferred embodiment of the present day. In the whole, ^-integration, the sulfur blade is usually included with a voltage conversion circuit 5Q. The voltage conversion circuit 50 is connected with a reference voltage, a common voltage and an interface (time ρ, ι / ρ) to convert an externally input DC voltage to output a higher positive or negative voltage, for example A grab voltage is converted to 6V « and -3V for other circuits. However, the other circuit that receives this voltage is not - straight action, for (4), power, the voltage / conversion / 50 can be temporarily turned off while other circuits are not operating. The second horizontal shift temporary storage 24 or the second vertical shift register 34 of the present invention can provide the clock signal to the voltage conversion circuit 5 as a timing control signal, and control the voltage conversion circuit 50, and change the view The number of cages is output to the horizontal drive circuit 20 to control the horizontal drive circuit 20. In addition, the timing data can be provided to the timing generator by the second horizontal shift register 24 or the second vertical shift register 34, and the timing control signal is correspondingly generated and transmitted to the voltage conversion circuit 5 to control the voltage conversion. Circuit 5〇. In summary, the timing control circuit of the display device of the present invention includes a timing generator and a second horizontal shift temporary bribing second wire shifting temporary vehicle. The timing control method of the present invention generates a horizontal input clock signal and a horizontal shift clock signal by a timing generator. The second horizontal shift register generates timing data 11 200834508 according to the horizontal input clock signal and the second horizontal shift clock signal, and transmits to the timing generator. Timing produces thieves _ sequence information, production of miscellaneous signals and transmission of horizontal drive to avoid miscellaneous. The second vertical shift temporary storage is based on the timing generator, and the production data is used for timing generation. According to the time series data, the number is sent to the vertical circuit to control The direct drive circuit can reduce the power consumption, and the paste can be double-drawn. The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and the shape and structure according to the present invention. And/or the features are all included in the scope of the patent application of the present invention.寻炱化饰, [Simple diagram of the drawing] The picture of the younger brother is the block diagram of the conventional LCD display; the second picture is the block diagram of another conventional liquid crystal display; the schematic diagram of the money of the Keban; Set in the display of the spider - the fourth map of the invention - the best compensation; The fifth figure is the time when the bribe is known. The sixth figure is the side of the other preferred embodiment of the present invention. [Main component symbol description] 1 Display device 10, timing generator 12, first counter 14, second counter 20, vertical drive circuit 22, shift register 30, horizontal drive circuit 12 200834508 32' shift register 34' dummy shift register 40 display panel 45 display area 10 timing generator 20 horizontal drive circuit 22 first horizontal shift register 24 second horizontal shift register 26 latch module 260 sample latch circuit 262 hold latch circuit 28 digital analog converter 30 vertical drive circuit 32 first vertical shift register 34 second vertical shift register 45 display area 50 voltage conversion circuit