TWI339881B - Chip package - Google Patents

Chip package

Info

Publication number
TWI339881B
TWI339881B TW096136568A TW96136568A TWI339881B TW I339881 B TWI339881 B TW I339881B TW 096136568 A TW096136568 A TW 096136568A TW 96136568 A TW96136568 A TW 96136568A TW I339881 B TWI339881 B TW I339881B
Authority
TW
Taiwan
Prior art keywords
chip package
package
chip
Prior art date
Application number
TW096136568A
Other languages
English (en)
Other versions
TW200834838A (en
Inventor
Chi Hsing Hsu
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200834838A publication Critical patent/TW200834838A/zh
Application granted granted Critical
Publication of TWI339881B publication Critical patent/TWI339881B/zh

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    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
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TW096136568A 2007-02-15 2007-09-29 Chip package TWI339881B (en)

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US20060081557A1 (en) 2004-10-18 2006-04-20 Molecular Imprints, Inc. Low-k dielectric functional imprinting materials
WO2009067241A1 (en) * 2007-11-21 2009-05-28 Molecular Imprints, Inc. Porous template and imprinting stack for nano-imprint lithography
US8350379B2 (en) * 2008-09-09 2013-01-08 Lsi Corporation Package with power and ground through via
US20100072671A1 (en) * 2008-09-25 2010-03-25 Molecular Imprints, Inc. Nano-imprint lithography template fabrication and treatment
US8470188B2 (en) * 2008-10-02 2013-06-25 Molecular Imprints, Inc. Nano-imprint lithography templates
US20100104852A1 (en) * 2008-10-23 2010-04-29 Molecular Imprints, Inc. Fabrication of High-Throughput Nano-Imprint Lithography Templates
US8616873B2 (en) * 2010-01-26 2013-12-31 Molecular Imprints, Inc. Micro-conformal templates for nanoimprint lithography
TW201144091A (en) * 2010-01-29 2011-12-16 Molecular Imprints Inc Ultra-compliant nanoimprint lithography templates

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JP3432982B2 (ja) * 1995-12-13 2003-08-04 沖電気工業株式会社 表面実装型半導体装置の製造方法
US6889429B2 (en) * 2001-03-26 2005-05-10 Semiconductor Components Industries, L.L.C. Method of making a lead-free integrated circuit package
US6506633B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of fabricating a multi-chip module package
US7042098B2 (en) * 2003-07-07 2006-05-09 Freescale Semiconductor,Inc Bonding pad for a packaged integrated circuit
JP5123664B2 (ja) * 2005-09-28 2013-01-23 スパンション エルエルシー 半導体装置およびその製造方法
KR100871382B1 (ko) * 2007-06-26 2008-12-02 주식회사 하이닉스반도체 관통 실리콘 비아 스택 패키지 및 그의 제조 방법

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CN101136382A (zh) 2008-03-05
US20080197503A1 (en) 2008-08-21
CN100573858C (zh) 2009-12-23

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