TWI339506B - Phase lock loop circuit and corresponding frequency conversion method - Google Patents

Abstract

The present invention relates to a phase lock loop circuit. The phase lock loop circuit includes a phase frequency detector, a filter, a voltage-controlled oscillator, and an M multiple divider. The phase frequency detector has an input configured for inputting a reference frequency. The M multiple divider has an output configured for outputting a channel frequency. The phase lock loop further includes a N/N+1 multiple divider and a N/N+1 multiple divider controller. The N/N+1 multiple divider has an input connected to the voltage-controlled oscillator, an output connected to the phase frequency detector. The N/N+1 multiple divider further includes another input connected to the N/N+1 multiple divider controller for receiving control signals produced from the N/N+1 multiple divider controller, such that the N/N+1 multiple divider can output N during a first period of a working cycle, and output N+1 during a second period of the working cycle.

Description

1339506 12 丨 丨 d d d d d d 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六 六The method, in particular, relates to a method for accurately converting the frequency of a phase locked loop circuit. [Prior Art] [_2]Dlgital Television is a television system developed for the family to feel the strong atmosphere of the theater. Compared with the widely used analog TV, it greatly improves the clarity and width of the picture, and it is: 〇)(〇)〇1!103<:1;1)丨5(:) Road sound. For digital TV, the United States, Europe, and transcripts; the state is in the process of formulating its own broadcasting system, and the United States adopts the Vestigial Sideband (VSB) system. For details, see Wayne et al. C〇nsumei·

VSB Modem Subsystem Design for Grand Alliance Digital Television Receivers, published in Electronics, Vol. 41, No. 3, August 995. [0003] A phase locked loop circuit is generally provided in the receiver of the aforementioned digital television. Referring to FIG. 1 , a commonly used phase-locked loop circuit includes a phase detector 11 , a filter 12 connected to the output end of the phase detector 11 , and a voltage control connected to the output end of the filter 12 . The oscillator 13 is connected to the output of the voltage controlled oscillator 13 and the multiple frequency divider 14 , and a multiple of the input terminal connected to the phase detector 11 and the other output terminal of the voltage controlled oscillator 13 Frequency divider 15. Among them, Μ and Ν are both integers. [0004] The other input end of the phase detector 11 inputs a reference frequency f, which is ref ref 096147845 Form No. A0101 Page 4 / Total 18 Page 0993469765-0 1339506 • » December 30, 2010 The output of the digital divider 14 outputs a channel frequency. The output frequency of the output terminal of the voltage controlled oscillator 13 can be calculated by using the path frequency f channel. That is, and the voltage controlled oscillator has a feedback loop composed of the N-multiplier 15 and the phase detector 11 to make the output frequency of the voltage-controlled oscillator f vco

VCO: Nf is equal to Ν times the reference frequency f ref , that is, ref ο [0005] & the voltage of the voltage controlled oscillator η is not a positive multiple of the reference frequency f vco ref, so when the pressure is controlled The output frequency of the buffer 13 • fVC〇 is not the reference frequency ~ “integer multiple, the phase-locked loop circuit cannot be used to generate the required output frequency f vco of the voltage-controlled oscillator 丨3, which greatly limits the output frequency f vco The path frequency of the phase-locked loop circuit f. channel [0006] In view of this, it is necessary to provide a phase-locked loop circuit whose output path frequency is not limited and a corresponding frequency conversion method thereof. 0007]

[0008] Hereinafter, a phase-locked loop circuit and its corresponding frequency conversion method will be described by way of an embodiment, and its path frequency is not limited at all. A phase locked loop circuit comprising a phase detector, a filter connected to an output end of the phase detector, a voltage controlled oscillator connected to an output end of the filter, and - and the voltage The output frequency of the control oscillator is connected to a multiple frequency divider to receive an output frequency outputted by the output of the voltage controlled oscillator, and one input end of the phase detector inputs a reference frequency, the multiple of the reference frequency The output end of the frequency converter outputs a desired channel frequency, wherein the phase-locked loop circuit further comprises a Ν/Ν + 1 multiple frequency divider and a Ν/Ν+ι multiple frequency divider controller, the Ν/Ν + 1 The multiplier is placed between the phase detector and the 096147845 voltage controlled oscillator, and an input is connected to the voltage controlled oscillator form number Α0101, page 5 of 18, which is 0993469765-0 1339506 [0009] [ [0015] [0015] [0015] [0015]

υAugust 30th, the nuclear replacement page I output is connected to the other input of the phase detector, and the other input terminal of the N/N + 1 multiple division Is is connected to the n/n + a multiple frequency dividing controller receives the control signal generated by the N/N+1 multiple frequency dividing controller; the n/n + i controller calculates the ratio of the path frequency to the reference frequency, and processes the ratio Obtaining an integer data and a decimal data; the integer data and the decimal data are calculated to obtain a first time period and a second time period, so that the N/N + 1 multiple frequency divider is outputted during a first time period of one working cycle n multiples, and output N+1 multiples in the second time period. A frequency conversion method for a phase-locked loop circuit includes the following steps: Step 1: Calculate the output frequency of the output required by the 篆 篆 篆 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; . The ratio of the frequency of the M times to the reference frequency is processed to obtain an integer data and a decimal data. Step 3: processing the integer data to obtain a first processed signal p and a second Processing signal a; Step 4: determining whether the second processing signal a is less than a minimum value min, and thus subtracting H and - second adjusting signal aadjust Ϊ Step 5: discrete processing the fractional data to obtain a discrete signal Xin; Step 6: Add the discrete signal xin to the second adjustment signal a adjust to obtain the adjusted second adjustment signal a; adjust 096147845 form number A0101 page 6 / total 18 page 0993469765-0 1339506 099 December 30 Japanese Junzheng Replacement Page [0016] Step 7: Use the adjusted second adjustment signal a" and the first adjustment adjust signal Padjust to obtain a first terminal signal Pfinal a second terminal signal 〜1丨; [0017] Step 8: calculating the first time period 利用1 by using the first terminal signal P, the second terminal signal af.11 na1 f 1 - na 1 and the minimum value min η And the second time period Τ2, the Ν/Ν+1 multiple frequency divider outputs a ν multiple in the first time period T1, and outputs a N+1 multiple in the second time period T2. [0018] Compared with the prior art, the phase-locked loop circuit of the present invention and its corresponding frequency conversion method 'set the N/N+1 multiple frequency divider to the T1 time by using the N/N+1 multiple frequency dividing controller. Output N multiple, and output N + 1 multiple at time T2' Therefore, the output frequency of the output required by the voltage controlled oscillator does not need to be an integer multiple of the reference frequency, which greatly expands the output frequency of the voltage controlled oscillator. The range also greatly expands the range of the path frequency of the phase-locked loop circuit. Moreover, since the phase-locked loop circuit uses a mathematical algorithm in the frequency conversion process, the area of the circuit is saved. [Embodiment] Φ [0019] The embodiment of the present invention will be further described in detail below with reference to the accompanying drawings. [0020] Referring to FIG. 2, a phase-locked loop circuit 1〇〇 according to an embodiment of the present invention is provided. The 096147845 phase-locked loop circuit 100 includes a phaser 11〇, a filter coupled to the output of the phase detector, a voltage controlled oscillator 130 coupled to the output of the phase detector 110, and A Μ multiplier 14 连接 connected to one of the output terminals of the voltage controlled oscillator 13 。. The phase-locked loop circuit 1 further includes a Ν/Ν + 1 multiple frequency divider 150 and a Ν/Ν + 1 multiple frequency divider controller 160, the Ν/Ν + 1 multiple frequency divider 15〇 and the Phase 1 〇 输入 表 表 表 Α Ι Ι 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 993 993 993 993 993 993 993 993 993 993 993 993 993 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换 替换The ingot|1 is connected to the other output end of the voltage controlled oscillator 130, and the N/N + i multiple frequency divider 150 is connected to the N/N+1 multiple frequency dividing controller 16 to receive The N/N +1 multiple frequency divider controller 16 generates a discrete control signal, and controls the N/N+1 multiple frequency divider 150 to output an N multiple at time T1, and outputs a multiple of N+1 at time T2. The other input end of the phase detector is input-reference frequency Fref, and the output end of the Μ frequency divider 140 outputs a channel frequency F channe1 °. Please refer to FIG. 3 , which is a phase-locked loop circuit provided in an embodiment of the present invention. The frequency conversion method includes the following steps: I Step 1: Calculate the output frequency of the output of the voltage controlled oscillator by using the path frequency. In this step, the output frequency Fvco required by the voltage controlled oscillator 1303⁄4 is twice the Fchannel of the path frequency required for the output of the chirp divider 140, that is, F = MF. Vc〇channel Step 2: Use the channel frequency Fvc〇 (that is, the output frequency of the required output of the voltage controlled oscillator 13〇) and the reference frequency Frd to obtain the channel frequency of the channel frequency '(:0 and reference frequency^ The ratio is processed to obtain an integer data and a decimal data. In this step, the ratio of the channel frequency Fvco to the reference frequency Fref can be processed by a round function to obtain The integer data f.+ and the decimal data f. Winter use & - is not limited to the round function, it can also be processed in the form of floor function or ceu function. 096147845 Form No. A0101 Page 8 / Total 18 pages 0993469765-0 1339506 • · Dan.. December 30, 099 shuttle is replacing page [0026], if the factory such as "functi〇n way to compare values for processing, ^ positive poor ^integer Round(Fvc/Fref); and the decimal data ffractlonal = (Fvc〇/Fref) — finteger, where the fractional data is fractional positive or negative. If H采取r function is used, the ratio is Line processing, the integer data integer i1〇〇r (Fvco / Fref); and the decimal data fractional (Fvc 〇 / Fref) [i nteger ' where the decimal data ffractiona 丨 can only be a positive number. Similarly, if you take the Ceil function The ratio is processed, the integer data f teger = Ceil(Fvcc/Fref); and the fractional data fractional = (Fvc〇/Fref) a fin, tegei•, where the fractional data is only negative. [0027] Step 3 The integer data is processed to obtain a first processing signal p and a second processing signal a. [0028]

In this step, the first processing signal P is the integer data f divided by x integer and then obtained by fl〇〇r functi〇n, that is, p = fi〇〇r(f in teger/N); The second processing signal a is obtained by subtracting the integer data f from the integer of the first processing signal P and N, that is, [0029] a: integer

p*N

[0030] Step 4: determining whether the second processing signal a is less than a minimum value min, and thereby obtaining a first adjustment signal paqust and a second adjustment signal Bad just 0 when the first processing signal a is small, It is easy to be filtered by the phase-locked loop circuit 10D. To avoid this phenomenon, need to process the first signal? And second 096147845 Form No. A0101 Page 9 / Total 18 Page 0993469765-0 [0031] [0033] [0036] [0037] [0038] [0038] Processing signal a is adjusted to correspondingly Obtaining the first adjustment signal p

Had -

Just and a second adjustment signal aadjust. Therefore, in this step, a minimum value min ' is set to the minimum value mi η as an integer. When the second processing signal β is smaller than the minimum value miη, then p ^. =p _ ] , a = a + N , If not, Padjust = p, aad"ust = a, to avoid the above phenomenon. Step 5: discrete processing the fractional data to obtain a discrete signal xin. In this step, the fractional data ffractlQnal is discretely processed to obtain a discrete signal Xin, and the discrete processing may multiply the fractional data fractional A discrete number of bits i:t: nu secret er), such as 2bit, etc., and then the product is rounded up, from the broken scales full signal ^in, ie xin = fl〇〇r ( f 氺 fractional ' step 6: adding the discrete signal Xin to the second adjustment signal a adjust to obtain the adjusted second adjustment signal a. In this step, 'add the discrete signal xin obtained in step 5 to the first adjustment signal aadjust to obtain Adjusted second adjustment signal just, ie aadjust = aadjust+xiri. Step 7: Use the adjusted second adjustment signal a and the first adjustment ^ ad just 汛 Pa Padjust to get a first terminal signal Pf ., and a first Second terminal final number. final In this step, the second adjustment signal 3 and the first adjustment signal adjust, Padjust need to be further processed to obtain the first terminal signal 09 6147845 Form No. A0101 Page / 0/18 pages 0993469765-0 1339506 _ December 30, 1999, the child's ridge page fina丨 and the second terminal signal afin£^, which further includes the following steps: [0039] a : Determining whether the adjusted second adjustment signal aadjust is greater than the sum of n and the minimum value min η, if greater than, then p".=ρ +1 » adjusts aadjust = aadjust - N, and returns to continue to perform a, if not, then Executing b; [0040] b: determining whether the adjusted second adjustment signal is less than the minimum value min, and if so, then Pf. . =p .. - 1 5 a .. + + N, if not final adjust final adjust & , then Pf. , =p".', and af. .=a .. + ° final ad just final ad just

[0041] Through the above two steps, the second adjustment signal a ^ and the first adjustment d d j U s t signal p are further processed to obtain a first terminal signal pf., and a second final terminal signal a, . Final [0042] Step 8: calculating the first time period Τ1 and the second time period 利用2 by using the first terminal signal pf., the second terminal signal a.11 η 31 f [na 1 and the minimum value min η The Ν/Ν+1 multiple frequency divider outputs a Ν multiple in the first time period Τ1, and outputs a Ν+1 multiple in the second time period Τ2. [0043] In this step, the first terminal signal 卩, ., the second terminal signal afinal and the minimum value min are used to calculate a first time period T1 and a second multiple of the output N+1 that need to output N times. Time period T2, where T1 is (p, .fbu na 1 ~a ,)*N*T , and the second time period T2 is final vco a,. ,*(N+1)*T , T is The period of F (1/F). Final vco vco vco vco [0044] Compared to the prior art, the phase-locked loop circuit 100 of the present invention and its corresponding frequency conversion method are set to N/N + 1 multiples by using the N/N+1 multiple frequency dividing controller 160. The frequency divider 150 outputs N times at the time T1, and the N+1 multiple is output at the time T2. Therefore, the output of the voltage controlled oscillator 130 needs to be output 096147845. The form is spliced A0101 page 11/18 page 0993469765- 0 1339506

I. December 3, 099 Η Amendment page I The frequency F does not need to be an integer multiple of the reference frequency F f , which greatly expands the range of the output frequency F of the voltage controlled oscillator 130, and also

V CO greatly expands the path frequency F u of the phase-locked loop circuit 100. Moreover, since the phase-locked loop circuit 100 adopts a mathematical algorithm in the frequency conversion process, the area of the circuit is saved. [0045] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Any equivalent modifications or variations made by those skilled in the art to the spirit of the present invention are intended to be included in the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0046] FIG. 1 is a schematic diagram of a phase-locked disk electric-road name provided by the prior art. 2 is a schematic diagram of a phase locked loop circuit according to an embodiment of the present invention. 3 is a schematic diagram of a frequency conversion method of a phase locked loop circuit according to an embodiment of the present invention. [Main component symbol description] · [0049] Phase-locked loop circuit: 1 0,1 0 0 [0050] Phase detector: 11,110 [0051] Filter: 12,120 [0052] Voltage-controlled oscillator: 13, 130 [0053] Μ Multiplier: 14,140 [0054] ΝMultiplier: 15 096147845 Form No. 1010101 Page 12/Total 18 Page 0993469765-0 1339506 December 30, 2017 Shuttle Replacement Page [0055 ] N/N + 1 multiple divider: 150 [0056] N/N + 1 multiple divider: 160

096147845 Form No. A0101 Page 13/Total] Page 8 0993469765-0

Claims (1)

1339506 I 095 December 3ϋ 修正 Correct replacement page VII. Patent application scope: 1. A phase-locked loop circuit comprising a phase detector, an output of the phase detector a phase-connected filter, a voltage-controlled oscillator connected to the output of the filter, and a 倍 multiplier connected to an output of the voltage-controlled oscillator to receive the voltage-controlled oscillator One output frequency outputted by the output terminal, one input end of the phase detector inputs a reference frequency, and the output end of the Μ multiple frequency divider outputs a required channel frequency, and the improvement is that the phase-locked loop circuit further includes a Ν/Ν+1 multiple frequency divider and one Ν/Ν+1 multiple frequency dividing controller, the Ν/Ν + 1 multiple frequency divider is disposed between the phase detector and the voltage controlled oscillator, one input end thereof Connected to the voltage controlled oscillator, the output of which is connected to the other input of the phase detector, and the other input of the /N+1 multiple frequency divider is connected to the Ν/Ν + ΐ ΐ The control signal generated by receiving the Ν/Ν + 1 multiple frequency divider controller: the Ν/Ν + 1 controller calculates the ratio of the path frequency to the reference frequency, and processes the ratio to obtain an integer data and Fractional data; the integer data and the decimal data are calculated by the first time And a second period, so that the Ν / Ν + 1 fold multiple of the first frequency divider output v a duty cycle of the time period, the second period of the output Ν + 1 multiples. 2 . A frequency conversion method for a phase locked loop circuit, comprising: Step 1: calculating an output frequency of an output required by the voltage controlled oscillator by using a path frequency; Step 2: obtaining the channel frequency and a reference frequency by using a channel frequency Μ times the ratio between the channel frequency and the reference frequency, the ratio is processed to obtain an integer data and a decimal data; Step 3: processing the integer data to obtain a first processing signal ρ 096147845 Form number Α 0101 14 Page / Total 18 pages 0993469765-0 1339506 On December 30, 099, the shuttle is replacing the page and a second processing signal a; Step 4: determining whether the second processed signal a is smaller than a minimum value mi η, and thus obtaining a first An adjustment signal ρ β + and a second adjustment signal du JUSt aad just ; Step 5: discrete processing the fractional data to obtain a discrete signal xin; Step 6: adding the discrete signal xin to the second adjustment signal a Adjust adjusts the second adjustment signal a ^. + ; ad just Step 7: using the adjusted second adjustment signal ap and the first adjustment adjust signal Padjust to obtain a first terminal signal Pfinal and a second terminal signal a.., final Step 8: using the first terminal signal p, The second terminal signal Γ 1 Π d 1 af inai and the minimum value miη calculate the first time period τ 1 and the second time period Τ 2, and the Ν / Ν + 1 multiple frequency divider is output in the first time period τι Ν multiple ' and output Ν + 1 multiple in the second time period Τ2. Frequency conversion method of a phase locked loop circuit as described in claim 2 Wherein, in step one, the output frequency of the voltage controlled oscillator is Μ times the channel frequency. 4. The frequency conversion method of the phase-locked loop circuit according to claim 3, wherein in the second step, the integer data can be obtained by using r〇und functi〇n and floorfuncti〇n to obtain the decimal data as the ratio. The difference from the integer data. The frequency conversion method of the phase-locked loop circuit as described in claim 4 of the scope of the patent patent, wherein in step 3, the first processing signal is obtained by dividing the integer data by N and then by floor functi〇n, The second processing signal 096147845 0993469765-0 is obtained by subtracting the product of the first processing signal and 1^ from the integer data. A0101 Page 15 of 18 1339506 I _ 一_ _ «1 j I 093 iZ month 3U H to the replacement page, such as the frequency conversion method of the phase-locked loop described in claim 5, in step four If the second processing signal a is smaller than the minimum value, Pad just=p*-J, 3ad just = a 〇a adjust=a + N; if not, Bay 1Jp adjust :P as described in claim 6 The frequency conversion method of the phase-locked loop circuit', wherein the step 7 further comprises: =p X1 adjust adjust a : determining whether the adjusted second adjustment signal aadiust is greater than the sum of the minimum values min, if greater than, then the ratio adjust = Aadjust - N 'and return to continue a 'If not, then execute b; b: judge the adjusted second adjustment signal is; if ten is the minimum, then p min, if -1, a final ^adjust a ;fi :^acLjust^^, if not, then Pf. . =p , and af. , = a , 〇iinal adjust final adjust The frequency conversion method of the phase-locked loop circuit as described in claim 7 Wherein, the first time period T1 is (pf. -af.,)*N*T, and ί1na 1 final vco is the second time Period T2 is af; nal * (N + l) * T, T F is the circumferential final vco vco vco of (l / F vco 096147845 eds Long Form Page 16 A0101 / 18 Total 0993469765-0