JP6121809B2 - Signal processing apparatus, exciter, and signal processing method - Google Patents

Description

  Embodiments described herein relate generally to a signal processing device applied to a direct conversion method, an exciter equipped with the signal processing device, and a signal processing method.

  Some terrestrial digital broadcasting services and mobile phone communication services adopt the direct conversion method. This direct conversion method is a method of modulating an I (In-phase) component and a Q (Quadrature) component of a baseband signal to be transmitted using a pair of orthogonal carriers having a frequency equal to the frequency of the output carry-out wave.

  A conventional direct conversion modulator analog-converts each of the I and Q components of a digital baseband signal digitally processed at a specified sampling frequency by a digital / analog converter (DAC), Analog modulation is performed for each of the I and Q components using a specified orthogonal carrier (two output carriers having the same frequency and 90 ° out of phase with each other) to obtain a signal having a specified output carrier frequency. .

In the above-described method, it is necessary to generate orthogonal carriers corresponding to the I and Q components, respectively, and it is also necessary to configure all circuits such as DACs for I and Q components and mixers for modulation, all with analog circuits. was there. Therefore, in addition to the demerit that the circuit scale increases as a whole, there is a problem that it is difficult to increase the modulation accuracy due to the orthogonal modulation error.
Therefore, in a communication service that requires a high C / N ratio (Carrier to Noise Ratio), a modulation method using a digital method has become mainstream (see, for example, Patent Document 1).

  Here, when an orthogonal modulation circuit that performs a modulation method using a digital method is operated only with a predetermined clock signal, the frequency accuracy and stability of the orthogonal carrier wave output from the digital modulation circuit is determined by the clock signal. However, high accuracy and stability are not guaranteed for the clock signal for operating the modulation circuit. Therefore, if the digital modulation circuit is operated only with the clock signal, it is not possible to generate a broadcast wave with high frequency accuracy and stability that satisfies the standards of the terrestrial digital broadcast service or the like.

  Therefore, since a quadrature modulation circuit using a modulation method using a digital method outputs a quadrature carrier wave having high frequency accuracy, it is necessary to separately include a local signal oscillator that outputs a local signal serving as the carrier wave. This local signal oscillator receives a high-accuracy standard frequency input from a predetermined frequency standard, and generates a local signal with high frequency accuracy and stability based on this. As the predetermined frequency standard, for example, a rubidium frequency standard, a GPS (Global Positioning System) frequency standard, or the like is used.

JP 2006-186697 A

  In this case, in the modulation method using the above digital method, an oscillator for generating a local signal (analog signal) as an output carrier wave with high frequency accuracy is required, and this local signal is once passed through the ADC. Processing to sample (digitize) is required. Therefore, there is a problem that the process scale is large and the circuit scale is large.

  The problem to be solved by the present invention is to provide a signal processing device, an exciter, and a signal processing method for generating an output carrier wave having high frequency accuracy and stability while simplifying the process and the circuit scale. .

The signal processing apparatus according to the embodiment includes a frequency set value calculation unit and a carrier wave signal generation unit. The frequency set value calculation unit inputs a clock signal and a standard signal that oscillates at a standard frequency with higher frequency accuracy than the clock signal, calculates the clock frequency of the clock signal based on the standard signal, A frequency setting value having a negative correlation with the calculated clock frequency is calculated.
The carrier signal generation unit is a circuit that sequentially outputs a digital sampling value of a predetermined periodic waveform signal in synchronization with the clock signal, and when the digital sampling value is sequentially output at a constant period, the digital sampling value The digital sampling value to be output is changed so that the frequency of the periodic waveform signal formed by (1) increases or decreases in proportion to the frequency setting value.

In the signal processing method of the embodiment, the frequency set value calculation unit inputs a clock signal and a standard signal that oscillates at a standard frequency with higher frequency accuracy than the clock signal, and the clock signal is based on the standard signal. And a frequency setting value having a negative correlation with the calculated clock frequency is calculated.
The carrier signal generator is a circuit that sequentially outputs a digital sampling value of a predetermined periodic waveform signal in synchronization with the clock signal, and when the digital sampling value is sequentially output at a constant period, The digital sampling value to be output is changed so that the frequency of the periodic waveform signal formed by the sampling value increases or decreases in proportion to the frequency setting value.

The figure which shows the function structure of the exciter of 1st Embodiment. The figure which shows the function structure of the signal processing apparatus of 1st Embodiment. The figure explaining the process of the carrier wave signal generation part of 1st Embodiment. The figure explaining the process of the frequency setting value calculating part of 1st Embodiment. The 1st figure explaining the effect of the signal processor of a 1st embodiment. FIG. 5 is a second diagram for explaining the effect of the signal processing apparatus according to the first embodiment. 3 is a third diagram for explaining the effect of the signal processing apparatus according to the first embodiment; FIG. FIG. 4 is a fourth diagram for explaining the effect of the signal processing apparatus according to the first embodiment;

<First Embodiment>
Hereinafter, an exciter according to a first embodiment will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a functional configuration of the exciter according to the first embodiment. In this figure, reference numeral 1 denotes an exciter.

(Outline of exciter)
The exciter 1 according to the present embodiment inputs a broadcast TS (Transport Stream) signal, and this broadcast TS signal conforms to the ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) communication standard used in digital terrestrial television broadcasting. This is an apparatus (Exciter) that converts a modulated signal (I, Q modulated signal) and outputs a broadcast wave on which the I, Q modulated signal is superimposed. The broadcast TS signal is a digital signal including video information and audio information encoded based on a predetermined standard (MPEG-2 (Moving Picture Experts Group-2)).
The exciter 1 is provided in a television broadcasting station, for example. The output carrier wave output from the exciter 1 is amplified by a predetermined amplifier, then radiated to the public wirelessly through an antenna, and sent to a home television. In principle, the exciter 1 outputs an output carrier wave at a frequency (carrier frequency) determined for each exciter 1. Since this carrier frequency corresponds to each channel of terrestrial digital television broadcasting, the output carrier frequency (output carrier frequency f ₀ ) is required to have very high accuracy and stability.

(Overall structure of exciter)
As shown in FIG. 1, the exciter 1 includes a signal processing device 10, a modulation unit 20, a multiplier 21, an adder 22, and a DAC 23.

  The modulation unit 20 inputs a broadcast TS signal, a clock signal (CLK), and a frame synchronization signal (FSYNC), which are digital signals for video / audio conforming to the predetermined standard. The modulation unit 20 performs a process of converting the input broadcast TS signal into a modulation signal conforming to the ISDB-T standard and outputting it in synchronization with the input clock signal CLK and the frame synchronization signal FSYNC. Specifically, the modulation unit 20 converts an input broadcast TS signal into an I-modulated signal and a Q-modulated signal based on the QAM modulation method and outputs the converted signal. Since the specific processing content of the modulation unit 20 is a known technique, detailed description thereof is omitted.

  The signal processing apparatus 10 according to the present embodiment functions as a carrier signal output unit that outputs a carrier signal that is a digital sampling value of an output carrier in synchronization with the clock signal CLK input together with the broadcast TS signal. More specifically, the signal processing device 10 synchronizes with the input clock signal CLK, and each of the sine wave signal and the cosine wave signal, which are two periodic waveform signals having the same frequency and different phases by 90 °, as carrier signals. Are sequentially output in parallel (FIG. 1). Further, the signal processing apparatus 10 according to the present embodiment further inputs a predetermined standard signal REF as an input. The standard signal REF will be described later.

The multiplier 21 is a functional unit that multiplies two input signals (digital sampling values). As shown in FIG. 1, the digital sampling values of the I modulation signal and the Q modulation signal output from the modulation unit 20, and the digital sampling values of the cosine wave signal and the sine wave signal output from the signal processing device 10, respectively. The data is sequentially input and multiplied, and the operation data is sequentially output.
The adder 22 is a functional unit that inputs the operation data of the two multipliers 21 and adds them.

As described above, the modulation unit 20 and the signal processing device 10 sequentially output digital sampling values of the I modulation signal, the Q modulation signal, the cosine wave signal, and the sine wave signal in synchronization with the same clock signal CLK. . Similarly, the multiplier 21 and the adder 22 execute arithmetic processing of various signals that are sequentially input in synchronization with the same clock signal CLK and output it. That is, the modulation unit 20, the signal processing device 10, the multiplier 21, and the adder 22 are all digital circuits that perform various processes using the same clock signal CLK as a drive source.
Here, the clock signal CLK is a signal having a clock frequency fc = 8.13 MHz (more precisely, 512/63 MHz). However, the clock signal CLK is not a signal for which high accuracy and high stability are guaranteed. Therefore, strictly speaking, the clock signal CLK is sequentially input to the modulation unit 20, the signal processing device 10 and the like as a frequency obtained by adding the clock error frequency Δfc to the ideal clock frequency (standard clock frequency) fcr = 8.13 MHz. Will be. In this case, the clock frequency fc can be expressed as fc = fcr + Δfc.
As will be described later, the modulation unit 20 and the signal processing device 10 are actually driven by a multiplied clock signal CLK ′ having a frequency obtained by multiplying the input clock signal CLK by N times (N is an integer of 1 or more). .
The clock frequency is not limited to fc = 8.13 MHz described above, and a frequency such as 10 MHz may be used, for example.

  The DAC 23 is a functional unit that converts an input digital signal (digital sampling value) into an analog signal (actual voltage) and outputs the analog signal. Specifically, the DAC 23 sequentially inputs operation data from the adder 22 output in synchronization with the clock signal CLK, and outputs a voltage corresponding to the operation data. Therefore, the analog signal output from the DAC 23 is a broadcast wave having a predetermined frequency on which the I modulation signal and the Q modulation signal are superimposed.

(Functional configuration of signal processing device)
FIG. 2 is a diagram illustrating a functional configuration of the signal processing apparatus according to the first embodiment.
Next, the functional configuration of the signal processing apparatus 10 described above will be described in detail with reference to FIG.
As shown in FIG. 2, the signal processing apparatus 10 according to the present embodiment includes a frequency set value calculation unit 12 and a carrier wave signal generation unit 13.

The frequency set value calculation unit 12 inputs a standard signal REF that oscillates at a predetermined standard frequency fref from a frequency standard (not shown) that is an external device, and calculates a clock frequency fc of the clock signal CLK that is separately input. have. Here, the frequency standard is, for example, a rubidium frequency standard or a GPS frequency standard.
The frequency set value calculation unit 12 receives a standard signal REF having a standard frequency fref = 10 MHz, for example, from a frequency standard device (not shown). Then, based on the highly accurate standard signal of 10 MHz, the clock frequency fc of the clock signal CLK input separately is calculated as a numerical value. Here, the standard signal REF is a highly accurate signal generated from the frequency standard. Therefore, the frequency set value calculation unit 12 can accurately calculate the clock frequency fc based on the standard signal REF.

  Further, the frequency set value calculation unit 12 calculates the frequency set value ft so as to have a negative correlation with the clock frequency based on the calculated clock frequency fc of the clock signal CLK. That is, the frequency set value calculation unit 12 calculates the frequency set value ft so as to satisfy the relationship of ft∝1 / fc. Specific contents of this processing will be described later.

As shown in FIG. 2, the frequency set value calculation unit 12 includes a carrier frequency storage unit 120. The carrier frequency storage unit 120 is a storage unit that stores an output carrier to be actually output by the exciter 1, that is, a carrier frequency target value f _m0 indicating a target value of a broadcast wave frequency (output carrier frequency f ₀ ). . For example, when the exciter 1 is to output an output carrier with an output carrier frequency f ₀ = 600 MHz, the carrier frequency storage unit 120 stores the numerical value “600 MHz” as the carrier frequency target value f _m0 . . The output carrier frequency f ₀ corresponds to a channel of terrestrial digital broadcasting, and is uniquely determined for each exciter 1 in principle. Therefore, the carrier frequency storage unit 120 stores the carrier frequency target value f _m0 corresponding to the channel that the exciter 1 is responsible for.

The carrier signal generation unit 13 is a digital circuit that receives the frequency setting value ft calculated by the frequency setting value calculation unit 12 and generates and outputs a carrier signal having a frequency corresponding to the frequency setting value ft. Specifically, the carrier wave signal generation unit 13 is a digital circuit that sequentially outputs a digital sampling value of a predetermined periodic waveform signal (that is, a carrier wave signal) in synchronization with an input clock signal CLK. In the present embodiment, the predetermined periodic waveform signal is a cosine wave signal and a sine wave signal having the same frequency and different phases by 90 °.
Here, when the carrier wave signal generation unit 13 sequentially outputs the digital sampling values of the carrier wave signals (the cosine wave signal and the sine wave signal) at a constant cycle, the frequency of the output carrier wave formed by the digital sampling values is It has a function of changing the output digital sampling value so as to increase or decrease in proportion to the frequency setting value ft. Here, “when each digital sampling value is sequentially output at a constant period” means that the clock frequency fc of the clock signal CLK input by the carrier wave signal generation unit 13 is always constant without having an error component (Δf). (Standard clock frequency fcr). The function of this carrier wave signal generation unit 13 will be described in detail below.

(Processing of carrier wave signal generator)
As shown in FIG. 2, the carrier signal generation unit 13 includes a phase accumulator 130, a COS (cosine) table 131, and a SIN (sine) table 132.
The phase accumulator 130 is a functional unit that performs an operation of accumulating the phase P every predetermined phase interval ΔP while synchronizing with the clock signal CLK. When the phase P reaches 360 °, the phase accumulator 130 accumulates again at the same phase interval ΔP from 0 °.
The COS table 131 is a sampling table that stores digital sampling values for one period of a cosine wave signal corresponding to each of the phases P divided at equal intervals.
Similarly, the SIN table 132 is a sampling table that stores digital sampling values for one period of the sine wave signal corresponding to each of the phases P divided at equal intervals.
With the above functional configuration, the carrier wave signal generation unit 13 outputs the digital sampling values of the COS table 131 and the SIN table 132 corresponding to the phase P specified for each phase interval ΔP by the accumulation operation of the phase accumulator 130.

FIG. 3 is a diagram for explaining processing of the carrier wave signal generation unit according to the first embodiment.
The processing of the carrier wave signal generation unit 13 will be described more specifically with reference to FIG.
The carrier wave signal generation unit 13 according to the present embodiment sequentially outputs digital sampling values in synchronization with a multiplied clock signal CLK ′ obtained by multiplying the clock signal CLK by N (N is an integer of 1 or more). The signal processing device 10 includes a predetermined multiplier circuit (not shown), and the carrier wave signal generation unit 13 receives the multiplied clock signal CLK ′ output from the multiplier circuit.
Here, it is assumed that the multiplied clock frequency of the multiplied clock signal CLK ′ obtained by multiplying the clock signal CLK by N times is fc ′ and the period is tc ′ (= 1 / fc ′). Then, the phase accumulator 130 performs a process of calculating the phase P while adding the phase interval ΔP to the previous phase P every period tc ′. Further, as described above, when the phase P reaches 360 °, the phase accumulator 130 performs the accumulation calculation process again at the same phase interval ΔP from 0 °. Therefore, the phase P output from the phase accumulator 130 becomes a triangular wave that gradually increases according to the time t (left in FIG. 3).

As described above, the COS table 131 and the SIN table 132 store digital sampling values for one period of the cosine wave signal and the sine wave signal corresponding to each of the phases P divided at equal intervals ( FIG. 3 right). COS table 131 and SIN table 132, for example, as shown in FIG. 3, the cosine wave signal, 2 ³² divided by the sine wave signal respectively one period of the waveform at equal intervals are sampled.
Carrier signal generation unit 13, from among the 2 ³² digital sampling values stored in each COS table 131 and SIN table 132, selects and outputs the digital sampling values corresponding to the phase P of the phase accumulator 130 is calculated . Then, when the phase P is added from 0 ° to 360 ° over a certain time T, the carrier wave signal generation unit 13 takes the time T [s] and the cosine wave signal and sine wave signal for exactly one cycle. Will be output. Therefore, the period of the cosine wave signal and the sine wave signal in this case is T [s], and the output carrier frequency f ₀ is 1 / T [Hz].

The carrier wave signal generation unit 13 receives the frequency setting value ft from the outside (frequency setting value calculation unit 12), and the frequency of the output carrier wave signal (cosine wave signal, sine wave signal) corresponds to the frequency setting value ft. The phase interval ΔP is set so as to be a value. Here, as shown in FIG. 3, when the frequency setting value ft is a certain value “ft1”, the phase accumulator 130 sets the phase interval ΔP to “10 °”, for example. Then, the phase accumulator 130 accumulates the phase P by the phase interval ΔP = 10 ° every period tc ′ [s]. In this case, since it takes 36 steps to accumulate for one period (that is, up to 360 °), the period T of the output cosine wave signal and sine wave signal is 36 × tc ′ [s] (output carrier frequency) f ₀ is 1 / (36 × tc ′) [Hz]).
On the other hand, when the frequency setting value ft is “ft2” (ft2 is a frequency twice as high as ft1), the phase accumulator 130 sets the phase interval ΔP to twice that in the above case, that is, 20 °. Then, the phase accumulator 130 accumulates the phase P by the phase interval ΔP = 20 ° every period tc ′ [s]. In this case, since 18 steps are required to be accumulated for one period, the period T of the output cosine wave signal and sine wave signal is 18 × tc ′ [s], which is 1/2 ( output carrier frequency _{f 0} is doubled).
In the above description, the phase P and the phase interval ΔP are expressed as an angle [°]. However, in implementation, the phase P and the phase interval ΔP directly specify a memory address for storing a digital sampling value of the carrier wave signal. It is represented by a value indicating the value and its interval.

That is, when the input frequency set value ft is small, the phase accumulator 130 sets the phase interval ΔP small according to the frequency set value ft. Then, the phase accumulator 130 accumulates the phase P by a small phase interval ΔP every period tc ′, and as a result, the time T until the phase P is accumulated from 0 ° to 360 ° increases. , the output carrier frequency _{f 0} becomes smaller. On the other hand, when the input frequency set value ft is large, the phase accumulator 130 sets the phase interval ΔP to be large in proportion to the frequency set value ft. Then, since the phase accumulator 130 accumulates the phase P by a large phase interval ΔP every period tc ′, the time T until the phase P is accumulated from 0 ° to 360 ° decreases, and the output carrier wave frequency _{f 0} is increased. That is, the output carrier frequency f ₀ is derived from the general formula (1) in relation to the phase interval ΔP and the multiplied clock frequency fc ′.

The phase accumulator 130 receives the specific frequency set value ft, and the output carrier frequency f ₀ matches the frequency set value ft on the assumption that the multiplied clock frequency fc ′ does not vary from the known value in the equation (1). Thus, the phase interval ΔP is set. That is, assuming that a known fixed value predetermined for the multiplied clock frequency fc ′ is the standard multiplied clock frequency fcr ′, the phase accumulator 130 calculates the phase interval ΔP based on Expression (2).

If the phase interval ΔP is set in this way, the carrier signal generation unit 13 sets the output carrier frequency f ₀ of the carrier signal as long as the multiplied clock frequency fc ′ is input in accordance with the fixed standard multiplied clock frequency fcr ′. It can be output in accordance with the frequency set value ft.

As described above, the phase accumulator 130 sets the phase interval ΔP to a value proportional to the input frequency setting value ft. By doing so, the carrier wave signal generation unit 13 is based on the premise that the multiplied clock frequency fc ′ is constant (fcr ′), and the frequency of the cosine wave signal and the sine wave signal formed by the digital sampling value to be output. The output digital sampling value can be changed so that (output carrier frequency f ₀ ) increases or decreases in proportion to the frequency setting value ft.

(Processing of frequency set value calculation unit)
FIG. 4 is a diagram for explaining processing of the frequency set value calculation unit according to the first embodiment.
Next, the processing of the frequency set value calculation unit 12 will be described in detail. The frequency set value calculation unit 12 according to the present embodiment includes a compensation value calculation unit 121 that receives the standard signal REF and the clock signal CLK and calculates a compensation value α according to the frequency difference between the signals. The compensation value calculation unit 121 further includes a circuit that detects a frequency difference between two input signals, and obtains the difference between the standard frequency fref of the standard signal REF and the frequency fc of the clock signal CLK by quantifying the difference. It has a function. Here, since the standard frequency fref is a known value for which high accuracy is guaranteed, the compensation value calculation unit 121 can obtain an accurate clock frequency fc from the obtained frequency difference.
The compensation value calculation unit 121 uses the clock frequency fc obtained as described above and the standard clock frequency fcr which is a known value when there is no error in the clock frequency fc, and the clock error frequency Δfc = fc. -Fcr is calculated.
Then, the compensation value calculation unit 121 calculates and outputs a predetermined compensation value α = Δfc / fc.

The subtracting unit 122 receives the carrier frequency target value f _m0 and the compensation value α stored in the carrier frequency storage unit 120, and performs a process of subtracting a value corresponding to the compensation value α from the carrier frequency target value f _m0 . Specifically, the subtraction unit 122 performs a process (f _m0 −α · f _m0 ) for subtracting the frequency α · f _m0 at a ratio corresponding to the compensation value α from the carrier frequency target value f _m0 . The subtraction unit 122 outputs a value obtained by the subtraction process. Therefore, the frequency setting value ft input to the carrier wave signal generation unit 13 is ft = (1−α) _fm0 .

  Here, since the compensation value α is α = Δfc / fc, the frequency set value ft is actually calculated as shown in Equation (3).

As described above, the frequency setting value calculation unit 12 sets the frequency setting value ft to a value corresponding to fcr / fc which is a ratio between the actual clock frequency fc including an error and the standard clock frequency fcr which is an ideal value. Set to. That is, the frequency set value calculation unit 12 calculates the frequency set value ft so as to have a negative correlation with the clock frequency fc based on the calculated actual clock frequency fc.
The effect of the frequency setting value calculation unit 12 calculating the frequency setting value ft as described above will be described later.

(Explanation of effect)
FIG. 5 is a first diagram for explaining the effect of the signal processing apparatus according to the first embodiment.
The exciter 8 illustrated in FIG. 5 includes a signal processing device 80. As illustrated in FIG. 5, the signal processing device 80 is obtained by removing the functions of the standard frequency acquisition unit 11 and the frequency set value calculation unit 12 from the signal processing device 10 according to the present embodiment. The effects of the signal processing apparatus 10 according to the present embodiment will be described in detail while comparing the characteristics of the exciter 8 including the signal processing apparatus 80 and the exciter 1 including the signal processing apparatus 10.

In the case of the exciter 8 shown in FIG. 5, the carrier signal generation unit 13 simply inputs only the carrier frequency target value f _m0 stored in the carrier frequency storage unit 120. Therefore, for example, when the carrier frequency target value f _m0 is stored as “600 MHz” in the carrier frequency storage unit 120, the carrier signal generation unit 13 inputs the carrier frequency target value f _m0 = 600 MHz from the carrier frequency storage unit 120. Then, the frequency set value ft is set to ft = 600 MHz.

Next, the phase accumulator 130 calculates the phase interval ΔP according to the frequency setting value ft = 600 MHz. Specifically, the phase accumulator 130 outputs the output based on Expression (2) based on the assumption that the multiplied clock frequency fc ′ does not vary from a known fixed value (standard multiplied clock frequency fcr ′) in Expression (1). A phase interval ΔP is calculated such that the carrier wave frequency f ₀ becomes the frequency set value ft (= 600 MHz). Then, the carrier wave signal generation unit 13 synchronizes with the multiplied clock signal CLK ′, and the digital accumulator 130 adds the digital sampling values (in the COS table 131 and the SIN table 132) corresponding to the phase P obtained by adding every phase interval ΔP. The stored one) is output.

  FIG. 6 is a second diagram for explaining the effect of the signal processing apparatus according to the first embodiment. FIG. 7 is a third diagram for explaining the effect of the signal processing apparatus according to the first embodiment.

The graph of FIG. 6 shows an example of the temporal transition of the carrier signal output from the signal processing device 80 (FIG. 5).
As described above, the phase accumulator 130 calculates the phase interval ΔP based on the known standard multiplied clock frequency fcr ′, the frequency setting value ft (= 600 MHz) based on the input from the carrier frequency storage unit 120, and Equation (2). To do. Here, consider a case where the multiplied clock signal CLK ′ is input to the carrier wave signal generation unit 13 as a complete high-frequency signal that does not include the multiplied clock error frequency Δfc ′ in the multiplied clock frequency fc ′. That is, in this case, the multiplied clock frequency fc ′ matches the standard clock frequency fcr ′. In this case, the carrier wave signal generation unit 13 outputs a digital sampling value according to the multiplied clock frequency fc ′ according to the standard multiplied clock frequency fcr ′. Accordingly, as shown in FIG. 6, the carrier wave signal generation unit 13 outputs a digital sampling value of the carrier wave signal at every constant standard period tcr ′ (= 1 / fcr ′), and as a result, the output carrier frequency of the carrier wave signal f ₀ matches the frequency set value ft = 600 MHz, which is the ideal output carrier frequency.

  However, the accuracy and stability of the multiplied clock signal CLK 'depend on the accuracy and stability of the clock signal CLK that is the basis thereof. As described above, the clock signal CLK is not a signal for which high accuracy and high stability are guaranteed. Therefore, actually, the multiplied clock signal CLK ′ is also a signal including the multiplied clock error frequency Δfc ′ in the multiplied clock frequency fc ′ (fc ′ = fcr ′ + Δfc ′). Then, the carrier wave signal generation unit 13 outputs a digital sampling value in synchronization with the multiplied clock signal CLK ′ including this error, and as a result, the frequency of the carrier wave signal may not be as intended (600 MHz). .

The graph of FIG. 7 shows another example of the temporal transition of the carrier signal output from the signal processing device 80 (FIG. 5).
For example, as a result of the multiplication clock frequency fc ′ input to the carrier wave signal generation unit 13 being reduced by the multiplication clock error frequency Δfc ′ (Δfc ′> 0), the period at which the digital sampling value is output from time tcr ′ at time t1. Consider a case in which tcr ′ + Δt (Δt> 0). Since the phase interval ΔP is calculated on the assumption that the multiplied clock frequency fc ′ matches the standard multiplied clock frequency fcr ′, the multiplied clock frequency fc ′ is shifted in the direction of decreasing by Δfc ′ from the standard multiplied clock frequency fcr ′. When the period tcr changes to tcr ′ + Δt, a carrier signal is output at a timing delayed from the ideal output carrier, and the output carrier frequency f ₀ shifts in a decreasing direction (FIG. 7). On the other hand, when the multiplied clock frequency fc ′ is shifted in the direction of increasing by the multiplied clock error frequency Δfc ′ from the standard multiplied clock frequency fcr ′, the carrier signal is output at an earlier timing than the ideal output carrier. Therefore, the output carrier frequency f ₀ is shifted in the increasing direction.

As described above, in the exciter 8 shown in FIG. 5, the accuracy and stability of the output carrier frequency f ₀ depend on the clock frequency fc (multiplied clock frequency fc ′) for which high accuracy and high stability are not guaranteed. Therefore, it is impossible to output an output carrier wave that is high enough to satisfy the standard of the terrestrial digital broadcasting standard.

FIG. 8 is a fourth diagram for explaining the effect of the signal processing apparatus according to the first embodiment.
Next, a carrier wave output from the exciter 1 including the signal processing device 10 according to the present embodiment will be described with reference to FIG.
In the signal processing apparatus 10 according to the present embodiment, as described above, the frequency set value calculation unit 12 inputs the standard signal REF and the clock signal CLK, and has a negative correlation with the clock frequency fc measured accurately. Therefore, the frequency set value ft is calculated so as to have the property (formula (3)).

Here, similarly to FIG. 7, at time t1, the multiplied clock frequency fc ′ decreases from the standard multiplied clock frequency fcr ′ by the multiplied clock error frequency Δfc ′, and the period changes from tcr ′ to tcr ′ + Δt (Δt> 0). Consider the case where
In this case, since the frequency set value calculation unit 12 calculates the frequency set value ft having a negative correlation with the clock frequency fc, the frequency set value ft is greater than the carrier frequency target value f _{m0 at} time t1. It is set to a large value f _m1 (> f _m0 ).

Then, the phase accumulator 130 of the carrier wave signal generation unit 13 calculates a new phase interval ΔP based on the newly set frequency setting value ft = f _m1 (> f _m0 ), and the phase interval ΔP is calculated at time t1. Increase (see equation (2), FIG. 3). Since the phase accumulator 130 accumulates the phase P of the carrier wave signal at a larger phase interval ΔP at time t1, the speed at which the phase P accumulates is increased. As a result, the time delay corresponding to the period error Δt is canceled by the increase in the accumulation rate of the phase P, and the accumulation rate of the phase P is kept constant before and after the time t1.
As described above, the output carrier frequency f ₀ formed from the finally output digital sampling value maintains a constant value (carrier frequency target value f _m0 ) (FIG. 8).

The frequency setting value ft calculated by the frequency setting value calculation unit 12 is calculated as shown in Expression (3). By substituting the frequency setting value ft obtained in this way into the equations (2) and (1), the output carrier frequency f ₀ becomes a constant carrier frequency target value f _m0 that does not depend on the clock error frequency fc. I understand that.
Note that the multiplied clock signal CLK ′ is generated based on the actual clock signal CLK by the multiplier circuit described above. Therefore, the ratio of error components in each signal, that is, the ratio (Δfc / fc) of the clock error frequency Δfc to the clock frequency fc, and the ratio (Δfc ′ / of the multiplied clock error frequency Δfc ′ to the multiplied clock frequency fc ′). fc ′) is assumed to be equal.

As described above, the signal processing device 10 can generate a carrier wave signal formed by the digital sampling value so as to compensate for fluctuations in the output cycle of the digital sampling value based on the error component (clock error frequency Δfc) of the input clock signal CLK. since control is performed to increase or decrease the frequency of, the final output carrier frequency f ₀ can always be stabilized at a constant value.

As described above, according to the signal processing device 10 according to the present embodiment, the frequency setting value calculation unit 12 sets the frequency setting value ft for the carrier signal generation unit 13 so as to compensate for the error of the clock signal CLK. The frequency of the carrier signal output from the signal generator 13 is high in accuracy. Therefore, an oscillator for generating a local signal (analog signal) as an output carrier wave with high frequency accuracy is not required.
In addition, the signal processing apparatus 10 according to the present embodiment outputs the digital sampling value of the carrier signal stored in advance while synchronizing with the clock signal. Therefore, it is not necessary to prepare an analog signal with high frequency accuracy and digitally sample it.

  According to the signal processing device 10 according to the embodiment described above, the frequency setting value calculation unit 12 and the carrier wave signal generation unit 13 are provided, thereby simplifying the process and the circuit scale, but also improving the frequency accuracy and stability. Can produce a high output carrier.

  The signal processing apparatus 10 according to the present embodiment described above is not limited to the above-described aspect, and can be modified as follows.

For example, in the above-described embodiment, the frequency setting value calculation unit 12 outputs the frequency setting value ft to the phase accumulator 130, and the phase accumulator 130 sets the phase interval ΔP according to the input frequency setting value ft. It was decided.
However, in the modification of the present embodiment, the frequency set value calculation unit 12 may calculate the set phase interval ΔPt corresponding to the frequency set value ft in the inside thereof and output this. In this case, the phase accumulator 130 performs a calculation for accumulating the phase P by directly referring to the set phase interval ΔPt input from the frequency set value calculation unit 12.

More specifically, the target phase interval ΔP _m0 corresponding to the carrier frequency target value f _m0 (for example, 600 MHz) is stored in advance in the carrier frequency storage unit 120 of the frequency setting value calculation unit 12 in the modification. .
Then, the subtraction unit 122 receives the target phase interval ΔP _m0 stored in the carrier frequency storage unit 120 and the compensation value α calculated by the compensation value calculation unit 121, and responds to the compensation value α from the target phase interval ΔP _m0. The value (α · ΔP _m0 ) is subtracted. Then, the subtraction unit 122 outputs the value obtained by the subtraction process. Therefore, the set phase interval ΔPt input to the carrier wave signal generation unit 13 is ΔPt = (1−α) ΔP _m0 .

  As described above, in the modification of the present embodiment, the frequency set value calculation unit 12 sequentially calculates the phase interval (set phase interval ΔPt) such that the frequency of the carrier wave to be output by the exciter 1 is constant. However, it may be input to the phase accumulator 130.

In the embodiment described above, and those two storage table (COS table 131, SIN table 132) provided in the carrier signal generating unit 13 sampling data number stored by the cosine wave and sine wave is 2 ³² but were, in other variations, it is not limited thereto, and can be changed, for example, 2 ¹⁶ and 2 ⁸ like.
In another modification, the number of sampling data stored in the two storage tables is smaller than the number of types of phase P that can be specified in the phase accumulator 130 (that is, the number of divisions for one period). May be. For example, types of phase P, which may be specified in the phase accumulator 130 to be the ^{2 32} patterns, may have a structure in which the number of sampling data stored in the COS table 131, SIN table 132 is ^{2 16.}
In this case, the phase P that can be specified by the phase accumulator 130 and the sampling data in the storage table do not correspond one-to-one, but the carrier wave signal generation unit 13 includes the sampling data stored in the storage table. The sampling data corresponding to the phase closest to the phase P designated by the phase accumulator 130 may be selected and output.
Thus, the number of data stored in the COS table 131 and the SIN table 132 is reduced and the memory mounted on the exciter 1 is reduced in size as long as the waveform of the output broadcast wave (output carrier wave) is maintained. It is possible.

In the above-described embodiment, the carrier wave signal generation unit 13 includes the phase accumulator 130 and two storage tables (COS table 131 and SIN table 132), and the phase accumulator 130 calculates in each of the two storage tables. The digital sampling value corresponding to the phase P to be output is output in parallel.
However, in another modification, the carrier wave signal generation unit 13 may include only one storage table that stores the digital sampling value of the sine wave signal. In this case, the carrier wave signal generation unit 13 obtains two digital sampling values specified by the phase P calculated by the phase accumulator 130 and the phase P + 90 ° shifted from the phase P by 90 ° from the one storage table. You may have the function to output.

  The signal processing apparatus 10 described above has been described as one that sequentially outputs digital sampling values in synchronization with the multiplied clock signal CLK ′ obtained by multiplying the clock signal CLK input by the exciter 1 by N times. The signal processing device 10 according to the embodiment may be synchronized with the clock signal CLK. In addition, the fact that each functional component described above operates “in synchronization with the clock signal CLK” includes the meaning that it operates in synchronization with the multiplied clock signal CLK ′ generated based on the clock signal CLK. .

Further, the signal processing apparatus 10 described above may be implemented by a general semiconductor integrated circuit together with the modulation unit 20, the multiplier 21, and the adder 22, for example, an FPGA (Field Programmable Gate Array). It may be implemented by a customizable electronic circuit.
Each process of the signal processing apparatus 10 described above is stored in a computer-readable recording medium in the form of a program, and the above process is performed by the computer reading and executing the program. There may be. Here, the computer-readable recording medium refers to a magnetic disk, a magneto-optical disk, a CD-ROM (Compact Disk Read Only Memory), a semiconductor memory, or the like. Alternatively, the computer program may be distributed to the computer via a communication line, and the computer that has received the distribution may execute the program.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the invention described in the claims and equivalents thereof, as long as they are included in the scope and gist of the invention.

DESCRIPTION OF SYMBOLS 1 ... Exciter 10 ... Signal processing apparatus (carrier wave signal output part)
12 ... Frequency set value calculation unit 120 ... Carrier frequency storage unit 13 ... Carrier signal generation unit 130 ... Phase accumulator 131 ... COS table 132 ... SIN table 20 ... Modulation unit 21 ... Multiplier 22 ... Adder 23 ... DAC

Claims (6)

A clock signal and a standard signal that oscillates at a standard frequency with higher frequency accuracy than the clock signal are input, the clock frequency of the clock signal is calculated based on the standard signal, and the calculated clock frequency A frequency set value calculation unit for calculating a frequency set value having a negative correlation;
A circuit that sequentially outputs a digital sampling value of a predetermined periodic waveform signal in synchronization with the clock signal, and the cycle formed by the digital sampling value when the digital sampling value is sequentially output at a constant period A carrier wave signal generation unit that changes the digital sampling value to be output so that the frequency of the waveform signal increases or decreases in proportion to the frequency setting value;
A signal processing apparatus comprising: The carrier signal generator is
A sampling table for storing the digital sampling value for one period of the periodic waveform signal corresponding to each of the phases divided at equal intervals, and a predetermined phase of the digital sampling values stored in the sampling table; The signal processing apparatus according to claim 1, wherein the signal processing apparatus sequentially outputs a signal corresponding to a phase specified for each interval, and sets the phase interval to a value proportional to the frequency setting value. The carrier signal generator is
The sampling table for each of the two periodic waveform signals whose phases are different from each other by 90 ° is provided, and the two digital sampling values stored in the two sampling tables are output in parallel. The signal processing apparatus according to claim 2. The frequency set value calculator is
The clock frequency fc [MHz], the standard clock frequency fcr [MHz] which is a fixed value when no error is included in the clock frequency, and the target value of the frequency of the periodic waveform signal to be output by the device itself the on the basis of the carrier frequency target value _f m0 [MHz] shown, formula ft = fcr / fc · by _{f m0,} claims 1 to 3, characterized in that calculating the frequency setting value ft [MHz] The signal processing device according to any one of the above. A signal processing device according to any one of claims 1 to 4,
A modulation unit that inputs a predetermined digital signal and the clock signal, converts the digital signal into a modulation signal conforming to a predetermined communication standard and outputs the same while synchronizing with the clock signal;
A multiplier that sequentially inputs and multiplies the digital sampling value of the modulation signal output from the modulation unit and the digital sampling value output from the carrier wave signal generation unit;
An exciter comprising: The frequency set value calculation unit inputs a clock signal and a standard signal that oscillates at a standard frequency with higher frequency accuracy than the clock signal, calculates the clock frequency of the clock signal based on the standard signal, Calculate a frequency setting value having a negative correlation with the calculated clock frequency,
The carrier signal generation unit is a circuit that sequentially outputs a digital sampling value of a predetermined periodic waveform signal in synchronization with the clock signal, and when the digital sampling value is sequentially output at a constant period, the digital sampling value The signal processing method is characterized in that the digital sampling value to be output is changed so that the frequency of the periodic waveform signal formed by the method increases or decreases in proportion to the frequency setting value.

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