TWI339012B - Level-shifting circuit - Google Patents

Description

1339012 A comparator, a logic circuit, a first acceleration circuit, and a second acceleration circuit. The positive feedback circuit receives a first signal and a second signal to generate a third signal and a fourth signal, wherein the first and second signals are mutually inverted signals. The comparator includes a first input receiving the third signal, a second input receiving the fourth signal, and an output generating an output signal according to the third and fourth signals, wherein the output signal has a first A standard, and a second level lower than the first level above. The logic circuit includes a complex logic gate for receiving the first signal to generate a first pulse and a second pulse. The first accelerating circuit is coupled to the first input terminal for receiving the first pulse, and accelerating the comparator to generate the output signal during a pulse width of the first pulse. The second accelerating circuit is coupled to the second input terminal for receiving the second pulse, and accelerating the comparator to generate the output signal during a pulse width of the second pulse. The present invention also provides a voltage level shifting circuit comprising a compare circuit, a logic circuit, and an acceleration circuit. The comparator includes an input end and an output end for receiving an input signal at the input end and offsetting the input signal to generate a round-out signal at the output end. The logic circuit includes a plurality of logic blocks </ RTI> for receiving the input signal to generate a pulse. The accelerating circuit is coupled to the comparator for receiving the pulse and accelerating the comparator to generate the output signal during a pulse width of the pulse. [Embodiment] Voltage level shift circuit 200 FIG. 2 is an embodiment of the present invention

Client's Docket No.: TT's Docket No: 0975-A41244-TW/Final/LukeLee 1339012 includes a positive feedback circuit 202, a comparator 204, a logic circuit 206, an acceleration circuit 208, and an acceleration circuit 210. The positive feedback circuit 202 receives the first signal VI and the second signal V2 to generate the third signal V3 and the fourth signal V4. The first signal VI and the second signal V2 are mutually inverted signals, that is, when the first signal VI is high, the second signal is low, and vice versa. The comparator 204 includes a first input receiving the third signal V3, a second input receiving the fourth signal V4, and an output generating an output signal OUT according to the third signal V3 and the fourth signal V4. The output signal OUT has a different level from the first signal VI and the second signal V2, wherein the high level of the output signal OUT is the voltage BOOT, and the low level is the voltage PHASE. The logic circuit 206 includes a plurality of logic gates for receiving the first signal VI to generate the first pulse P1 and the second pulse P2. The accelerating circuit 208 is coupled to the first input of the comparator 204 for receiving the first pulse P and accelerating the comparator 204 to generate the output signal OUT during the pulse width of the first pulse P1. The accelerating circuit 210 is coupled to the second input of the comparator 204 for receiving the second pulse P2 and accelerating the comparator 204 to generate the output signal OUT during the pulse width of the second pulse P2. Figure 3 is the circuit structure of Figure 2. The positive feedback circuit 202 can include transistors M1, M2, M3, M4, M9, M10, Mil, and M12. Comparator 204 can include transistors M5, M6, M7, and M8, and resistors IU, R2. The logic circuit 206 can include inverters INV1, INV2, INV3, and INV4, and a reverse OR gate NR1 and an inverse gate NA1. The acceleration circuit 208 can include transistors M13, M14, M15, M16. The acceleration circuit 210 may include transistors 1^17, 1\/[18,]^19, ]^20.

Client's Docket No.: TT's Docket No:0975-A41244-TW/Final/LukeLee 7 1339012 In the positive feedback circuit 202, the transistor M1 may be an N-type MOS field-effect transistor, the source of which is coupled to the voltage GND. The gate receives the first signal VI and determines whether the transistor M1 is turned on according to the voltage level of the first signal VI. The transistor M2 can be an N-type MOSFET, the source of which is coupled to the voltage GND, the gate receiving the second signal V2, and determining whether the transistor M2 is turned on according to the voltage level of the second signal V2. The transistor M3 can be a P-type MOS field-effect transistor, the source of which is coupled to the voltage BOOT, the gate is coupled to the gate of the transistor M6 (ie, the second input of the comparator 204), and the gate is coupled. Connected to the gate of transistor M5 (ie, the first input of comparator 204). The transistor M4 can be a P-type MOS field-effect transistor, the source of which is coupled to the voltage BOOT, the gate is coupled to the gate of the transistor M5 (ie, the first input of the comparator 204), and the drain handle Connected to the gate of transistor M6 (ie, the second input of comparator 204). The transistors M9 and M10 can be N-type MOS half-field transistors, forming a Shielding Device, which can avoid high voltage damage to the positive feedback circuit 202. Further, during the conduction of the electric crystal M1 or the transistor M2, the transistors M9, M10, Mil, and M12 can be regarded as resistance. When the first signal VI is at a high level and the second signal V2 is at a low level, the transistor M1 is turned on and the transistor M2 is not turned on, so the third signal V3 is pulled to the voltage GND to turn on the transistor M4. The transistor M4 is turned on to pull the fourth signal V4 to the voltage BOOT and to make the transistor M3 non-conductive. Therefore, the third signal V3 and the fourth signal V4 are respectively locked to the voltage GND and the voltage BOOT, and are respectively input to the gates of the transistors M5 and M6. Conversely, when the first signal VI is low and the second signal V2 is high

Client's Docket No.: TT's Docket No:0975-A41244-TW/Final/LukeLee 1339012 When the bit is on, the transistor M1 is not turned on and the transistor M2 is turned on, so the fourth signal V4 is pulled to the voltage GND, and the transistor M3 is turned on. The transistor M3 is turned on to pull the third signal V3 to the voltage BOOT, so that the transistor M4 is not turned on. Therefore, the third signal V3 and the fourth signal V4 are respectively locked to the voltage BOOT and the voltage GND, and are respectively input to the gates of the transistors M5 and M6. In the comparator 204, the transistor M5 can be a P-type MOS field-effect transistor, the source of which is coupled to the voltage BOOT, the gate is the first input of the comparator 204, and the drain is coupled to the output. The transistor M6 can be a P-type MOSFET, the source of which is coupled to the voltage BOOT, and the gate is substantially at the second input of the comparator 204. The transistor M7 can be an N-type MOS field-effect transistor, the drain of which is coupled to the output terminal, the gate is coupled to the drain of the transistor M6, and the source is coupled to the voltage PHASE. The transistor M8 can be an N-type MOS field-effect transistor, the drain of which is coupled to the drain of the transistor M6, the gate is coupled to the output terminal, and the source is coupled to the voltage PHASE. The resistor R1 is coupled between the voltage BOOT and the output terminal. The resistor R2 is coupled between the voltage PHASE and the pole of the transistor M6. The level conversion process of the output signal OUT to the comparator 204 is as follows. When the third signal V3 is the voltage GND and the fourth signal V4 is the voltage BOOT, the transistor M5 is turned on and the transistor M6 is turned off. The transistor M5 is turned on to increase the gate voltage of the transistor M8 and turn on, and the gate voltage of the transistor M7 is lowered without being turned on. Therefore, the output signal OUT of the output is the voltage BOOT. Conversely, when the third signal V3 is the voltage BOOT and the fourth signal V4 is the voltage GND, the transistor M5 is non-conductive and electrically

Client's Docket No.: TT's Docket No: 0975-A41244-TW/Final/LukeLee 1339012 Crystal M6 is conductive. Turning on the transistor M6 causes the gate voltage of the transistor M7 to increase and conduct, and causes the gate voltage of the transistor M8 to drop without being turned on. Therefore, the output signal OUT at the output is the voltage PHASE. In the logic circuit 206, the inverters INV1, INV2, and INV3 may be coupled in series to receive the first signal VI. The inverse OR gate NR1 receives the output of the inverter INV3 and the first signal VI to generate the first pulse P1. The gate NA1 receives the output of the inverter INV3 and the first signal VI. The inverter INV4 receives the output of the inverse gate NA1 to generate a second pulse P2. FIG. 4 is a schematic diagram of signal waveforms of the voltage level shift circuit 200. The first signal VI and the second signal V2 are mutually inverted signals, and the output signal OUT and the first signal VI are in phase signals but different voltage levels. Logic circuit 206 can generate a first pulse P1 at the falling edge of the first signal VI and a second pulse P2 at the rising edge of the first signal VI. The pulse widths of the first pulse P1 and the second pulse P2 can be determined by the sum of the transfer delays of the inverters INV1, INV2, and INV3. In the accelerating circuit 208, the transistor M16 can be an N-type MOS field-effect transistor, the gate of which is used to receive the first pulse P1 and the source is coupled to the voltage GND. The transistors M13 and M14 together form a current mirror, which can be a P-type MOS field-effect transistor. When the transistor M16 receives the first pulse P1 and is turned on, the transistor M14 can apply the voltage BOOT to the comparator 204. An input. The transistor M15 can be an N-type metal oxide half field effect transistor, which is a protection circuit coupled between the transistor M16 and the current mirror to avoid the high voltage destruction acceleration circuit 208. In the acceleration circuit 210, its circuit configuration is the same as that of the acceleration circuit 208.

Client's Docket No.: TT's Docket No:0975-A41244-TW/Final/LukeLee 10 1339012 The transistor M20 can be an N-type MOSFET, the gate is used to receive the second pulse P2, and the source is coupled. Connect to voltage GND. The transistors M17 and Μ18 together form a current mirror, which can be a P-type MOS half-field effect transistor. When the transistor Μ20 receives the second pulse Ρ2 and is turned on, the transistor M17 can apply a voltage BOOT to the comparator 204. The second input. The electric crystal M19 can be an N-type gold-oxygen half field effect transistor, which is a protection circuit coupled between the transistor M20 and the current mirror to avoid the high voltage destruction acceleration circuit 210. Figure 5 is another embodiment of the present invention. The voltage level shift circuit 500 includes a comparator 502, a logic circuit 504, and an acceleration circuit 506. The comparator 502 includes an input terminal receiving the input signal IN and offsetting the voltage level of the input signal IN to generate an output signal OUT at an output. The logic circuit 504 can include a complex logic gate for receiving the input signal IN to generate the pulse signal P. The accelerating circuit 506 is coupled to the comparator 502 for receiving the pulse signal P and accelerating the comparator 502 to generate the output signal OUT during the pulse width of the pulse signal P. Figure 6 is a circuit diagram of Figure 5. The comparator 502 may include electromorphs M1, M2, M3, M4, and M5, and a resistor R1. Logic circuit 504 can include inverters INV1, INV2, INV3, and inverse OR gate NR1. The acceleration circuit 506 can include transistors M6, M7, M8, and M9. In the comparator 502, the transistor M1 can be an N-type MOS field-effect transistor, and the gate receives the input signal IN and determines whether the transistor M1 is turned on or off according to the input signal IN, and the source is coupled to the voltage GND. The transistor M2 can be a P-type MOS field-effect transistor, the source of which is coupled to the voltage

Client's Docket No.: TT's Docket No: 0975-A41244-TW/Final/LukeLee 1339012 BOOT, the drain is coupled to the output of the comparator 502. The transistor M3 can be an N-type MOS field-effect transistor, the drain of which is coupled to the output of the comparator 502, the gate coupled to the gate of the transistor M2, and the source coupled to the voltage PHASE. The resistor R1 is coupled between the voltage BOOT and the gate of the transistor M2. The transistor M4 can be an N-type gold-oxygen half-field effect transistor, constituting a protection circuit to prevent the high voltage from damaging the comparator 502. Further, during the turn-on of the transistor M1, the transistors M4 and M5 can be regarded as resistance. In the logic circuit 504, the inverters INV INV2 and INV3 can be connected in series to receive the input signal IN. The inverse gate NR1 receives the output of the inverter INV3 and the input signal IN to generate the pulse signal P. Figure 7 is a schematic diagram of the signal waveform of the voltage level shifting circuit 500. The logic circuit 504 generates a pulse signal P at the falling edge of the input signal IN. The pulse width of the pulse signal P can be determined by the sum of the transfer delays of the inverters INV1, INV2, and INV3. As can be seen from Fig. 7, the output signal OUT and the input signal IN are in phase signals but different from each other. In the accelerating circuit 506, the transistor M6 can be an N-type MOS field-effect transistor, the gate of which is used to receive the pulse signal P and is turned on, and the source is coupled to the voltage GND. The transistors M8 and M9 together form a current mirror, which can be a P-type MOS half-field effect transistor. When the transistor M6 receives the pulse signal P and is turned on, the transistor M9 can apply the voltage BOOT to the gate of the transistor M3. . The transistor M7 can be an N-type metal oxide half field effect transistor, which is a protection circuit coupled between the transistor M6 and the current mirror to avoid the high voltage breaking acceleration circuit 506.

The level conversion process of the output voltage OUT is as follows. When the input voltage IN

Client's Docket No.: TT's Docket No:0975-A41244-TW/FinaI/LukeLee 12 1339012 From low level to high level on time, transistor Ml is turned on, pulling the gate voltage of transistor M2 to voltage GND, thus letting the transistor M2 is turned on and the transistor M3 is not turned on, so that the output signal OUT is the voltage BOOT. Conversely, when the input voltage IN changes from a high level to a low level, the transistor M1 is non-conducting, and the voltage BOOT can be turned on via the resistor R1 to the gate of the transistor M3 to make the transistor M2 non-conducting, so the output signal OUT is a voltage. PHASE. While the present invention has been described above in terms of several embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A shows a voltage level shifting circuit which can be used to connect two circuits having different voltage levels; FIG. 1B is a schematic diagram of voltage level conversion; FIG. 2 is an embodiment of the present invention, including a The voltage level shift circuit 200; Fig. 3 is a circuit configuration of Fig. 2; Fig. 4 is a signal waveform diagram of Fig. 2; Fig. 5 is another embodiment of the present invention, including a voltage level shift circuit 500; Fig. 6 is a circuit diagram of Fig. 5; and Fig. 7 is a schematic diagram of a signal waveform of Fig. 5.

Client's Docket No.: TT's Docket No: 0975-A41244-TW/Final/LukeLee 1339012 [Description of main component symbols] 102 to pre-stage circuit 106 to post-stage circuit 104, 200, 500 to voltage level shift circuit 202 to positive Feedback circuits 204, 502 to comparators 206, 504 to logic circuits 208, 210, 506 to acceleration circuits M1-M20 to transistors INV1 - INV4 to inverter NR] - reverse or gate NA1 - reverse gate

Rl, R2 ~ resistance

Client^ Docket No.: TT's Docket No:0975-A41244-TW/Final/LukeLee 14

Claims (1)

1339012 Case No. 096144085 Revised October 19, 1999 Revision 10: Patent Application Range: Replacement Page 1 · A voltage level shifting circuit, comprising: a positive feedback circuit 'for receiving a first signal and a second signal Generating a third signal and a fourth signal, wherein the first and second signals are mutually inverted signals; a comparator comprising a first input receiving the third signal and a second input receiving the The fourth signal and an output end generate an output signal according to the third and fourth signals, wherein the output signal has a first level and a second level lower than the first level; a logic circuit comprising: a plurality of logic gates for receiving the first signal to generate a first pulse and a second pulse; - a first acceleration circuit, _ to the first input terminal for receiving the first pulse And accelerating the comparator to generate the output signal during the first pulse-pulse width; and - the second acceleration circuit is coupled to the second input terminal for receiving the second pulse And accelerating the comparator to generate the output signal during one of the pulse widths of the second pulse. The voltage level shifting circuit described in item 1 determines the pulse of the first and second pulses. 2. The above-mentioned logic gate further includes a complex inverter having a width. The &lt;1: pressure level shifting circuit, wherein the logic circuit generates the first punch at the falling edge of the first signal and generates the second pulse 0975-Α41244-TW/ at the rising edge of the first signal Final 1 S 15 1339012 1俾(明汽曰曰修正=4. If applying for the voltage level shift circuit of the first item, the above-mentioned positive feedback circuit, the above-mentioned first acceleration circuit, and the above second The acceleration circuit includes a protection circuit for avoiding high dust damage. 5. The voltage level shift circuit described in claim i of the patent red square, wherein the logic circuit comprises: a plurality of inverters connected in series The first signal is received to receive the first signal; and a reverse gate is configured to receive the output of the inverter and the first signal to generate the first pulse. 6. As described in claim 5 The voltage level shifting circuit, wherein the logic circuit further comprises: - an inverse Μ ' for receiving an output of the upper inverter and the first LV, and an inverter for receiving the reverse gate Output to The voltage pulse level shifting circuit of claim 1, wherein the first accelerating circuit further comprises: a transistor for receiving the first pulse, wherein the electric crystal The system is turned on according to the first pulse; a current mirror for applying the first level to the first input terminal according to the first pulse; and a protection circuit coupled between the transistor and the current mirror 8. The voltage level shifting circuit of claim 1, wherein the second accelerating circuit further comprises: S 〇 975-A41244-TW/Finall 16 1339012 • 1 η year β 丨 1 day correction Substituting a transistor for receiving the second pulse, wherein the electro-crystal system is turned on according to the second pulse; and a current mirror for applying the first level to the second input according to the second pulse And a protection circuit 'coupled between the transistor and the current mirror. 9. The voltage level shift circuit according to claim 1, wherein the positive feedback power The circuit further includes: a first transistor, a 金-type MOS field-effect transistor coupled to a reference level and having a gate receiving the first signal, wherein the first electro-crystalline system is according to the above a second transistor is turned on; a second transistor is a 金-type MOS field-effect transistor coupled to the reference level and having a gate receiving the second signal, wherein the second transistor system Turning on according to the second signal; a second transistor is a p-type MOS field effect transistor having a source coupled to the first level and coupled to a gate of the second input terminal And a fourth transistor, which is a 金-type MOS field-effect transistor having a source coupled to the first level and coupled And a gate connected to the first input end and a drain connected to the second input end. The voltage level shifting circuit of claim 9, wherein the comparator further comprises: a fifth transistor, which is a p-type MOS field effect transistor, having the first coupling One source of the level is coupled to one of the gates of the first input terminal and coupled to one of the drains of the output terminal; S 〇 975-A41244-TW/Finall 17 1339012. The 丨1丨 correction replacement page is connected to the “the second crystal, which is a galvanic half-W crystal,” which has a consumption = to the above-mentioned first-level source, pure to the second input terminal - the gate And a drain: - the seventh transistor 'is a -N type gold oxide half field effect transistor, having a transition to the above output - the immersion, _ to the above-mentioned sixth transistor, the above-mentioned infinite pole - the gate" And _to a source of the second level; an eighth transistor 'is an -N type MOSFET, having the above-mentioned immersed to the sixth transistor a gate of the output terminal and a source of the second level; a first resistor, a second resistor coupled to the first level and the output terminal, coupled to the second The level is between the above-mentioned drain of the sixth transistor. 'Used in the above-mentioned number for the above-mentioned input 11. A voltage level shifting circuit, comprising: a comparator, including a round-in terminal and an output terminal receiving an input signal, and offsetting the input signal generating end An output signal; - the logic circuit 'comprising a plurality of logic gates for receiving the input signal to generate a pulse; and the acceleration circuit' is coupled to the comparator for receiving the pulse and during the pulse-pulse width Accelerating the above comparator to generate the above output signal. 12. The voltage level shifting circuit as described in item n of the patent application scope wherein the above logic (4) further comprises a pulse width for determining the pulse S 0975-A41244-TW/Finall 18 1339012 The complex inverter. The falling edge of the voltage level shifting input signal described in the item is generated. 13. The above-mentioned logic circuit inputs the pulse in the above-mentioned input circuit. The above-mentioned acceleration circuit and the above-mentioned comparator respectively include a protection circuit to avoid being damaged by a high-level offset circuit as described in the patent application scope. 15. The voltage level shifting circuit of claim 14, wherein the logic circuit comprises a ··; and the plurality of inverters are connected in series to receive the input signal or gate. And receiving the output of the inverter and the input signal to generate the pulse. 16. The voltage level shifting circuit of claim 5, wherein the accelerating circuit further comprises: a transistor for receiving the pulse, wherein the epitaxial system is turned on according to the pulse; a current mirror, And applying a first level to the comparator according to the pulse; and a protection circuit 'coupled between the transistor and the current mirror. The voltage level shifting circuit of claim 16, wherein the comparator further comprises: a first transistor 'having a gate receiving the input signal, wherein the first electro-crystalline system is based on The input signal is turned on; S 0975-A41244-TW/Finall 19 1339012 η 修正 修正 删 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二a drain, and a gate; a third transistor having a gate coupled to the output terminal, coupled to a gate of the gate of the second transistor, and coupled to a second a source of one of the levels; and a resistor coupled between the first level and the gate of the second transistor. S 0975-A41244-TW/Finall 20