1338443 九、發明說明： 【發明所屬之技術頜域】 本發明係有關一種驅動器，特別是關於一種用於電容 ' 性負載的驅動器的輸出級電路。 【先前技術】 功率MOS和IGBT需要驅動器予以驅動。例如，在圖 1所繪示的ST公司型號L6561的功率因數校正器晶片10 的電路中，圖騰枉輸出級能夠供應和吸收大電流以驅動一 個功率MOS 12。由於功率MOS 12的閘極具有一個大的 寄生電容122，所以該圖騰柱輸出級使用一個雙極性電晶 體102，俾在其被打開後提供大電流給功率MOS 12的閘 極，進而快速地上拉該閘極上的電壓。為了讓雙極性電晶 體102可以瞬間供應大電流，需要一個高驅動能力的電壓 調節器104提供電源Vcc給雙極性電晶體102的驅動器 φ 106。雖然雙極性電晶體102可以直接從電源供應器Vp汲 取大電流，但是在其被打開的瞬間，因為其驅動器106使 用功率因數校正器10中的内部供應電壓Vcc，因此瞬間大 電流會拉低該電壓Vcc。此供應電壓Vcc是藉電壓調節器 106從電源供應器Vp所提供的系統電壓轉換產生的，用 來提供功率因數校正器10中的邏輯電路的電源，其電壓 可能比系統電壓Vp低了許多。在許多電源應用上，系統 電壓Vp是高電壓（例如12V或更高），内部供應電壓Vcc 是低電壓（例如5V或更低）。在雙極性電晶體102被打開的 1338443 瞬間，大電流的供應導致内部供應電壓Vcc立即掉低，造 成使用内部供應電壓Vcc的電路運作不穩定。另一方面， 為了降低成本以及整合電路，現在的控制電路傾向以 ' CMOS製程來實現。然而，在圖1的功率因數校正器10 ^ 中，為了提供大的電流供應能力，卻使用了雙極性電晶體 102,造成此晶片10必須以BiCMOS製程來實現。BiCMOS 技術較困難，良率較低，成本也較高，這些都是不利於晶 片設計商的缺點。 【發明内容】 本發明的目的之一，在於提出一種具有大的電流供應 能力，卻不會造成内部供應電壓瞬間下降的驅動器。 本發明的目的之一，在於提出一種適用於全CMOS實 現的驅動器的輸出級電路。 根據本發明，一種驅動器的輸出級電路使用一 PMOS φ 作為高位側電晶體，在其被打開後直接從一電源供應器汲 取一電流對該驅動器的輸出端充電，俾快速地上拉該驅動 器輸出端的電壓。一個PMOS控制電路被用來控制該 PMOS，該PMOS控制電路受一控制訊號觸發而打開該 PMOS，以及一個電壓比較器在該驅動器輸出端的電壓上 升到一臨限電壓時訊令該PMOS控制電路關閉該PMOS。 【實施方式】1338443 IX. Description of the Invention: [Technical Jaw Domain of the Invention] The present invention relates to a driver, and more particularly to an output stage circuit for a driver for a capacitive 'sexual load. [Prior Art] Power MOS and IGBT require a driver to be driven. For example, in the circuit of the power factor corrector wafer 10 of ST company model L6561 illustrated in Figure 1, the totem 枉 output stage is capable of supplying and sinking a large current to drive a power MOS 12. Since the gate of the power MOS 12 has a large parasitic capacitance 122, the totem pole output stage uses a bipolar transistor 102, which supplies a large current to the gate of the power MOS 12 after it is turned on, thereby rapidly pulling up. The voltage on the gate. In order for the bipolar transistor 102 to supply a large current instantaneously, a high drive capability voltage regulator 104 is required to supply the power source Vcc to the driver φ 106 of the bipolar transistor 102. Although the bipolar transistor 102 can draw a large current directly from the power supply Vp, at the moment it is turned on, since its driver 106 uses the internal supply voltage Vcc in the power factor corrector 10, an instantaneous large current will pull down. Voltage Vcc. This supply voltage Vcc is generated by the system voltage conversion provided by the voltage regulator 106 from the power supply Vp, and is used to supply the power of the logic circuit in the power factor corrector 10, which may be much lower than the system voltage Vp. In many power applications, the system voltage Vp is a high voltage (e.g., 12V or higher) and the internal supply voltage Vcc is a low voltage (e.g., 5V or lower). At the moment of 1338443 when the bipolar transistor 102 is turned on, the supply of a large current causes the internal supply voltage Vcc to immediately fall, resulting in unstable operation of the circuit using the internal supply voltage Vcc. On the other hand, in order to reduce costs and integrate circuits, current control circuits tend to be implemented in 'CMOS processes. However, in the power factor corrector 10^ of Fig. 1, in order to provide a large current supply capability, a bipolar transistor 102 is used, so that the wafer 10 must be implemented in a BiCMOS process. BiCMOS technology is difficult, yield is low, and cost is high, which is not good for wafer designers. SUMMARY OF THE INVENTION One object of the present invention is to provide a driver having a large current supply capability without causing an instantaneous drop in the internal supply voltage. One of the objects of the present invention is to provide an output stage circuit suitable for a driver implemented in full CMOS. According to the present invention, an output stage circuit of a driver uses a PMOS φ as a high-side transistor, and after it is turned on, draws a current from a power supply to charge the output of the driver, and quickly pulls up the output of the driver. Voltage. A PMOS control circuit is used to control the PMOS, the PMOS control circuit is triggered by a control signal to turn on the PMOS, and a voltage comparator stops the PMOS control circuit when the voltage at the output of the driver rises to a threshold voltage. The PMOS. [Embodiment]
圖2係使用PMOS 14的圖騰柱輸出級驅動功率MOS 1338443 12的示意圖。由於PMOS的特性是在閘極·源極電壓低於 一臨界電壓時截止，而在閘極_源極電壓大於該臨界電壓時 導通’因此驅動PMOS 14的PMOS 142可以直接連接系統 電壓VP ’不需要使用内部供應電壓。如此一來，不但能 快速地切換PMOS 14,而且不論是在打開或關閉PMOS 14 的瞬間，都不會影響到内部供應電壓。 圖3係根據本發明的一個驅動器的輸出級。在此實施 鲁例中’高位側電晶體14使用PMOS，低位側電晶體丨6使 用NMOS，控制訊號產生器20根據輸入訊號I產生控制訊 號II和12，分別用來控制PMOS 14和NMOS 16。控制訊 號12直接用來切換NMOS 16。PMOS控制電路30使用系 統電壓Vp推動’其受控制訊號π觸發而以訊號a打開 PMOS 14。由於推動PMOS 14的PMOS控制電路30是直 接連接電源供應盗Vp，而電源供應器Vp的内阻低，所以 在PMOS 14突然汲取大電流時也不會影響提供給其他控 φ 制電路使用的内部供應電壓。在PMOS 14被打開後，其直 接從電源供應器Vp没取大電流對功率m〇s 12的閘極充 電。電壓比較器40監視驅動器輸出端的電壓v〇，在電壓 Vo上升到臨限電壓VSET時，電壓比較器4〇藉訊號Βί及 B2訊令PMOS控制電路30關閉PMOS 14。臨限電壓VSET 是一個預先設定鬲於打開功率M〇S 12所需的電壓，可以 調整來決定PMOS 14被關閉的工作點。在NM〇s丨6被打 開後，從功率MOS 12的閘極釋放電荷到地端GND。 較佳者，在驅動器輸出端v〇連接—個漏電用的電阻 1338443 R〇，讓電壓Vo在PMOS 14和NMOS 16都不導通的期間 緩慢下降。在其他實施例中，也可以單獨讓NMOS 16本 身的漏電流緩慢釋放功率MOS 12閘極上的電荷。 ' 圖4是一個控制圖3的輸出級的方法。輸入訊號I是 一個切換式訊號，控制訊號產生器20從其產生彼此不重 疊的控制訊號II和12。控制訊號II的上升緣觸發PMOS 控制電路30的輸出訊號A，進而打開PMOS 14，上拉輸 出端電壓Vo。一旦電壓Vo上升達臨限電壓VSET，觸發電 ® 壓比較器40的輸出訊號B1和B2，進而使PMOS控制電 路30關閉PMOS 14。在PMOS 14被關閉以後，NMOS 16 尚未被打開以前，這段期間的電壓Vo因為漏電而緩慢下 降。直到控制訊號12的上升緣被觸發，NMOS 16被打開 ，電壓Vo快速下降到零。待下一週期控制訊號II的上升 緣再度被觸發，重覆上述的過程。如訊號A所顯示的，在 一個切換週期中，PMOS 14只有在剛被打開後的一段很短 φ 的期間導通，這段期間供應大電流對功率MOS 12的閘極 充電，快速地上拉其閘極電壓而打開功率MOS 12。PMOS 14在大部份時間都是關閉的，因此比較省電，也避免短路 發生的機會。在PMOS 14被關閉以後，NMOS 16尚未被 打開以前，功率MOS 12靠著閘極上的電壓Vo保持其導 通。 圖5是圖3的輸出級的一個實施例，其中，電晶體 P1-P3是PMOS，電晶體N1-N6和電晶體16是NMOS。以 圖4所示的訊號說明其工作方式，輸入訊號I是一個切換 1338443 式訊號，控制訊號產生器20從其產生控制訊號II和12， 其内的兩串邏輯閘使控制訊號II和12不重疊。在控制訊 號Π低準位的期間，電晶體N1不導通，因此訊號A維持 在高準位，PMOS 14是關閉的。在控制訊號12高準位的 期間，NMOS 16 —直維持導通的狀態，因此電壓Vo是低 準位，功率MOS 12是關閉的。電晶體N4、P3、N5及N6 皆不導通，電流源306及406分別對節點402及404充電 ，因此訊號B1及B2皆在高準位，電晶體P1不導通，電 • 晶體N2導通。當輸入訊號I由低準位切換到高準位時， 控制訊號12先切換到低準位把NMOS 16關閉，然後控制 訊號II再從低準位切換到高準位，因此確保PMOS 14和 ,NMOS 16不會同時導通。在控制訊號II切換到高準位以 後，電晶體N1被打開，因為電晶體N2是導通的，所以形 成一條放電路徑將節點302的電荷釋放到地端，造成訊號 A切換到低準位，於是打開PMOS 14，系統電源Vp經 φ PMOS 14對功率MOS 12的閘極充電，導致電壓Vo上升 。一旦電壓Vo上升到臨限電壓VSET，電晶體N4、P3、 N5、N6導通，節點402和404上的電壓被拉低，於是訊 號B1和B2切換到低準位，進而關閉電晶體N2，先前的 放電路徑被切斷，同時電晶體P1也被打開，節點302再 度被充電，訊號A因而切換回到高準位而關閉PMOS 14 。由於NMOS 16尚未被打開，因此靠著功率MOS 12的 寄生電容122維持電壓Vo，但是因為電阻Ro的漏電而緩 慢下降。當輸入訊號I再由高準位切換回到低準位，控制 1338443 訊號II先切換到低準位，關閉電晶體N1，確保節點八處 沒有放電路徑，PMOS 14不會被打開，然後控制訊號12 由低準位切換到高準位，打開NMOS 16，電壓v〇迅速放 電到接地電位，同時也使得電晶體N4、P3、N5和N6關 閉’節點402和404上的電壓被充電到與系統電壓vp相 同，訊號Bl、B2回到高準位，又關閉電晶體P1，打開電 晶體N2，等待下一次輸入訊號〗的轉態。 在電壓Vo高於臨限電壓VsET時，PM〇S 14是不導通 的’因此具有自動煞車的保護功能，即使控制電路發生狀 況，也不會持續對功率MOS 12充電而造成元件燒毀。而 PMOS 14和NMOS 16不會同時導通，因此不會發生電流 從電源供應器Vp經輸出級直接流到地端GND，不但節省 電源，也避免短路的可能性。 圖6是圖3的輸出級的第二個實施例，其中，在圖5 的電流源304、306及406位置上的元件分別改用PMOS φ 開關 314、316、412。 圖7是圖3的輸出級的第三個實施例。如果系統電壓 Vp高於控制電路（邏輯閘）的操作電壓Vcc，則使用準位平 移電路50來平移訊號A的高準位，使其足以關閉PMOS 14 〇 圖8是圖3的輸出級的第四個實施例，以電流源匕及 NMOS電晶體N7、N8組成之差動放大電路60做為電壓 比較器。當輸入訊號I低時，控制訊號產生器產生控制訊 號Π低、12高’電晶體N7 OFF且電晶體16導通，輸出 1338443 電壓Vo低，使得電晶體N8也OFF，準位平移電路50及 電流源Is使得訊號B1和A等於系統電源vP，電晶體14 off。當輸入訊號I由低轉高時，控制訊號^高（乂叫且12 低(0V) ’電晶體Ν7導通’節點Α的電壓被快速地下拉， 電晶體14導通’使得輸出電壓v〇上升，電晶體N8導通 。隨著輸出電壓Vo的上升，流經電晶體N8的電流越來越 大’當流經電晶體N8的電流大於電流源ls提供的電流後 籲，節點B1的電壓會從系統電壓vP開始往下降，因而逐漸 導通了電晶體P1。輸出電壓Vo上升到一定程度後，由電 晶體P1流出的電流將大於原本流經電晶體N7的電流，且 把節點A的電壓重新提升回系統電源Vp的準位，此時電 晶體14 OFF ’且電晶體16仍然OFF，輸出電壓Vo停止 上升，維持在高準位。當輸入訊號I由高轉回低準位的時 候’控制訊號II低，12上升到高（Vcc)，電晶體N7 OFF 且電晶體16導通，輸出電壓Vo降為〇伏特。 φ 圖9是圖3的輸出級的第五個實施例，將圖8中的電 流源Is以電晶體P4、P5、N9及R2實現，此外，由於當 輸出電壓Vo維持在定電壓時，電晶體N7、N8仍會消耗 電流’因此本實施例更設置一個脈衝產生器75及電晶體 N10、N1卜當控制訊號Π由低轉高時，脈衝產生器75發 出一個固定時間寬的訊號，將電晶體N10及Nil導通，使 電晶體N7及N8運作如圖8之說明，經一段時間後，再把 電晶體N10及N11戴止，以降低電流損耗。 由於輸出級電路全部使用MOS元件，因此驅動器可 1338443 以使用CMOS製程來實現。又 使用_，所以不需要高驅動高”電晶體 源’整體電路也較穩定。 、"調㈣提供電 的二例所顯示的’使用本發明的輸出級電路 的可以應用在推動各種電容性的負載上，特別適合 應用在切換式電__，以得職成本、不影響内部供 應電壓、省電及自動保護功能的好處。 【圖式簡單說明】 圖1顯示一個習知的驅動器； 圖2係使用PMOS的圖騰柱輸出級驅動功率M〇s的 不意圖， 圖3係根據本發明的一個驅動器的輸出級； 圖4是一個控制圖3的輸出級的方法； 圖5是圖3的輸出級的一個實施例； • 圖6是圖3的輸出級的第二個實施例； 圖7是圖3的輸出級的第三個實施例； 圖8是圖3的輸出級的第四個實施例；以及 圖9是圖3的輸出級的第五個實施例。 【主要元件符號說明】 10 功率因數校正器 102 雙極性電晶體 104 電壓調節器 13384432 is a schematic diagram of a totem pole output stage drive power MOS 1338443 12 using PMOS 14. Since the characteristics of the PMOS are turned off when the gate/source voltage is lower than a threshold voltage, and turned on when the gate_source voltage is greater than the threshold voltage, the PMOS 142 driving the PMOS 14 can directly connect the system voltage VP ' An internal supply voltage is required. In this way, not only can the PMOS 14 be switched quickly, but the internal supply voltage is not affected at the moment when the PMOS 14 is turned on or off. Figure 3 is an output stage of a drive in accordance with the present invention. In the embodiment, the high side transistor 14 uses a PMOS, and the low side transistor 丨 6 uses an NMOS. The control signal generator 20 generates control signals II and 12 based on the input signal I for controlling the PMOS 14 and the NMOS 16, respectively. Control signal 12 is used directly to switch NMOS 16. The PMOS control circuit 30 uses the system voltage Vp to push 'which is triggered by the control signal π to turn on the PMOS 14 with the signal a. Since the PMOS control circuit 30 that drives the PMOS 14 is directly connected to the power supply thief Vp, and the internal resistance of the power supply Vp is low, the PMOS 14 suddenly draws a large current without affecting the internals provided to other control φ circuits. Supply voltage. After the PMOS 14 is turned on, it directly charges the gate of the power m〇s 12 from the power supply Vp without taking a large current. The voltage comparator 40 monitors the voltage v〇 at the output of the driver. When the voltage Vo rises to the threshold voltage VSET, the voltage comparator 4 signals the PMOS control circuit 30 to turn off the PMOS 14 by the signals Βί and B2. The threshold voltage VSET is a voltage that is preset to the turn-on power M〇S 12 and can be adjusted to determine the operating point at which the PMOS 14 is turned off. After NM〇s丨6 is turned on, the charge is discharged from the gate of the power MOS 12 to the ground GND. Preferably, a resistor 1338443 R〇 for leakage is connected to the output of the driver, so that the voltage Vo is slowly lowered while the PMOS 14 and the NMOS 16 are not conducting. In other embodiments, the leakage current of the NMOS 16 itself may be separately released to slowly release the charge on the gate of the power MOS 12. Figure 4 is a method of controlling the output stage of Figure 3. The input signal I is a switching signal from which the control signal generator 20 generates control signals II and 12 which do not overlap each other. The rising edge of the control signal II triggers the output signal A of the PMOS control circuit 30, thereby turning on the PMOS 14, pulling up the output terminal voltage Vo. Once the voltage Vo rises to the threshold voltage VSET, the output signals B1 and B2 of the voltage comparator 40 are triggered to cause the PMOS control circuit 30 to turn off the PMOS 14. After the PMOS 14 is turned off, before the NMOS 16 has not been turned on, the voltage Vo during this period is slowly lowered due to leakage. Until the rising edge of the control signal 12 is triggered, the NMOS 16 is turned on and the voltage Vo drops rapidly to zero. The rising edge of the next cycle control signal II is triggered again, repeating the above process. As shown by signal A, during a switching cycle, the PMOS 14 is turned on only for a short period of φ immediately after being turned on. During this period, a large current is supplied to charge the gate of the power MOS 12, and the gate is quickly pulled up. The power MOS 12 is turned on with a pole voltage. The PMOS 14 is turned off most of the time, so it saves power and avoids the chance of a short circuit. After the PMOS 14 is turned off, before the NMOS 16 is turned on, the power MOS 12 is kept turned on by the voltage Vo on the gate. Figure 5 is an embodiment of the output stage of Figure 3, wherein transistors P1-P3 are PMOS, transistors N1-N6 and transistor 16 are NMOS. The signal shown in FIG. 4 illustrates its working mode. The input signal I is a switching 1338443 type signal, and the control signal generator 20 generates control signals II and 12 therefrom, and the two strings of logic gates therein make the control signals II and 12 not overlapping. During the period when the control signal is low, the transistor N1 is not turned on, so the signal A is maintained at a high level and the PMOS 14 is turned off. During the high level of the control signal 12, the NMOS 16 is kept in an on state, so the voltage Vo is at a low level and the power MOS 12 is turned off. The transistors N4, P3, N5 and N6 are not turned on, and the current sources 306 and 406 respectively charge the nodes 402 and 404. Therefore, the signals B1 and B2 are at a high level, the transistor P1 is not turned on, and the transistor N2 is turned on. When the input signal I is switched from the low level to the high level, the control signal 12 is first switched to the low level to turn off the NMOS 16 and then the control signal II is switched from the low level to the high level, thus ensuring the PMOS 14 and The NMOS 16 does not turn on at the same time. After the control signal II is switched to the high level, the transistor N1 is turned on, because the transistor N2 is turned on, so that a discharge path is formed to discharge the charge of the node 302 to the ground, causing the signal A to switch to the low level, so that Turning on the PMOS 14, the system power supply Vp charges the gate of the power MOS 12 via the φ PMOS 14, causing the voltage Vo to rise. Once the voltage Vo rises to the threshold voltage VSET, the transistors N4, P3, N5, N6 are turned on, the voltages on the nodes 402 and 404 are pulled low, and the signals B1 and B2 are switched to the low level, thereby turning off the transistor N2, previously The discharge path is cut off, while transistor P1 is also turned on, node 302 is again charged, and signal A thus switches back to the high level to turn off PMOS 14. Since the NMOS 16 has not been turned on, the voltage Vo is maintained by the parasitic capacitance 122 of the power MOS 12, but is slowly lowered due to the leakage of the resistor Ro. When the input signal I is switched from the high level to the low level, the control 1338443 signal II first switches to the low level, turns off the transistor N1, ensures that there is no discharge path at the node eight, the PMOS 14 will not be turned on, and then the control signal 12 Switch from low level to high level, turn on NMOS 16, voltage v〇 is quickly discharged to ground potential, and also make transistors N4, P3, N5 and N6 off 'the voltages on nodes 402 and 404 are charged to the system The voltage vp is the same, the signals B1 and B2 return to the high level, and the transistor P1 is turned off, and the transistor N2 is turned on, waiting for the next state of the input signal. When the voltage Vo is higher than the threshold voltage VsET, the PM 〇S 14 is non-conducting. Therefore, it has a protection function of automatic braking, and even if the control circuit is in a state, the power MOS 12 is not continuously charged and the component is burnt. The PMOS 14 and the NMOS 16 are not turned on at the same time, so no current will flow directly from the power supply Vp through the output stage to the ground GND, which not only saves power but also avoids the possibility of short circuit. 6 is a second embodiment of the output stage of FIG. 3 in which the components at the current sources 304, 306, and 406 of FIG. 5 are each multiplexed with PMOS φ switches 314, 316, 412. Figure 7 is a third embodiment of the output stage of Figure 3. If the system voltage Vp is higher than the operating voltage Vcc of the control circuit (logic gate), the level shifting circuit 50 is used to translate the high level of the signal A to be sufficient to turn off the PMOS 14 . FIG. 8 is the output stage of FIG. In the four embodiments, the differential amplifier circuit 60 composed of a current source 匕 and NMOS transistors N7 and N8 is used as a voltage comparator. When the input signal I is low, the control signal generator generates a control signal Π low, 12 high 'transistor N7 OFF and the transistor 16 is turned on, and the output 1338443 voltage Vo is low, so that the transistor N8 is also OFF, the level shifting circuit 50 and the current The source Is causes the signals B1 and A to be equal to the system power supply vP and the transistor 14 off. When the input signal I goes from low to high, the control signal ^ high (howling and 12 low (0V) 'the transistor 导7 is turned on' the voltage of the node Α is quickly pulled down, and the transistor 14 is turned on' causes the output voltage v 〇 to rise, The transistor N8 is turned on. As the output voltage Vo rises, the current flowing through the transistor N8 becomes larger and larger. 'When the current flowing through the transistor N8 is greater than the current supplied by the current source ls, the voltage of the node B1 will be from the system. The voltage vP starts to fall, and thus the transistor P1 is gradually turned on. After the output voltage Vo rises to a certain extent, the current flowing from the transistor P1 will be larger than the current flowing through the transistor N7, and the voltage of the node A is raised again. When the system power supply Vp is at the level, the transistor 14 is OFF' and the transistor 16 is still OFF, the output voltage Vo stops rising and remains at the high level. When the input signal I turns from high to low level, the control signal II Low, 12 rises to high (Vcc), transistor N7 OFF and transistor 16 turns on, output voltage Vo drops to 〇V. φ Figure 9 is a fifth embodiment of the output stage of Figure 3, the current in Figure 8. Source Is is based on transistors P4, P5, N9 and R2 In addition, since the transistors N7 and N8 still consume current when the output voltage Vo is maintained at a constant voltage, the present embodiment further sets a pulse generator 75 and transistors N10 and N1 to control the signal from low to high. When the pulse generator 75 sends a fixed time wide signal, the transistors N10 and Nil are turned on, so that the transistors N7 and N8 operate as illustrated in FIG. 8. After a period of time, the transistors N10 and N11 are then worn. In order to reduce the current loss, since the output stage circuit uses all MOS components, the driver can be implemented in CMOS process with 1388443. In addition, _ is used, so the high-drive high-transistor source is not required. The overall circuit is also stable. (4) The two examples of providing electricity show that 'the output stage circuit using the present invention can be applied to push various capacitive loads, and is particularly suitable for application in switched mode __, to obtain the service cost, does not affect the internal supply voltage, Benefits of power saving and automatic protection function [Simplified diagram] Figure 1 shows a conventional driver; Figure 2 shows the use of PMOS totem pole output stage drive power M〇s 3 is an output stage of a driver in accordance with the present invention; FIG. 4 is a method of controlling the output stage of FIG. 3; FIG. 5 is an embodiment of the output stage of FIG. 3; A second embodiment of the output stage of FIG. 3; FIG. 8 is a fourth embodiment of the output stage of FIG. 3; and FIG. 9 is a fifth of the output stage of FIG. Embodiments [Description of main component symbols] 10 Power factor corrector 102 Bipolar transistor 104 Voltage regulator 1338443
106 驅動器 12 功率MOS 122 寄生電容 14 PMOS 142 PMOS 16 NMOS 20 控制訊號產生器 30 PMOS控制電路 302 節點 304 電流源 306 電流源 314 PMOS開關 316 PMOS開關 40 電壓比較器 402 節點 404 節點 406 電流源 412 PMOS開關 50 準位平移電路 60 差動放大電路 70 PMOS控制電路 75 脈衝產生器106 Driver 12 Power MOS 122 Parasitic Capacitor 14 PMOS 142 PMOS 16 NMOS 20 Control Signal Generator 30 PMOS Control Circuit 302 Node 304 Current Source 306 Current Source 314 PMOS Switch 316 PMOS Switch 40 Voltage Comparator 402 Node 404 Node 406 Current Source 412 PMOS Switch 50 level shifting circuit 60 differential amplifying circuit 70 PMOS control circuit 75 pulse generator