TWI336856B - Method and system of logically-addressed file storage - Google Patents

Description

1336856 IX. Description of the Invention: [Technical Field of the Invention] This application relates to the operation of a reprogrammable non-volatile memory system, such as a semi-guided flash memory, and more specifically to such memory. Data management in the body. All patents, patent applications, papers, and other publications, documents, and objects referred to herein are hereby incorporated by reference in their entirety for all purposes. [Prior Art]

The early generation of commercial flash memory system 鲚 姐 姐 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 That is 5 12 bytes. An extra ancestor θ, the number of extra-greedy greedy (for example, 丨6 bytes) is also usually included in each group φ w ~ + a you can edit the group to store an error correction code and possible Other management data related to the memory unit group of the user data and/or the virgin gray technique that only π han / : 3⁄4 re-stored data. The memory unit in each such group can be the smallest number of memory cells to be erased, and the memory unit of the data unit and any management data contained in the unit is erased. The effective number. Examples of this type of memory system are described in U.S. Patent Nos. 5,602,987 and 6,426,893. Flash Memory - Features 'The memory cells need to be erased before using the data to reprogram them. Flash memory systems are most commonly provided in the form of a memory card or flash drive that can be removably connected to various hosts (e.g., a personal computer, a camera, or the like), but can also be embedded in such a host system. When writing data to the memory, the host typically assigns a unique logical address to the segment, cluster, or other data unit within the continuous virtual address space of the 117059.doc J-3〇«56 memory system. . Similar to a disk operating system (D〇s), the host writes data to and reads data from the address in the logical address space of the memory system. A controller within the memory system translates the logical address received from the host into the physical address of the actual stored data in the memory array and then tracks the address translation. The data storage capacity of the memory system is at least as large as the amount of data that can be addressed within the entire logical address space defined for the memory system. In a later generation of flash memory systems, the size of the erase unit is increased to a memory cell block sufficient to store one of the plurality of data sectors. Even if the host system to which the memory system is connected can be programmed and read in a minimum unit (e.g., a segment), a large number of segments are still stored in a single erase unit of the flash memory. Certain data segments within a block typically become expired due to host updates or replacement of logical data segments. Since the entire block must be erased before any material stored in the block can be overwritten, the new or updated data is typically stored in another block that has been erased and has the remaining capacity for that data. This program causes the original block to have expired data that occupies valuable space in the memory, but if any valid data remains in the block, the block cannot be erased. Therefore, in order to make better use of the storage capacity of the memory, the data is usually merged or collected by copying the data of the effective partial block number to an erased block, so that the data can be erased therefrom. Wait for the (etc.) block of the data and re-use its entire data capacity. It is also necessary to copy the data in the order of the logical addresses of the data sections in a block in order to aggregate the data areas 117059.doc 1336856 segment. This will increase the speed of reading data and transferring the read data to the host. . If such data replication occurs frequently, it may degrade the operational performance of the memory system. This particularly affects the operation of the memory system in the case where the storage capacity of the memory is slightly larger than the amount of data that can be addressed by the host through the logical address space of the system (i.e., a typical case). ^ In this case, data consolidation or collection may be required before the host stylized command can be executed. This will increase the stylization time. The size of the block is increasing in the latter generation of memory systems to increase the number of bits of data that can be stored in a given semiconductor region. Blocks storing 256 data segments and more data segments are becoming commonplace. In addition, two, four or more blocks of different arrays or sub-arrays are often logically linked together into meta-blocks to increase the parallelism of data stylization and reading. The challenge with such large capacity units of operation is how to operate it efficiently. A common prior interface between a host and a memory system uses a logical addressing scheme for the data segments stored by the memory. However, when the host broadcast is mapped to a logical address space, the host file often becomes logically fragmented, whereby it may be widely distributed throughout the memory array. This makes it more difficult to manage the memory array because the block in the memory array is part of the archive and therefore often contains one of the valid data disk expiration data. In order to recover the space occupied by expired data, it may be necessary to copy a large amount of valid data. SUMMARY OF THE INVENTION A memory system in accordance with an embodiment of the present invention receives data from a host using a logical 117059.doc 1336856 addressing scheme. The host first maps the host to the logical address space. Then the host provides a signal to the memory system that indicates the profile configured for a particular host data segment, and then, when the memory: the system receives the host data segment, the memory system uses its previous The received configuration information determines the storage of the host data section. Specifically, the memory system places segments from the same host file in the same metablock of the memory array. In this way, the audit: can occupy multiple metablocks. The host also sends a time when the end of a host ^ has been sent so that the memory system can close the reference and perform an operation to store the file more efficiently. A host is used to notify a memory system of the configuration of the data section. The notification scheme uses the directory and the FAT section so that the strictness of the notification scheme is compatible with the previous logical interface. In particular, the beginning of a new building is identified by a directory section that indicates the first cluster of files: then, when the section of the cluster is sent, the sections are stored in a new Inside the block. Any cluster that is logically contiguous with the previous receive cluster can be assumed to be from the same scale as the previous cluster. When a host sends a new cluster that does not come from the same slot as the second pre-cluster, the host will indicate that the new cluster is from a new host (not previously sent from any of the sections) so there is no The metablock is opened for the file, then the host sends a _ directory section to indicate - the beginning of the new standard. =, the cluster is from - the slot is opened (previously sent from this broadcast) ^ ^ stored in one Or a plurality of metablocks are used for the file), then the host sends a FAT item - the fat section is used for the previous bundle 117059.doc 1336856 set of the open file (which includes the indicator pointing to the new cluster). In addition to sending a signal to indicate "in addition to the information" the host can send - FAT to indicate the end of a file. Such a FAT section contains the item "for the last cluster of the file" which refers to the end of the case. Different from the line scheme of storing FAT and directory information in non-volatile memory, this scheme sends configuration information before sending the host data referenced by the configuration information. Moreover, most of the previous schemes do not provide the main memory system. The configuration information sent by the machine is used as the fat and directory section. 6 The system can use the file configuration information provided by the host to keep the data of a specific host together. Even when the host file is mapped to a logic by the host. The address range may be logically fragmented, but the memory system may use information about the mapping to store the data of the first floor in a dedicated block. Thus, when the host indicates - the beginning of the new case A new block will be opened. Any data from the block will then be stored in the same metablock. If necessary, additional metablocks will be opened for the file. Finally, the host indicates the file. At the end, or the memory system closes the file for some other reason. At this point, if there is a metablock that only partially fills the data from the host file, then the residual data can be combined from a shared area. Similar residual data for other files in the block. If the host deletes the file (indicated by a directory section or by another means), the file can be easily restored. The occupied space rarely copies valid data, because most of the files are in a dedicated metablock. A notification scheme can also allow a host to notify a memory system that the power is about to be removed, so that the memory The system can be prepared for power loss. H7059.doc ^36856 (9) by storing any material in volatile memory to non-volatile memory). A notification scheme may also allow a host to notify a memory that "the time when the power will be maintained, so that the memory system can perform housekeeping operations, such as a recycling operation." [Embodiment] Flash Memory Overview 'Refer to Figures 1 to 7 A typical operation of a current flash memory system and a host device. That is, various aspects of the present invention can be implemented in the system. One of the host systems of FIG. 1 stores data in a flash memory 2 and from The data is "despite the fact that the flash memory can be embedded in the host system as a more popular form of adopting - the card is removably connected to the host through the matching portions 3 and 4 of the mechanical connector. There are many different commercial flash memory cards currently available, examples are c〇mpactFiash (CF), MultiMediaCard (MMC), Secure Digital (SD), Memory Stick, Smart Media and TransFlash cards, although each of these cards Card Base • Its standardized specifications have a unique mechanical and/or electrical interface, but the flash memory included in each card is very similar. These cards are available from • SanDisk CorPoration (ie, the transferee of the present invention). 8 grabs 4 also... The trademark provides a U flash drive, and the material drive is a small-sized hand-held memory system with a universal serial bus (USB). The plug is connected to the host by being plugged into the USB socket of the host. Each of the memory card and the flash drive includes a controller that interfaces with the host and controls the operation of the flash memory therein. The host system of memory cards and flash drives is quite different. 117059.doc 丄336856 It includes personal computer (pc) laptops and other portable computers, cellular phones, personal digital assistants (PDAs), Digital still camera, digital camera and portable audio player. The host computer usually contains one built-in socket for one or more types of 6 memory cards or flash drives, but some sockets require a memory card to be inserted. As long as the memory 2 is involved, the host system 1 of Figure 1 can be considered to have two * main parts, which are composed of a combination of circuit and software. It is an application φ part 5 and interface memory 2 The drive portion 6. For example, in a personal computer, the application portion 5 can include a processor that runs character processing, graphics, control, or other popular application software. In a camera, a cellular phone, or primarily dedicated to perform a single function. In other host systems of the set, the application part 5 includes software for operating a camera to take and store photos, operating a cellular phone to make and receive calls, and the like. The memory system 2 of FIG. 1 includes a flash memory 7 and a circuit. 8. Both are connected to the host to which the card is connected for transferring data back and forth and controlling the memory 7. • The controller 8 generally logically addresses the data used by the host during data programming and reading. The physical address between the memory 7 is converted. Referring to Fig. 2, a circuit of a typical 'flash" memory system which can be used as one of the non-volatile memory 2 of the figure 2 will be described. The system controller is usually implemented in a single

Or a plurality of integrated circuit memory chips, a single such memory crystal on the integrated circuit chip 11, connected to one or more of the devices f; 15 as shown in FIG. The particular bus bar 13 shown includes a separate conductor set 17 for carrying data, and a set 21 of state signals. A group 19 for memory addresses and for controlling and or a single conductor set can be time-divided between the three functions 117059.doc 1336856. In addition, (iv) its (iv) unified bus configuration, for example, the title of the application filed on August 9, 2004, the ring bus structure and its use in the flash memory system (US Patent Application No.) Ring busbar as described in 1〇/915,〇39. A typical controller die 11 has its own internal bus bar 23 that interfaces through the w-plane circuit 25 to the system bus bar 13 ^ which is typically connected to the main function of the bus bar - a processor 27 (eg, a micro a processor or microcontroller), a read only memory (ROM) 29 containing code to initialize ("boot) the system, read only memory (RAM) 3 1, which is mainly used to buffer the δ The data transmitted between the body and a host, and circuitry 33, which calculates and checks an error correction code (ECC) for data being passed through the controller between the memory and the host. The controller bus bar 23 is coupled to a host system via circuit 35. This is accomplished by the external contacts 37 of the card as part of the connector 4, in the case where the system of Fig. 2 is included in a memory. One clock 39 is connected to and used by the components of the other components of the controller. The memory chip 15 and any other components connected to the system bus 13 generally comprise a memory cell array organized into a plurality of sub-arrays or planes 'two such planes 4 and 43 for simplicity, but may be Alternative such planes such as four or eight are used instead. Alternatively, the memory cell array of the wafer 15 may not be divided into planes. However, when such division is made, each plane has its own row control circuits 45 and 47 which are independently operable with each other. The circuits 45 and 47 receive the addresses of their individual memory cell arrays from the address portion i9 of the system bus 13 and decode them to address the 117059.doc -12- 1336856 bit lines 49 and 51. Specific one or more. In response to the address received at the address pool 9, the word line 5 3 is addressed by the column control circuit $5. Source voltage control circuits 57 and 59 are also coupled to the individual planes, as are p well voltage control circuits 61 and 63. If the memory chip 15 has a single array of memory cells and if two or more such wafers are present in the system, an array of wafers can be operated similar to a plane or sub-array within the multi-planar wafer. The data is transmitted by entering and exiting the planes 41 and 43 through the individual data input/output circuits 65 and 67 of the data portion 17 of the connection system bus 13. The circuits 65 and 67 provide lines 69 and 71 for connecting to the planes through the individual row control circuits 45 and 47, while staging the data into the memory cells and memory cells from their individual planes. Read the data. Although the controller 11 controls the operation of the memory chip 15 to program data, read data, erase, and participate in various housekeeping transactions, each memory chip also includes a certain control circuit that is executed from the controller 1 Command to perform such a function. The interface circuit 73 is connected to the control and status portion 21 of the system bus. Commands from the controller are provided to a state machine 75, which then provides specific control of other circuits to execute the commands. Control lines 77 through 81 use these other circuits to connect state machine 75' as shown in FIG. The status information from the state machine 75 is transmitted through the line 83 to the interface 73 for transmission to the controller 11 through the bus bar portion 21. It is currently preferred to use one of the NAND architectures of the memory cell arrays 41 and 43, although other architectures such as the NOR architecture may be used instead. References US Patent Nos. 5,570,315, 5,774,397, 6,046,935 •13·117059.doc

NAND flash memory examples and their actions are known in U.S. Patent Nos. 1,336,856, 6, 373, 746, issued to s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s The operation of a part of the system.

3 is a circuit diagram illustrating an exemplary nanD array, which is part of the memory cell array 41 of the memory system of FIG. 2, "providing a large number of global bit lines". For simplicity of explanation, only four such devices are shown in FIG. Lines 91 to 94. A plurality of serially connected & early memory strings 97 to 104 are connected between one of the bit lines and a reference potential. Using the memory cell string 99 as a representative, a plurality of charge storage memory cells 107 to 〇1 are connected in series to the selection transistors 111 and 112 at either end of the string. When a string of selected transistors is rendered conductive, the string is connected between its bit line and the reference potential. Therefore, one memory unit is programmed or read at a time. The word lines 115 to 117 of FIG. 3 individually extend across the charge storage elements of a memory cell within each of the plurality of memory cell strings, and the gates 119 and 120 control the ends of the strings. Select the state of the transistor. The memory cell strings of the shared common character and the control gate lines 115 to 120 are erased together to erase one of the memory cell blocks 123. This unit block contains the minimum number of units that can be erased by the secondary entity. A list of memory cells, i.e., those memory cells along one of the word lines 11 5 to 11 8 , is programmed once. In general, the columns of a NAND array are programmed in a predetermined order, in this case from a list of word lines 118 that are closest to the end of the string connected to ground or another common potential. Start. The sequence of memory cells along sub-line 117 is then programmed to do so and throughout block 123. -14· 117059.doc

1336856 Finally stylized along the word line 丨丨5 column. A second block 125 is similar, and its memory cell string is connected to the same global bit line as the strings in the first block 123.

The characters of the group it and the control gate line 4 and the control gate lines are driven to their proper operating voltage by the control circuit 55. If there are multiple planes or sub-arrays in the system (e.g., plane (4) of Figure 2), then a memory architecture uses a common word line extending between them. Or there may be more than two planes or sub-arrays that share a common word line. In other memory architectures, the word lines of individual planes or sub-arrays are driven separately. The memory system is operable to store more than two (four) charge levels in each charge storage element or domain, as described in several patents and published applications of the above-referenced NAND patents, whereby Multiple data bits are stored in each component. The charge storage element of the memory cell is the most common conductive floating (four), but is alternatively a non-conductive dielectric charge-acquisition material, as described in US Patent Application Publication No. 2003/〇1〇9〇93 wide

Figure 4 conceptually illustrates the organization of one of the flash memory cell arrays 7 (Figure 1) used as an example. The four planes or sub-arrays 13 1 to 丨 3 4 of the memory cells may be located in one A single integrated memory cell is placed on two wafers (two planes of the planes on each wafer) or on four separate wafers. The specific configuration is not critical to the following discussion. Of course, other numbers A plane (e.g., i, 2, 8, 16 or more) may be present in a system. The planes are each divided into quarters of the 5th memory unit located in the individual planes Hi to 13 4 (as shown in the figure). 4 rectangles are shown), such as blocks 137 I38, I39, and 140. There may be tens or hundreds of 117059.doc 15 1336856 blocks in each plane. As described above, the blocks of the memory cells are wiped. In addition to the unit, the smallest number of memory cells can be physically erased together. However, to increase the parallelism, the blocks are operated in a larger metablock unit. One block from each plane is logically linked. Together to form a one-dimensional block. Show four areas Blocks 137 through 140 form a metablock 141. All of the cells within the unary block are typically erased together. The blocks used to form the unary block need not be limited to the same relative position within their individual planes, as Blocks 145 through 148 are shown in one of the second metablocks 143. Although it is generally preferred to extend the metablocks across all planes, in order to achieve higher system performance, the operational memory system , enabling it to dynamically form metablocks from any or all of the ''two or two blocks in different planes. This allows the size of the metablocks to be more closely matched in a stylized operation for The number of stored data. The individual blocks are sequentially divided into a plurality of pages of memory cells for operational purposes as shown in FIG. 5. For example, the memory cells of each of the blocks 131 to 134 Each page is divided into eight pages p〇 to P7 ^ or there may be 16, 32 or more pages of memory cells in each block. The unit of stylized and read data in the page block contains one time. Stylized minimum amount of data. NAND architecture in Figure 3. a page is formed by a memory cell along a word line within a block. However, to increase the operational parallelism of the memory system, such pages within two or more blocks can be logically The linked page is shown in Fig. 5. Fig. 5 shows a metapage 151 formed by physical pages from one of the four blocks 131 to 134. For example, the metapage 151 is included in each of the four blocks. Page P2 within the block, but the pages of the unary page do not have to have the same relative position within each block of the block 117059.doc • 16-1336856, although preferably across all four planes side by side To program and read the maximum amount of data, to achieve higher system performance, the memory system can also be operated to form a metapage from any or all of one, two or three pages in separate blocks in different planes. This allows the stylization and read operations to adaptively match the amount of data that can be easily processed in parallel and reduce the chance that the portion of the unary page will remain unprogrammed. As shown in Fig. 5, a unitary page formed by a plurality of planar physical pages includes memory cells along the plurality of planar word line columns. Rather than stylizing all cells in a word line column at the same time', it is more common to use two or more interlaced groups to alternately program 'each group stores a data page (in a single block) or A data element page (across multiple blocks). By programming the alternate memory cells once, it is not necessary to provide each bit line with a peripheral circuit unit including a data register and a sense amplifier for time division between adjacent bit lines. This saves the amount of substrate space required for the peripheral circuitry and allows the memory cells to be packaged at an increased density along the columns. In addition, the preferred system simultaneously programs each unit along a column to maximize the parallelism that can be obtained from a given memory system. Referring to FIG. 3, by providing two columns of select transistors (not shown) along at least one end of the NAND strings instead of the single column shown, it is extremely convenient to simultaneously program the data into every other memory along a column. In the body unit. A column of the selected transistor money response-control signals will be connected to each individual bit line within the block, and the other selected transistors will respond to the additional control signal to be in the middle of each string. Connect to its individual bit line. Because: 117059.doc

1336856 Writes two data pages to each column of the 5 memory cells. The amount of material in each logical page is typically an integer number of one or more data segments. By convention, each segment contains 512 bytes of data. Figure 6 shows a logical page of one of the data sections 153 and 155 of one page or metapage. Each section typically contains 512 bytes of stored user or system data portion 157 and a different number of bits of management data associated with the data in section 157 or its stored physical page 1* or block. Tuple 1 5 9 . The number of bytes of the management resource is typically 16 bytes, which form a total of 528 bytes for each of the segments 153 and 155. The management part ι59 may include: an ECC, which is an experience count, one or more control flags calculated according to the data portion ι57 during the stylization period, its logical address, the number of erased and reprogrammed blocks, and the number of times of control. The standard, operating voltage level and/or the like, plus an ECC calculated from such management data 159. Alternatively, the management data 159 or a portion thereof may be stored in different pages in other blocks. As the parallelism of the memory increases, the data storage capacity of the metablock increases # and the size of the data page and the metapage also increases. This data page can contain more than two data sections. One

Material section. There are two sections in a data page, and there are four sections in each of the two metapages. The material thus stored for each metapage. This is a relatively high degree of parallelism and is further increased as the number of memory cells increases. To this end, the width of the hidden body is extended to add one page and one dollar page. The many examples described in this application use meta-regions* and stylized units, respectively, but most of the techniques are block and page. Wipe and program the unit. Class 117059.doc 1336856 The technique applied to a memory system using blocks and pages is generally applicable to metablocks and metapages. The above identified entities are smaller re-programmable non-volatile memory cards and flash drives with commercial data storage capacity of 512 million bytes (MB), i + 100 million bytes (GB), 2 GB and 4 GB and possibly higher. Figure 7 illustrates the most common interface between a host and such a mass storage system. The host is a data file generated or used by the application software or firmware executed by the host. One character processing data file is an example, and one of the computer aided design (CAD) software drawing files is another example, which is mainly found in general computer mainframes such as PCs, laptops, and the like. A file in the Pdf format is also such a file. A static digital video camera produces a data file for each photo stored on a memory card. A cellular phone uses information from a file on an internal memory card, such as a telephone directory, which stores and uses a number of different files, such as an address file, a calendar file, and the like. In any such application, the memory card can also contain software for operating the host. s memory system, especially the memory system embodied in the removable card ~T, 'good by a standard interface to communicate with different hosts. Different hosts can communicate differently with the memory system. The second interface class uses such interfaces as one of the logical addressing systems of the shared logical address space and the addressing systems based on the interface and the slot. Logical Addressing Figure 7 Φ ss - ρ, a common logic interface between the host and the semester system. A contiguous logical address space 161 is large enough to provide an address for all data that can be stored in the memory system. The host address space is typically divided into data cluster increments, each cluster being designed to contain several data segments in a given host system, and in some cases between 4 and 64 regions • k. A standard section contains 5 12 bytes of data and some management data. In the example of Figure 7, it is shown that three files 丨, 2 and 3 have been created. An application running on the host system creates each file as an ordered data set and identifies the application by a unique name or other reference. Sufficient available logical address space not allocated to other files is assigned to file 1 by the host. File 1 shows that a continuous range of available logical addresses has been assigned. Address ranges are also typically configured for specific purposes, such as for a particular range of host operating software, thereby avoiding the use of such address ranges for storing data, even if the host assigns logical addresses to the data. Address. As shown in Figure 7, when file 2 is created behind the host, the host similarly assigns two different consecutive address ranges within logical address space 161. A file does not have to be assigned a contiguous logical address, but can be an address fragment that is placed between the address ranges of other files. This example then displays another portion of the host's address space that was previously not configured for the file and other data for the other file created by the host. In this example, File 1, File 2, and File 3 are all assigned to a portion of a shared logical address space (logical address space 16 1). The host keeps track of the memory logical address space by maintaining a file configuration table (FAT) with a directory in which the logical addresses assigned by the host to various host files are maintained. This directory is generally stored with FAT in non-117059.doc

1336856 Volatile memory and host memory, and frequently updated by the host with the storage of new rights, deletion of other files, modification of files and the like. For example, when deleting a host file, the host can unconfigure the logical address previously configured for the deleted file by updating the directory and FAT table to show that it is now available for other data references. In some cases, only the directory is updated when a file is deleted and the FAT project remains for the expired data bundle, set. One of the logical addresses used within the FAT can be referred to as a logical block address φ (LBA), so one of such logical addressing is used in the logical address space that is typically used for data from different slots. The interface can be referred to as the lba interface. The host does not care about the physical location of the memory system controller to choose to store the file. A typical host only knows its logical address space and the logical addresses that have been configured for its various files. On the other hand, the memory system only knows the part of the logical address space that has been written to the data through a typical host/card interface, but does not know the logical address configured for a particular host file, or even the number of host files. The memory system controller converts the logical address provided by the host for storing or capturing data φ into a unique physical address within the array of flash memory cells storing the host data. A block 163 represents one of the logical to physical address ^ conversion worksheets maintained by the memory system controller. ‘· The memory system controller is programmed to store the data file in a block and metablock of the memory array I65 in a manner to maintain the system efficiency b at a higher level. Four planes or subarrays are used in this description. Preferably, the maximum parallelism allowed by the system is used to program and read data across one of the entire metablocks formed by a block from each of the planes. At least one metablock 167 is typically configured as a reserved area 117059.doc

A - 21 - Block ' is used to store the work and materials used by the memory controller. Another metablock 169 or a plurality of metablocks can be configured to store host operating software, host FAT tables, and the like. Most of the physical storage space is reserved for storing data files. However, memory controllers generally do not understand how the host has configured receiving data in its various archives. All memory controllers generally learn from interaction with the host, and the data written by the host to a specific logical address is stored in the corresponding physical address maintained by the logical-to-physical address table 163 of the controller. In a typical memory system, in addition to the storage capacity necessary to store the amount of data in the address space 161, the storage capacity of some additional blocks is provided. One or more of the additional blocks are used as redundant blocks for replacing other blocks that may become corrupted during the life of the memory. A logical tool set that typically changes a block contained within an individual metablock for various reasons includes replacing a corrupt block originally assigned to the metablock with a redundant block. One or more additional blocks (e.g., metablock 171) are typically maintained in an erase block pool. When the host writes data to the memory system, the controller translates the logical address assigned by the host into a physical address within the unary block in the erased block pool. Other metablocks that are not used to store the logical address space I" are then erased and designated as erase pool blocks for use during subsequent data write operations. As the original stored data becomes out of date, the new data frequently overwrites the data stored at the logical address of the special host. In response, the 'memory system controller writes new data in an erase block, and then changes the logic to the physical address table for the logical address to identify the logical address at which the data is stored. 117059.doc 1336856 New physical block. The blocks containing the original data at the logical addresses are then erased and made available for storage (4). If at the start of the writer = there is no storage capacity in the pre-erase block from the erase block pool, then such erase must often be sent before the current data write operation is completed. This can be used to facilitate the shadow (4) (four) material programming speed ^ memory controller generally only when the host writes new data to the same logical address of a given logical address, know that the data has been The host is described as expired. Many of the blocks of this memory can therefore temporarily store such invalid information. The size of the block and metablock is increasing to efficiently use the area of the integrated circuit memory chip. This results in a larger proportion of individual data being written to store the storage capacity below one dollar block and in many cases even at least one of the storage capacity of one block. Since the memory system controller typically directs new data to a wiper block, this can cause portions of the metablock to be unfilled. If the new data is an update of certain data stored in another metablock, then the logical addresses of the logical addresses adjacent to the new data element pages are also required to be logical addresses from the other elements. The remaining valid data element pages of the block are copied in the Xinyuan block. The old metablock can retain other valid material metapages. This point over time causes the data of a particular metapage of a unique metablock to be described as expired and invalid, and replaced by new data with the same logical address written to a different metablock. In order to maintain sufficient physical memory space to store data on the entire logical address space 161 'this data will be compressed or merged periodically (garbage collection) ° also need to actually put the data in the metablock as much as possible Sections are maintained in the same order as their logical addresses, 117059.doc -23- 1336856, since this makes reading data in adjacent logical addresses more efficient. Therefore, generally, data compression is performed under this additional objective and (10) collection. U.S. Patent No. 6,763,424 describes certain aspects of managing the use of a memory and metablock when receiving partial block data updates. Data compression - generally involves reading all valid data element pages from a single block and writing them to a new block. 'Ignore invalid data in this program.

Meta page. The metadata page with valid data is also preferably configured with - physical address - human order - the physical address matches the logical address order of the data stored in the meta pages. The number of metapages occupied in the new metablock will be less than the number of metapages occupied in the old metablock, since 70 pages containing invalid data are not copied into the new metablock. Then erase the old block and make it available for storing new data. The additional metapage capacity obtained by the combination is then used to store other data. Collecting from two or more metablocks with proximity or during garbage collection

A metapage of valid data that is almost adjacent to a logical address and rewritten in another ^block' is usually a metablock in the erased pool. Copying all valid material pages from the original two or more 70 blocks can be erased for future use. Data merging and garbage collection # can take f time and can affect the performance of the memory system, especially if data merging or garbage collection needs to occur before the command from the host can be executed. Such operations are typically scheduled by the memory system controller to occur as much as possible in the context, but the need to perform such operations may cause the controller to provide the host with a busy status indicator, 117059.doc -24- 1336856 Until such an operation is completed. An example of delaying the execution of a host command is that in the following scenario 1, there is not enough pre-erased metablock in the erase block pool to store all the data that the host wants to write into the memory, and firstly needs data merge or garbage collection to clear One or more valid data element blocks can then be erased. Therefore, attention has been directed to the control of management memory to minimize such interruptions. A number of such techniques are described in the following U.S. Patent Application: Serial No. 1 〇 / 749, 831 'December 3 (2003) application, titled "Management of Non-Volatile Memory Systems with Large Erase Blocks";; Serial No. 10/ 750, 155' December 30, 2003 application, titled "Non-volatile memory and method with block management system"; No. 1〇/917,888,2〇〇4年8 Application on March 13th, titled "Non-volatile memory and method with memory plane alignment"; No. 10/917,867, August 13, 2004 application; Serial number 10/917,889, August 13, 2004 , titled "Non-volatile memory and method with phasing program invalidation"; and serial number 1〇/ 9i7,725 'Application dated August 13, 2004, titled " Non-volatile with control data management Sexual memory and methods". A challenge to efficiently control the operation of a memory array having a significant erase block is to match and align the number of data sectors being stored during a given write operation with the capacity and boundaries of the memory blocks. . A method is to allocate less than a maximum number of blocks for storing one of the new data from the host when it is necessary to store a quantity less than the number of blocks filled with an entire metablock. U.S. Patent Application Serial No. 10/749, filed on Dec. 30, 2003, the disclosure of which is incorporated herein by reference. May 7th, 2004, the patent application serial number 117059.doc -25- 1336856 10/841,118 and December 16, 2004 6'27 1 private title for the stylization of data operation, indicating the boundary between data blocks Adaptation between physical boundaries with metablocks. The memory controller can also be used from (4), which is stored in non-volatile memory by the host to operate more efficiently.

Recall system. This type of use is used to understand when the host recognizes the data as expired by canceling the logical address of the f material. Knowing this allows the memory controller to schedule the erase before it is normally written to the logical address by the host to understand the block containing the invalid data. This is described in U.S. Patent Application Serial No. 10/897,049, filed on Jul. 21, the entire disclosure of which is entitled "<RTIID=0.0>> Other techniques include monitoring a host file that writes new data to memory to infer whether a given write operation is a single file, or whether it is a multiple file at the boundary between the files. 2, 4, December 23

The number of patent applications filed is US Patent Application Serial No. 1/〇22,369, entitled "FAT Analysis for Optimizing Continuous Cluster Management", indicating the use of this type of technology. In order to operate the memory system efficiently, the controller needs to know as much as possible the logical addresses of the data that the host assigns to its individual files. However, when the host/memory interface includes the logical address space 161 (Fig. 7), it is difficult for the memory controller to know more about the host data file structure, as described above. Addressing based on broadcasts An alternative interface for bulk data storage between a host and a memory system eliminates the use of logical address spaces. Instead, the host is logically addressed to each other by a unique file ID (or other unique reference) and an offset address in the data unit (eg, bit 117059.doc -26-group) within the file. This file address is directly supplied to the memory system control H, and the memory line controller then maintains a table of the location of the data stored in each host file. This new interface can be implemented using the same memory system as described above with respect to Figures 2-6. The main difference from the above is the way the memory system communicates with a host system. In Figure 8, the description is based on the standard case, which should be compared with the logical address interface of Figure 7. The identification of one of the files of the files 2 and 3 and the data offset of the broadcasts of FIG. 8 are directly transmitted to the memory control_. The logical address information is then translated into a physical block of the memory 165 and a physical address of the meta page by a memory controller function 173. Since the memory system knows the location of the data that makes up each file, it can be erased as soon as the host deletes the file. This is generally not the case for a typical logical address interface. In addition, by using archival objects instead of logical addresses to identify host data, the memory system controller can store data in one way that reduces the need for frequent data merging and collection. Therefore, the frequency of data copying operations and the amount of copying data are significantly reduced, thereby increasing the stylized and read performance of the memory system. Examples of rights-based interfaces include such interfaces that use direct data file storage. The direct data file storage memory system is described in the following pending US patent applications: Serial Numbers 11/060, 174, 11/060, 248, and 11/060 '249 'All applications were filed on February 16, 2005, in the name of Alan W. Sinclair or with Peter J. Smith, and in provisional applications filed by Alan W. Sinclair and Barry Wright, 60/705, 388 117059. Doc • 27- 1336856, titled "Direct Data File Storage in Flash Memory" (collectively referred to as "Direct Data File Storage Application"). Due to direct data storage applications The file interface (shown in Figure 8) is simpler than the logical address space interface described above (as described in Figure 7) and allows the memory system to perform better, so the direct data file storage system preferably has many However, at present, the host system is mainly configured to operate using a logical address space interface, so a memory system having a direct data file interface is incompatible with most hosts. Therefore, it is necessary to provide a memory system for any interface operation. Logic to Virtual File Mapping, US Patent Application No. 1 1/196 869, filed August 3, 2005, entitled " And the interface system based on the direct data file operation, describes a system that enables a memory system to use a logical addressing interface or a file-based interface to interface with the host. Figure 9 illustrates such a system. The host operation of Figure 7 and the file-based memory operation of Figure 8 plus an added address translation 丨 72 within the memory system. Address translation 172 sets multiple sets of logical addresses across the memory space 161. Map to individual logical files & to " across the modified address space 16". Preferably, the entire logical address space 161 is divided into the logical files, so the number of logical files depends on the logical address space and the size of the individual logical files. Each logical file of the logical references contains a set of data that contiguously contiguous logical addresses across space 161. Preferably, the amount of data in each logical file of the logical files is the same and the amount is equal to the data storage capacity of the unary blocks in the memory 165. The unequal size of the logical file and/or 117059.doc • 28 - 1^6856 is different from the storage capacity of one of the blocks or metablocks of the 6th δ recall. The data in each of the files in the individual files & to are represented by logical offset addresses within the files. The file identifiers and data offsets of the logical files are converted to physical addresses within the memory 165 at 173. The logical files a to j are stored directly in the memory 165 by the same private order and agreement as described in the direct data file storage application. Especially in the case where the number is equal to the capacity of one block or metablock of the memory, the program is the same as the program for storing the data file of FIG. 9 in the suffix 165, except for the logic. The amount of known data in the file makes this simpler. The logical files of the logical files 3 through 〖 are shown in Figure 9 as being mapped to one of the metablocks of the memory block 165. It is also necessary for the file-based storage to be the same or-equivalent to interact with the host as the current logical address memory system that the host is designed to interface with. By mapping individual logical troughs into corresponding individual memory metablocks, the direct data archive interface is used to achieve essentially the same performance and timing characteristics as when using logical address space interfaces. ^ Figure 9 is a data file-based back-end storage system designed to work with a host through a traditional logical address space interface. It can also have an additional direct data file interface. The host data files from the file interface and the logical broadcasts from the logical interface are translated into memory metablocks: address. The data is then stored in the address of the memory by an execution-direct data slot protocol. This agreement contains the direct data archive storage technology of the previously listed direct data storage application. Field 117059.doc -29· 1336856 Logical Addressing File Storage As described above, the data is maintained in a contiguous area of a memory array and uses a memory system managed by a file as a file. Advantages. However, many hosts provide data to the memory system in the form of data segments with logical addresses. Host files in such systems • may be logically fragmented such that one host file occupies multiple logical address ranges while other data occupy an intermediate logical address range. Although mapping a logical address space to a virtual file using a predefined _ mode allows a filed primary back end to handle logically addressed data, the virtual file maintains a logically fragmented pattern of logical address spaces, such that A metablock containing a single virtual file may contain material from a Xuxiang host broadcast. A memory system needs to receive logically addressed data from a host and store the data from a single host file in one or more blocks that do not contain data from many or any other files. data. In this way, even if a host using a logical address space shared by all files is used to transmit one of the data in the form of a segment having a logical address, the advantage of the standard-based storage can still be realized. Some advantages. In one embodiment, a host sends information about a data section to a memory system prior to transmitting the data section. The memory system can use this information to store the segment and other segments of the same file. In this manner, segments from the same rights are held together in a particular segment that can be dedicated to storing only the standard (although some blocks may store data from multiple files). The information sent by the host can be in the form of FAT and directory sections, and the FAT and directory sections provide configuration information about the section to be sent 117059.doc I336856. This sequence is the reverse order of the usual sequence 'in the normal sequence, the host sends the data section, then sends the configuration information in the form of FAT and directory sections and the 'in the first system', the simon system generally does not use fat And the contents of the directory section to modify its operation.

One of the goals of a logically addressed file storage scheme is to receive logically fragmented material from a host and store the file in a physical configuration that is less fragmented than the logical segment. Thus, one of the files mapped to two or more portions of the discontinuous logical address space (with other logical addresses between the two portions) is continuously stored in the physical memory array. use

- Entity continuous storage of files may mean that all data in a file is stored in a single block, or when the data in the file exceeds the capacity of a block, the data from the file exclusively occupies - or Multiple blocks and only one block contains information from the file and other resources not from the file. The blocks that store the data from the case do not need to be configured in any particular way. Thus, "continuous" in this context does not mean that the blocks containing the instance are located together, but that the data is configured in the other block. Figure 10 shows a logically addressed file storage scheme in accordance with an embodiment of the present invention. - The host sends the file i, the broadcast 2 and the slot 3 for storage in the memory array 18G. From the file to the logical address conversion 16 (4), the host adopts the mode of the class (4) shown in FIG. 7 and the lion to share logical address space 161. The broadcast file is logically fragmented as shown in data file 2, and the data file 2 occupies two parts of the logical address space 161, and the data is not occupied: the middle portion separates the two parts. Similarly, the data file 3 is divided into 117059.doc -31 · 1336856 into two parts. In some memory systems, the file may become more fragmented. The standard takes up many separate parts of the logical address space. When the data files 1, 2, and 3 are mapped to the logical address space by the file-to-logical address conversion 16 ,, the file-to-logic address conversion information 产生 82 is generated. The file-to-logic address translation information 18 2 is passed to the memory. However, unlike many prior systems, in this case, the file-to-logic conversion information 182 is sent to the memory prior to the material it references. Thus, information reflecting the mapping of file 2 to two different logical address ranges of logical address space 161 is sent to the memory prior to transmitting the data segments of the logical address ranges. The trough-to-logical address translation information 182 allows the logical-to-physical address translation 184 to be accomplished using a file-to-logical address translation information 182 to determine one of the physical addresses of the individual segments to be stored. 1A shows a metablock 配置67 configured as a reserved block, a metablock 169 configured to store host operating software, a host fat table and the like, and a meta-region previously maintained in an erased block pool. Block 171. Figure 1〇 also shows the archives stored in the unary block, the archive 2 in the other metablock, and the archive 3 occupying the other metablocks. Even if the file 2 is mapped to the logical address space 161, the second separated portion 'stores the two parts of the file 2 together due to the logical-to-physical address translation 184. Similarly, file 3 is logically fragmented into two parts' which occupy two portions of logical address spaces 16i that are separated from each other. Additional information that is not part of Block 3 is mapped to the middle of the logical address space. However, the logically separated portions of File 3 are stored together in a binary block that does not contain data for other files. It is advantageous to configure this file in the metablock to contain only a single file, because 117〇59.do, • 32- is when an archive becomes expired, an entire metablock becomes out of date and does not need to be Copying of valid data generally done during garbage collection. It may not be efficient to have all of the metablocks store only one file of data, as the file may not be able to fill an integer number of metablocks and maintaining unused portions of the metablock will reduce memory capacity. However, comparing previous systems (even if some of the metablocks contain data from multiple archives) can reduce file fragmentation in the memory array. The information can be combined later from other files so that it is not wasted

Residual archives from multiple archives use an efficient approach. Figure 11 shows an example of archive A, which is mapped to logical address space 161 and logically fragmented into four sections by this mapping. The file for this mapping to logical address translation information 182 is sent to the memory before the data is sent to the memory. Therefore, the logical address mapped by the portion of the file A is identified by the file to logical address information 182 due to the file A. Then, when the data of the file A is sent to the memory, the location of the data of the file A is stored. Determined by the identification of the file a. Figure η shows the logical to physical translation 184 that occurs in memory. The portion of file A mapped to the logical address space 1 > 1 1 is mapped to the contiguous portion of the physical memory array 180. In this example, metablock 4 fills up the data from archive eight and metablock 7 fills the data from archive A. In metablock 7, 117059.doc 1336856 is combined into a single shared block. Notification Schemes Various notification schemes can be used to send files from the host to the memory to logical address translation information. In one example, the notification scheme used follows the same format as that used when storing control information in memory. This scheme uses the FAT section and the directory section to update the FAT and directory information in the non-volatile memory so that it can be used for later restoration. _Displays the method by which configuration information can be stored. Slots 8 and 0 are stored in a memory. — The catalogue includes items for both the case and the broadcast. A directory item contains various information about a file 'including the first cluster of the file. Thus, for file A, the directory item indicates the first cluster of cluster 2, so the first FAT project for broadcast A is used. Cluster 2 project. The first cluster system cluster is indicated for the rights B' directory item. The courage contains a cluster item indicating the cluster under which the file is indicated. Because @, when the location of the first-FAT project for a profile is obtained from the catalog, the FAT project for the previous cluster configured for the profile indicates the follow-up belly project. It can be considered that the FAT project key lock ", because & for a particular slot case, a win item points to the next - position. For the audit file a 'cluster 2 is indicated by the directory ^一隹隹# The project for cluster 2 indicates that cluster 3 is used for one of the documents A: 隹〃. The item for cluster 3 refers to * cluster 4 is used for the lower cluster of slot A. 4 is used for the project indication of cluster 4 - the end of the file (E °F). Thus, cluster two: give the last cluster of slot A. For the case B, the directory indicates the ΐ-cluster of the B. The item for cluster 0 indicates that cluster 1 is used for the lower cluster of the file.项目 The item indicated for cluster 1 is cluster 5 for the next cluster of archives 117059.doc -34- 1336856 B. The item for cluster 5 indicates cluster 6 is used under archive b - cluster and the item for cluster 6 indicates the end of a file. Thus, cluster 6 is the last cluster of archives B. The FAT and directory information is typically maintained by a host and periodically stored in non-volatile memory by sending FAT segments and directory segments. • The previous scheme has used the directory and FAT structure to store files to logical addresses, a message. However, unlike the prior scheme, one of the φ examples according to one embodiment of the present invention transmits the file to the logical address information before transmitting the data to the memory. In a typical prior system, the FAT and directory segments are sent and stored in memory only after the data to which they are referenced. One reason for delaying the transmission of FAT and directory segments is to avoid recording incorrect information in non-volatile memory in the event of power loss prior to writing data. In one embodiment, a solution avoids this problem by writing only the portion of the FAT for a file before storing the file referenced by the FAT for a file. In this way, if a power loss occurs, part of the FAT indicates that the write is collapsed | the project is not completed and the file cannot be used. ^ In the exemplary notification scheme, the FAT and directory segments are sent by the host to inform the memory about the file configuration of the data segment that the host is about to send. In general, it is not necessary to send the file configuration information for each cluster of the transmitted host data. In the case where a host transmits a continuous sector cluster, the memory assumes that the clusters belong to the same file. Thus, in the case of transmitting a single file as a continuous cluster stream, the host can identify the table only before sending the first cluster and send the file end pointer after the last segment. Figure u shows that the host sends a file of Figure 12 to the memory. 117059.doc -35- 丄336856

example. First, a directory section 301 is sent which indicates that cluster 2 is the first cluster of files. The segments of cluster 2 are then sent and stored by the memory in a new block 302 of the memory array because this cluster is the beginning of a new host file. Subsequently, the segments of clusters 3 and 4 are successively received and stored in the same block as the segment of cluster 2. After receiving cluster 4, the host sends a _FAT section 303 with a file end directory for cluster 4, which indicates the last cluster within file A. It is also possible to send all FAT information for file A at this time because the entire file A has been stored. At this point, the memory can close file A and perform a reclamation operation when needed. This point shows an example of a file that is sent in a logically continuous manner without any intermediate writes to other files. Figure 14 shows an example of a host of Figure 12 transmitting a file B. First, a directory section 410 is sent which indicates the first cluster of clusters of archive B. The cluster is then sent and stored in a new block 412 because. Then, receive the area of cluster 1 and the sections are the first section of a new file.

The segments are also stored in block 412 because they continue to assume that they are also from broadcast B because of the segments and the segments of the cluster. Next, receive a coupon ¥ 414' which is included for the cluster! The indicator of the FAT project and used for this project indicates the next cluster in the Cluster 5 Series File B. The ρΑΤ section 414 may not contain the item for cluster 5 at this time because the host has not yet sent the cluster 5. The FAT section 414 notifies the memory controller (four) that although there is a hop at the logical address from cluster i to cluster 5, the section of cluster 5 contains plexes #1 from (four) B under H and then 'when cluster 5 is received The segments are then stored in block 412 along with the segments of cluster 1. After 117059.doc -36 - 1336856, cluster 6 is received and stored in block 412 because it is contiguous with cluster 5. Subsequently, a FAT section 416 is received which contains the _ file end entry for cluster 6. You can then close the file and perform a reclamation operation on the block containing file B if necessary. In some cases, the memory can assume that the host will continue to write to the next cluster of the same file when there is a jump in the logical address. In such a memory system, no special notification is required when the host continues to write data from the same file using a jump in the logical address. Figure 14 can be viewed as an example of logically discontinuous writing of one file without intermediate writing to other files, because there is a jump in the logical address between the segment of the cluster and the segment of cluster 5. , but the host sends the file B in a time period dedicated to sending the file B (ie, no data from other files is sent during this time). Figure 15A shows two files C and D mapped to a portion of a logical address space. In this case, the two files C&D are not only fragmented in the logical address space, but also sent in a temporary fragmentation manner. . The host sends the clusters of files C and D in a logical order, so the cluster 10 is sent first, then the cluster 发送 is sent, then the cluster 12 is sent, and so on. Even though the clusters are sent in a logically sequential order, the move still involves some changes between the files. The host notifies the changes between the memory files. Figure 15B shows the method by which the host notifies the memory when the host begins writing to a different file. First, a directory section 52 is sent which indicates the first cluster of the cluster file C. The host then sends the clustered chunks and stores them in a memory array within a new chunk 522 because the sections are the first section of a new archive. Then, the host sends another directory section 117059.doc •37-

524 ' refers to the first cluster of clusters that do not cluster u. The cluster 11 is then sent and stored in another new block 526. Receive clusters 12 and /, clusters 11 are then stored together in block 526. The memory system assumes that cluster 12 belongs to the same archive as cluster 11 because cluster 12 and cluster Ui|_ continue and the host does not otherwise indicate. Next, the host sends a - FAT section with the item for cluster 10. The project for cluster 1 includes an indicator of it: a cluster under the archive of cluster 10 (file c). In this case, the indicator indicates under the file C - cluster cluster 13 . Then, the receiving cluster 13 is logically continuous even though it is received with the last cluster (cluster 12), but the memory system still knows that the cluster 13 system is configured for the archive c, so the region of the cluster 13 & Stored together in block 522.

The following table summarizes the notification schemes for identifying the file configuration for the above examples.

Continuously different files to the next cluster of items for the last file cluster jump jump different file machine to send a new FAT section, which: ^'^'^_ next cluster or no project for the last file bundle _ 1 machine sends if indicates the second directory section of the salary file _ x, ^ machine sends a new FAf section, and the next cluster of signals for the last file of the project ^ cluster of rights, the host can An indication is sent by 117059.doc -38 - 1336856 including one of the FAT sections for the end of one of the cluster files, ie the cluster is the last cluster of a particular file. This allows the file to be closed and allows the memory system to perform a reclamation operation on the block containing the file, as described below. Memory Operation In an example, when a host closes a file, the metablock containing the file data can then be marked for preparation for recycling operations. Techniques for recovering memory space in a memory system using the techniques of the present invention are similar to those described in the Direct Data Archives Application. In particular, when the file is closed - there may be one or more metablocks filled with data from the file, but there is often a block of a that only partially fills in the data from the file. In order to store the residual file data more efficiently, the host can copy the residual file from one file to a block containing the residual file data from another file. Choose which residual profile to remove and move its destination to keep the amount of unused memory small. Thus, if a file is closed and the residual file data occupies 3% of the unary block, the memory system will look for a metablock containing 70% (or close to 7〇%) of the remaining file data occupying the unary block. The meta-block containing the portion of the data from multiple files can be considered a shared block. Although direct data archive storage techniques can be combined with the techniques of this application, embodiments of the present invention generally use logical addresses to manage data within a memory array without the use of file identifiers used in direct data file storage. In another example, in accordance with an embodiment of the present invention, one or more dedicated metablocks and a shared block of the memory system in the memory array are I17059.doc

A -39- Save the file so that when the slot is no longer needed by the host, you can immediately erase the 4 dedicated S block for reuse and can schedule the shared block for garbage collection. The directory and FAT information generally indicate when the host has deleted the file by removing the directory item for a file. In some cases, FAT items can reflect this deletion. A memory system can determine that the host has been deleted - the file based on the directory, so any metablock containing only the data from the 41⁄4 case can be erased. This type of metablock can now be added to the section where the metablock is to be erased as part of the ongoing reclamation operation. Similarly, a shared block containing one of the materials from the Xiao case can be added to a block of garbage collection, so that the space occupied by the expired data can be recovered. An efficient method can be used when the δ mnemonic system has information about the host deleting files and the files are stored in the metablock together with a plurality of metablocks containing data from only one file in a continuous manner. Schedule recycling operations. An example of such scheduling is described in U.S. Patent Application Serial No. 1/259,423, filed on Jan. 25, 2005, entitled "Scheduled Non-Volatile Memory Recycling Operations". One advantage of one of the notification schemes based on a FAT and directory section is that it uses signals that are typically used for an LBA interface. Many prior systems are compared, and these FAT and directory segments are sent at a time, but they contain valid information and are generally compatible with previous LBA interfaces. Thus, a host using a notification scheme in accordance with one embodiment of the present invention will be compatible with a suffix system that does not use such notification schemes. Such a memory system will store the FAT and directory segments without using it to determine where to store the host data segments. The FAT segment stored in this manner is valid because it contains items for the stored 117059.doc • 40-data cluster. Thus, in the event of an unexpected power loss, the FAT data stored in the non-volatile memory will not be erroneous. The incomplete nature of the FAT information used for the broadcast may indicate that the memory system has not completed storing the data for the file in the event of a power loss. Although the example provided above uses the Control Data section (FAT and Directory) to send configuration resources, other information can also be sent by using a host that is compatible with the existing logic. Sending two or more identical FAT segments can indicate subsequent host behavior to a S-repeated system. In one example, one machine is available. The memory system indicates that the host does not need immediate access to the memory system and will maintain power. This point can be indicated by continuously transmitting repeated fat segments. The memory system can only write to one of the segments, or both can be written. In response to the received duplicate FAT segment, the memory system determines that power will be maintained and the host does not require any immediate access, so the memory system can enter-idle. In an idle state, the memory system can perform a transaction (e.g., a recycle operation) to garbage collect metablocks containing expired data and merge metablocks containing unwritten portions. An idle state is terminated by receiving another host command. The memory system can indicate a busy status to the host while performing housekeeping operations in the idle mode. A busy stone status indicator informs the host that the memory system is performing housekeeping operations, but does not prevent the host from sending a command to terminate the housekeeping operation and begin executing the new command. In another example, a host can indicate an upcoming power cut by transmitting an identical FAT segment three times. I have recalled that this signal can be reacted by entering a shutdown state. In this case, the memory system indicates to the host that it is busy until it stores the data in the non-volatile memory and does not perform any other operations to protect it from power cut-off. The host waits until the memory system is no longer busy before removing power. Multiple host FAT or directory segments can also be sent by the host to indicate other host behavior. A host can also use a duplicate control information section to identify a particular slot for deletion. When a memory system receives an indication from a host that a particular file should be deleted, the file is placed in a column for garbage collection. Similarly, a host can also use a duplicate control information section to identify a particular file for erasing. When a memory system receives an indication from a host that a particular file should be erased, the memory system places the file in a queue for garbage collection and immediately proceeds to perform garbage collection from non-volatile The memory array removes all the data from the file. In the case where a memory system is capable of using a notification signal, but the connection does not provide a host for such a notification signal, the memory system determines that the host does not provide a notification signal' and then stores the data in a manner that does not require such a signal. The memory system can make this decision when the memory system first receives communications from a host. For example, if the memory system receives a data segment to be written without any previous fat or directory segments, the memory may determine that the host will not be actuated by such signals and may select a data storage scheme. Ignore the file configuration of the section when selecting the location of the storage section. In one example, the 'from the host' "recognition drive" command allows the host to determine if a memory system can use the notification signal. The memory system responds with a "identification drive command returning information' which includes whether it has this capability. One of the preset data storage schemes used by a memory system connected to one of the unsupported notification signals can store the data as shown in Figure 7 regardless of the profile of a particular sector 117059.doc • 42-13638856. An example of such a storage solution is provided in U.S. Patent Application Serial No. 10/750,155, the disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in 10/917,889 and 10/917,725. In another embodiment, a notification scheme may not be limited to communicating in accordance with an existing interface. Additional commands that define an incompatible one existing interface are used to provide configuration information from a host to a memory system. When first connected, hosts and cards that use additional commands typically require a handshake route that makes it possible to recognize the use of such additional commands. In general, hosts and cards that can use such additional commands will also be able to operate without additional commands when connected to a host or card that cannot use these additional commands. Thus, backwards compatibility is maintained for memory systems and hosts that use any such new commands. Additional commands may also be provided that are independent of the delivery profile configuration information. For example, an explicit command may be defined for a host to erase or delete a particular profile. While the invention has been described with respect to the specific embodiments of the present invention, it is understood that the invention is intended to be protected within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a host connected to a non-volatile memory system as one of the currently implemented ones; FIG. 2 is an exemplary flash memory used as one of the non-volatile memories of FIG. Figure 3 is a block diagram of a memory cell array that can be used in the system of Figure 2; 117059.doc • 43· 1336856 Figure 4 illustrates an exemplary physical memory organization of the system of Figure 2; 5 shows an expanded view of one of the physical memories of FIG. 4; FIG. 6 shows another expanded view of one of the physical memories of FIGS. 4 and 5; FIG. 7 illustrates a host and a reprogrammable memory system. a shared logical address interface; Figure 8 illustrates a file interface between a host and a reprogrammable memory system;

Figure 9 illustrates a logical address interface used by a memory system to use logical address to logical file conversion; Figure 10 illustrates a logical interface between a host and a memory system, logic within the memory system The translation to the physical address depends on the file received from the host to the logical address information; Figure 11 illustrates the logical interface of Figure 10, a file is logically fragmented by a host and subsequently stored by the host The memory system is to be fragmented; « Figure 12 illustrates the use of a directory and file configuration table (FAT) to store file configuration information for files a and B in a memory system; Figure 13 illustrates the use as a logically continuous host One of the host files A sent by the data cluster informs the operation of the scheme; ", 丨P sentence is sent in the logical bit cluster and sent to the host slot B_, for example; one of the systems is notified of the operation of the scheme; Figure 15 Including the 拉 〒匕栝 〒匕栝 directory and file configuration table (FAT) for slot lucky (: and D's case configuration carefully 邙 六 6 # 育 育 储存 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育 育#

For the logical segment of the cluster C and the file D, the logical cluster is continuously contiguous and I 8 is handed over, and one of the host files sent by the most episode is notified to the party 117059.doc -44- 1336856 [main component symbol Description] 1 Host system 2 Flash memory 3 Matching part 4 Matching part 5 Application part 6 Driver part 7 Memory 8 Controller 10 Cluster 11 Integrated circuit chip/controller chip/cluster 12 Cluster 13 System bus/cluster 15 Memory Chip 17 Conductor Group / Data Section 19 Conductor Group / Address Section / Address Busbar 21 Conductor Group / Control and Status Section / 23 Internal Busbar / Controller Bus 25 Interface Circuit 27 Processor 29 Read Only Memory Body (ROM) 31 Read Only Memory (RAM) 33 Circuitry 117059.doc 45 - 1336856 35 Circuit 37 External Contact 39 Clock 41 Plane 43 Plane '* 45 Line Control Circuit, 47 Line Control Circuit 49 Bit Line • 51 Bit line 53 word line 55 column control circuit 57 source voltage control circuit 59 source voltage control circuit 61 P well voltage control circuit 63 P well voltage control circuit • 65 Input/Output Circuit 67 Data Input/Output Circuit. 69 Line, * 71 Line, 73 Interface Circuit 75 State Machine 77 Control Line 78 Control Line 79 Control Line 117059.doc -46- 1336856 79 Control Line 80 Control Line 81 Control Line 83 line 91 global bit line 92 global bit line 93 global bit line 94 global bit line 97 memory unit string 98 memory unit string 99 memory unit string 100 memory unit string 101 memory unit string 102 memory Early element string 103 memory cell string 104 memory cell string 107 charge storage memory cell 108 charge storage memory cell 109 charge storage memory cell 110 charge storage memory cell 111 selection transistor 112 selection transistor 115 word line 116 Word line 117059.doc -47- 1336856 117 word line 118 word line 119 gate 120 gate 123 first block 125 second block 131 plane or sub-array 132 plane or sub-array 133 plane or sub-array 134 Plane or Sub-Array 137 Block 138 Block 139 Block 140 Block 141 Meta Block 143 Second Element Block 145 Area 146 Block 147 Block 148 Block 151 Metapage 153 Data Section 155 Data Section 157 Data Section 117059.doc .48· 1336856 159 Management Section 160 File-to-Logical Address Translation 161 Shared Logical Address Space 161' Address Space 163 Block/Logical to Physical Address Table 165 Memory Array/Memory 167 Metablock 169 Metablock 171 Metablock 172 Address Translation 173 Memory Controller Function 180 Memory Array 182 File to Logic Address Conversion Information 184 Logical to Physical Address Translation 301 Directory Section 302 New Block 303 FAT Section 410 Directory Section 412 New Block 414 FAT Section 416 FAT Section 520 Directory Section 522 New Block 524 Directory Section 117059.doc • 49, 1336856 526 New Block 528 Not described in the text P0 Page PI Page P2 Page P3 Page P4 Page P5 Page P6 Page P7 Page 117059.doc -50-

Claims (1)

1336856 Patent Application No. 095146712 - Chinese Patent Application Substitution (September 99) X. Patent Application Range: 1. A method for storing data segments from a plurality of files in a non-volatile memory array, A section of each of the plurality of files is mapped to a shared logical address by a host, the method comprising: receiving, from the host, an audit configuration information indicating one of the profiles of a host data section; Receiving, by the host, the host data segment for storage in the non-volatile memory array; and subsequently storing the host f-segment segment in the non-volatile memory array in a physical address determined according to the file, The physical address is assigned to the file based on file configuration information from the host. 2. The method of claim 1, wherein the file configuration information from the host comprises a file configuration table information section. 3. The method of claim 2, wherein the host data segment is within a segment cluster and the file configuration table information segment includes an archive configuration table entry pointing to the cluster. The method of month length item 1, wherein the profile configuration information from the host. A directory information section containing an item for the file. 5. The method of claim 1, wherein the segment is stored in a erase block. The erase block is dedicated to storing segments from the file. 6. The method of claim 5, wherein after storing the host data section, the ::Hui host receives additional information indicating that the section is a post-segment section in the file and closes the file side by side in response The process is used for recycling. The method of claim 1 includes the step of receiving two or more n7059-990902.doc 8. from the host 8. The same control data section and the helmet are used as a response to the recovery operation, and the host is provided with a Status indicator. The method of claim 1 further includes receiving two or more identical control batting zones and preparing the memory array in response to a power loss. 9. - The method of storing the host data section from a host file in the non-volatile memory array as the minimum erasing unit - the section from the host file and other files is mapped to a shared logical address space, the method comprising: receiving a first plurality of data sectors of the host file, the first plurality of sectors occupying a first portion of the logical address space; and subsequently receiving the non-host file a second plurality of data segments, the first plurality of segments occupying a second portion of the logical address space; subsequently receiving a third plurality of segments of the host file, the third plurality of segments occupying a third portion of the logical address space, the first portion of the logical address space and the third portion of the logical address space responsive to the first and third portions of the logical address space The capital is identified as being set to the host (4), and the first plurality of segments and the third plurality of regions and ° are stored in the -= block of the memory array. Also; area ^. The second plurality of blocks are stored in the second element block. 10. The method of claim 9, wherein the first element block is dedicated to storing the data of the I17059-990902.doc 1336856 host file. The method of claim 9, wherein the first and third portions of the logical address space are identified as being configured for the host file due to the directory and file configuration table segments sent by the host. The method of claim 9, wherein the second portion of the logical address space extends from the first portion of the logical address space to the third portion of the logical address space, the method further comprising: receiving the first Before the second plurality of segments, a directory segment is received indicating that the first cluster of one of the second plurality of segments is not configured to the host archive. 13. The method of claim 12, further comprising: prior to receiving the third plurality of segments, receiving a profile configuration table section indicating that the first cluster of the third plurality of segments is not configured for the Host file. 14. A method of storing a host data file in a non-volatile memory array having a unitary block as a minimum erase unit, comprising: receiving a first plurality of data sectors of the host data file, the first Each of the plurality of sectors has a logical address from one of the logical address spaces defined for the memory array, the plurality of sectors having logical addresses occupying two or more of the logical address spaces a plurality of discontinuous portions; receiving a second plurality of data sectors not belonging to the host data file, each of the second plurality of segments having a logical address from the logical address space, and embedding the first plurality Receiving the second plurality of segments by receiving the segments; storing two or more discontinuities from the logical address space of 117059-990902.doc 1336856 in a metablock containing only one of the host data files Data; and receiving configuration information about the segment of the first plurality of segments prior to receiving the segments of the first plurality of segments, the file configuration information Identifying a plurality of such segments as belonging to that section of the host material resource files. 15. The method of claim 14, wherein the file configuration information is in the form of an archive configuration table and a directory section. 16. The method of claim 14, further comprising receiving a file end message, 'which indicates a logical address of the end of the host data file, and in response, closing the host data file and scheduling the host data file for garbage collection . 17. A method of interfacing a memory system and configuring a host data file sector to a host of a shared logical address space, the method comprising: the memory system receiving a plurality of host data segments from the host, the plurality The segments are configured to a host file, the plurality of host data segments having logical addresses assigned by the host but not consecutive; and the δ 圮 圮 system determining whether the plurality of segments are configured for the host® slot And in response to determining that the plurality of segments are configured for the host file - the case where the § memory system stores the plurality of segments in a portion of the memory array 'to enable the location to be consecutively located And the memory system uses the file configuration resource received from the host to determine whether the segment of the plurality of segments is configured for the host file. 1 8. The method of claim 17, wherein the file configuration received from the host is 117059-990902.doc 19. 20. 21. 22. 23. 24. The map includes one or more file configuration table information sections. The method of claim 1 wherein the file configuration received from the host is included in the file includes one or more directory segments. For example, the method of requesting item 7, wherein the record is /, TX heart and mind to further determine the end of the host file has been received and as A qw you close the file and schedule the file for garbage collection. : Used to interface configuration host data audit section A non-volatile memory system of one of the shared logical address spaces, comprising: - a memory interface, which receives a plurality of host data sections configured to the host file, the plurality of host data sections having the host Assigned discontinuous logical address; and - the memory controller, determines; t whether the plurality of segments are configured for the host file, and in response determines that the plurality of segments are configured to the host Storing a plurality of segments in a portion of the memory array to continuously locate the plurality of segments; wherein the memory controller uses the configuration information received from the host to determine Whether the segment of the plurality of segments is configured for the host slot. The non-volatile memory system of claim 21, wherein the file configuration information received from the host includes - or a plurality of file configurations The non-volatile memory system of claim 2, wherein the file configuration information received from the host includes one or more directory segments, such as the non-volatile memory system of claim 21, wherein The memory controller further determines that the end of the host file has been received and responds as H7059-990902.doc 25.1336856 closes the rights and schedules the file for garbage collection β one for use in a volatile memory array A non-volatile memory system for receiving a tribute received by a host, comprising: an interface 'receiving a plurality of host rights as a data section, the data section having a definition defined for the memory system a logical address configured by a logical address space, the interface further receiving configuration information about configuring the plurality of host files for the logical address space; and logic to entity translation & The decision has the location stored in the data section of one of the logical addresses, and the location of the plurality of host files is determined according to the logical address indicated by the configuration information to determine the location. 26. 27. 28 29. 30. A non-volatile memory system of a beta-sector 2, wherein the logic-to-physical translation circuit is not part of a memory controller. The non-volatile memory system of claim 25, wherein the interface Receiving configuration information about the segment prior to receiving the segment. The non-volatile memory system of claim 25, wherein the logical-to-physical translation circuit stores the segment in another segment of the host file Storing a location adjacent to a location entity. The non-volatile memory system of claim 25, wherein the logic-to-physical translation circuitry stores different files of the plurality of host files in the non-volatile memory. Within a different block of the array, a single block includes only the section of the host file. The non-volatile memory system of claim 25, wherein the configuration information is stored in the non-volatile memory array in a block of a section that is not used to store the plurality of host files, and 117059-990902.doc 1336856 is stored. Inside. 31. The non-volatile memory system of claim 25, wherein the interface further receives an indication of the end of the host file, and in response, the host building file stored in the memory segment array Sections are stored in the same block as another host file 117059-990902.doc