1336569 九、發明說明： 【發明所屬之技術領域】 本發明係關於產生DA轉換器（converter)之内部系統. 時脈之系統時脈產生電路，尤有關於一種用於D a轉換器之 系統時脈產生電路，用以從藉由△ Σ調變方式所獲得之1 位元數位輸入數據將類比輸出數據予以解調。又 【先前技術】 以採用△ Σ調變方式之f知之DA轉換器而言， 利文獻1所記載之裝置。 ^卜广將藉由ΔΣ調變方式所獲得之1位元數位數 康’予以轉換成取樣頻率不同之多位缝位數據之 的取樣頻率之比率（rate)轉換裝置丄 、 所記載者。 )轉換裝置而舌，已有專利文獻2 已有非專利文獻11336569 IX. Description of the Invention: [Technical Field] The present invention relates to an internal system for generating a DA converter. The system clock generation circuit of the clock, especially when used in a system for a Da converter The pulse generating circuit is configured to demodulate the analog output data from the 1-bit digital input data obtained by the △ Σ modulation method. Further, [Prior Art] A device described in Document 1 is known as a DA converter using a Δ Σ modulation method. ^Bu Guang will convert the 1-bit number obtained by the ΔΣ modulation method into a ratio of the sampling frequency of the multi-slot data with different sampling frequencies. ) conversion device and tongue, there is already a patent document 2
此外，以立體音響DA轉換器而言 所記載之DA轉換器。 [專利文獻1 ]Further, the DA converter described in the stereo DA converter is used. [Patent Document 1]
日本專利特開平9-186600號公報 [專利文獻2] 口令寻刊符開平9-148885號 [非專利文獻1J 職r-b_n公司產品目錄pcM 173 體音響DA轉換器。 PCM 1739、立 近年來，作為行動通信終 尤為顯著。在行衷置係以仃動電話的普及 動電話中為了處理聲音信號，係内建有聲 315889 5 1336569 音處理用之DA轉換器或AD轉換器。此外，聲音處理用之 Μ轉換器係㈣超取樣（QVer sampl丨ng)技術及△ Σ調變 技術，具有可變更△ Σ調變部之動作取樣比率之功能。 因此，藉由依據外部類比低通濾波器“卯，L〇w pass filter)之應用而變更取樣比率，即可實現高性能高功能的 Μ轉換器。因此，不僅行動電話，亦包括dvd_m、扒卜a， 甚至亦廣泛應用在家庭劇院系統Μ放大器等。 第5圖係顯示採用超取樣技術與△ Σ調變技術之μ 轉換器之構成圖，非專利文獻1中記載類似之電路。 〇上述電路係由輸入介面電路51，· 8倍超取樣數位濾波 器52 ;採用△ Σ調變方式之^轉換電路53 ;由低通濾波 器及輸出放大器組成之輸出電路54;以及對外料統時脈 曰應而產生預疋的内部系統時脈，並供給至個別的電路 51 52、53之系統時脈產生電路55所構成。 士輸入介面電路51係用以輸入供進行選擇L·聲道與R 鼙I之Μ時脈CRCK ;雙時脈（biclock)BCK ;以及藉由△ Σ °周麦方式獲得之1位元數位輸入數據DATA。 一以知用ΔΣ調變方式之DA轉換電路53之電路構成而 言，已有專利文獻1之第i圖所示之電路構成。 第6圖係顯示ad轉換電路之概略構成方塊圖，該AD 轉換電路係用以從類比輸入信號藉由△ Σ調變方式以獲得 1位π數位輸入數據。該AD轉換電路係由前置濾波電路 61 :加法電路62、積分器63、比較器64、延遲電路65、j 位兀DA轉換電路66所構成。另外’第6圖所示電路之詳 315889 6 1336569 細動作係為公知者，故在此省略詳細說明β 第7圖係顯示第6圖電路中出現之各種信號的關係波 形圖。 當藉由LR選擇信號LRCK(A)所選擇之L或R聲道之聲 音類比信號如（B)所示量化為16乃至24位元，再由未圖示 之8倍超取樣信號處理電路予以超取樣，並將（C)所示經量 化的類比信號輸入至前置濾波電路6丨時，即經由第6圖的 電路藉由ΔΣ調變作信號處理，並輸出1位元的數位輸入 數據成為（D)所示的波形。 該數位輸出係藉由輸入至輸入介面電路51作為第5 圖所不之數據DATA ’將原本的類比信號從輸出電路54予 以類比再生作為L聲道輸出或是R聲道輸出。 【發明内容】 [發明欲解決之問題] 然而，採用上述的超取樣技術及△ 2調變技術，並採 用第5圖所示DA轉換器，將第7圖（]))所示j位元數位輸 入數據予以解調為類比信號時，須視需要將供給至M轉換 電路53的内部系統時脈之時序周期予以變更。 通常’第5圖所示電路構成之DA轉換器係準備取樣比 率為10至2GGKHZ之基準頻率（fs)作為外部系統時脈，並 在系統時脈產生電路75内僅遞增預定的倍數（128/192/ 256/384/512/768)，並視需要作成可自動選擇該經遞增 之内部系統時脈而予以供給之構成。 如此，用以變更取樣頻率之取樣比率之技術，於專利 315889 7 1336569 ίΐΐ亦有記载’不過皆係藉由將外部系統時脈予以-安 僅遞乓預定之倍數而為之者。 上述任-情況均會有無法依據輸人數據而使主 生八有任意取樣比率之内部系統時脈的問題。 本發明係用以解決上述問題而研創者，其目的在提令 :用於da轉換ϋ之系統時脈產生電路，使藉由△ ς調雙 方式所獲得之丨位元數讀人數據，與具有任意取樣比_ 之内部系統時脈同步’而可解調成為類比。Japanese Patent Laid-Open Publication No. Hei 9-186600 [Patent Document 2] Password Searcher Kaiping No. 9-148885 [Non-Patent Document 1J job r-b_n product catalog pcM 173 body audio DA converter. PCM 1739, in recent years, is particularly remarkable as a mobile communication. In order to handle the sound signal, the DA 315889 5 1336569 DA converter or AD converter for sound processing is built in the mobile phone. In addition, the Μ converter system for sound processing (4) oversampling (QVer sampl丨ng) technology and Δ Σ modulation technology have the function of changing the action sampling ratio of the Δ Σ modulation unit. Therefore, by changing the sampling ratio according to the application of the external analog low-pass filter "卯, L〇w pass filter", a high-performance and high-performance chirp converter can be realized. Therefore, not only mobile phones but also dvd_m, 扒Further, it is widely used in home theater systems, amps, etc. Fig. 5 is a view showing a configuration of a μ converter using an oversampling technique and a Δ Σ modulation technique, and a circuit similar to that described in Non-Patent Document 1. The circuit is composed of an input interface circuit 51, an 8x oversampling digital filter 52, a conversion circuit 53 using a ΔΣ modulation method, an output circuit 54 composed of a low pass filter and an output amplifier, and an external source clock. The pre-existing internal system clock is generated and supplied to the system clock generation circuit 55 of the individual circuits 51 52 and 53. The input interface circuit 51 is used for input for selecting L·channel and R.鼙I Μ clock CRCK; double clock (biclock) BCK; and 1-bit digital input data DATA obtained by Δ Σ ° Zhou Mai method. A circuit of DA conversion circuit 53 using ΔΣ modulation method In terms of composition The circuit configuration shown in the first diagram of Patent Document 1 is shown in Fig. 6. Fig. 6 is a block diagram showing a schematic configuration of an AD conversion circuit for obtaining an offset from an analog input signal by a Δ Σ modulation method. Bit π digit input data. The AD conversion circuit is composed of a pre-filter circuit 61: an adder circuit 62, an integrator 63, a comparator 64, a delay circuit 65, and a j-bit ΔDA conversion circuit 66. Detailed description of the circuit 315889 6 1336569 The detailed operation is well known, so the detailed description of the β is shown here. Fig. 7 shows the relationship waveform of various signals appearing in the circuit of Fig. 6. When the signal is selected by LR LRCK(A) The sound analog signal of the selected L or R channel is quantized to 16 or 24 bits as shown in (B), and then oversampled by an 8 times oversampling signal processing circuit (not shown), and (C) is shown. When the quantized analog signal is input to the pre-filter circuit 6丨, the circuit of FIG. 6 is subjected to signal processing by ΔΣ modulation, and the 1-bit digital input data is output as the waveform shown in (D). The digital output is input to the input interface circuit 51. The data DATA ' of the fifth figure is analogously reproduced from the output circuit 54 as an L channel output or an R channel output. [Summary of the Invention] [The problem to be solved by the invention] However, the above-mentioned super Sampling technology and Δ 2 modulation technology, and using the DA converter shown in Figure 5, demodulating the j-bit digital input data shown in Figure 7 (])) into an analog signal, it shall be supplied to the The timing period of the internal system clock of the M conversion circuit 53 is changed. Generally, the DA converter of the circuit shown in Fig. 5 prepares the reference frequency (fs) of the sampling ratio of 10 to 2 GGKHZ as the external system clock, and The system clock generation circuit 75 is incremented by only a predetermined multiple (128/192/256/384/512/768), and is configured to automatically select the incremented internal system clock as needed. Thus, the technique for varying the sampling rate of the sampling frequency is also described in the patent 315 889 7 1 336 569 </ RTI> but is by the fact that the external system clock is given a multiple of the predetermined number. In any of the above-mentioned cases, there is a problem that the internal system clock of the arbitrary sampling rate cannot be made according to the input data. The present invention is a researcher for solving the above problems, and the purpose thereof is to propose a system clock generation circuit for a da conversion system, which is to read the human data by the number of bits obtained by the Δ ς double mode, and The internal system clock synchronization with any sampling ratio _ can be demodulated into an analogy.
[解決問題之方案][Solution to solve the problem]
本發明之系統時脈產生電路，係一種用於DA轉換哭之 系統時脈產生電路’該D/A轉換器係使藉…調變；式 所獲得之1位元數位輸人數據與内料、統時脈同步，並解 調成類比輸出數據而予以輸出，其特徵為具備：叶數器電 路’輸人具有預定之錢頻率脈與LR時脈 (LRCLK) ’並將LR時脈之丨周期中所含之外部系統時脈之 時脈數予料數；時序產生電路，依據由計數器電路所計 數之計數值，產生藉由預定之間隔抽出時序而將外部系統 時脈予以間隔抽出的遮蔽信號；以及遮蔽電路，藉由遮蔽 信號將外部⑽時料以遮蔽’並將經遮蔽之部份的時脈 予以間隔抽出再產生内部系統時脈。 此外，本發明之系統時脈產生電路之特徵在，依據外 部系統時脈之重複頻率，將間隔抽出時序經變更及/或分 頻後之外部系統時脈作為外部系統時脈使用。The system clock generation circuit of the invention is a system clock generation circuit for DA conversion crying. The D/A converter is used to adjust the data of the 1-bit digital input and the internal material obtained by the method. Synchronous clock synchronization, and demodulation into analog output data for output, characterized by: leaf processor circuit 'input has a predetermined money frequency pulse and LR clock (LRCLK) 'and LR clock The number of clocks of the external system clock included in the cycle is predetermined; the timing generating circuit generates an occlusion of the external system clock by intermittently extracting the timing by a predetermined interval according to the count value counted by the counter circuit. The signal; and the masking circuit, by masking the signal, the external (10) material is shielded and the clocked portion of the clock is intermittently extracted to generate an internal system clock. Further, the system clock generating circuit of the present invention is characterized in that the external system clock whose interval is extracted and/or frequency-divided is used as an external system clock according to the repetition frequency of the external system clock.
此外，本發明之系統時脈產生電路之特徵在將lR 315889 8 1336569 時脈之1周期予以均等分割，按個別的分割領域將計數值 予以分配配置，並依據配置而產生遮蔽信號。 此外，本發明之系統時脈產生電路之特徵在，外部系 統時脈之重複頻率可在基準取樣比率（fs)之256乃至 倍範圍内任意選擇。 此外，本發明之系統時脈產生電路之特徵在，間隔抽 出時序係依據被間隔抽出的時脈數，於〇乃至15時脈時設 定為每16時脈，於16乃至31時脈時設定為每8時脈，ς 3^至—63時脈時設定為每4時脈，於64乃至ΐ27時脈時 設定為每2時脈’於128乃至255時脈時設定為每（時脈。 此外，本發明又提供内建有系統時脈產生電路之Μ 轉換器，以及内建有該DA轉換器之行動電話。 【實施方式】 [發明之實施形態] 第1圖係顯示本發明之一實施形態之系統時脈產生 路之構成方塊圖。 該電路係由輸入LR時脈LRCLK、雙時脈BCLK、】位元 數位輸入數據DATA-1N及外部系統時脈SYSCLK之計數器電 路=;時序產生電路12;以及遮蔽電路14所構成，用以 獲得預定之内部系統時脈SYS_CLK作為遮蔽電路以之 出。 計數器電路10係用以計數LR時脈在i 部系統時脈之時脈數。 ， 時序產生電路12係依據由計數器電路1 〇所計數之計 315889 9 1336569 =產生藉由預定之時序將外部系統時脈作間 遮心戒，並將該信號供給至遮蔽電路14。 的 遮敝電路14係輸入有來自時序產生 號；來自計數器電路H)的外料统料^V2的遮敝仏 系統時脈。 ❻統時脈’或是經2分頻之 自計數器電路1〇所供給之外部系統時脈、或經 之外部系統時脈藉由遮蔽信號予 n ’、 時脈作間隔抽出，再由遮蔽電路"輸出作為内部系統時 脈。採用此被輸出之内部系統時脈而驅動 圖另第：圖、第3圖係說明第1圖之電路動作之時序皮形 圖。另外，第3圖係將第2圖LR時 以放大顯示之圖。 吁脈之肖期份的動作予 如第2圖所示，以外都备站主p 卜邛系統時脈而言，係產生基準取 ==5ΓΜ026倍的時脈。再者，於該外部系統 的外= 6至1024倍之中，可作成具有任意頻率 ==系統~脈。因此，依據以第1圖之計數器電路10 預定之間隔抽出時序將外部系統時 脈作間隔抽出，以產生第2圖（6)所示内部系統時脈。 另外，須將用以抑制失真率下降所作間隔抽出的時 序’在LR時脈之！周期中予以均等分配。因此，第2圖所 不之例係使1周期作成區域[卜^之^分割而間隔抽 出的時脈，在該等區域内得以均等的分配。 作 ’尺說月第1圖所示系統時脈產生電路之電路動 315889 1336569 士叶數器電路10係將LR時脈在1周期（ifs)中的外部系 統％脈之上昇數（時脈數）進行計數。然後，將其結果六山、 時序產生電路12。 夂 计數數為256至511fs時，依原狀將外部系統時脈供 給至時序產生電路以。此外，計數數為512至l〇23fs時了 將2刀頻之系統時脈供給至時序產生電路12。 /時序產生電路12係由LR時脈在1周期（lfs)中的外部 ^日!；之計數數’產生用以將該外部系統時脈作間隔抽 々、4序。由於間隔抽出之時序須在1周期中盡可能予以 句等刀配，因此將間隔抽出之時脈數作4等分，如第 所示，均等分配為區域A、B、C、D。 另外，將依據必要的間隔抽出數而間隔抽出的基本時 序予以设定如下。 間隔抽出數 〇至15時脈 每16時脈產生 16至31時脈 每8時脈產生 32至63時脈 每4時脈產生 64至127時脈 每2時脈產生 128至255時脈每1時脈產生 朊，二外’此處所指時脈係為由計數器電路10供給之時 眭’至511fs時係顯示外部系統時脈，512幻023fs 時則顯示2分頻之系統時脈。 315889 11 之外部系統時脈）予以遮蔽而進行間隔抽出。採用以該遮蔽 電路14所產生的信號為内部系統時脈，作為供△ ς處理之· 内部系統時脈之用。 第4圖係顯示第1圖所示系統時脈產生電路中的時序 產生電路12之詳細構成電路圖。 时時序產生電路12係由時脈選擇器電路12卜區域計數 =控制電路122、區域Α計數器123、區域Β計數器124、 區域c計數器125、區域D計數器126及時脈致能產生 路127所構成。 鲁 時脈選擇器電路121係根據lr時脈在i周期中之外部 系統時脈之計數結果’而用於選擇外部系統時脈或2分頻-之時脈之任一者之輸出。 . 區域計數器控制電路122係用以控制各區域A計數器 U3至126之計數的開始或結束。 區域A計數器123係於區域八區間、區域B計數器124 係於區❹區間、區域C計數器125係於區域C區間、以 及區域D計數器126係於區域D區間，分別用以產生時脈 致能信號之基準計數器。 時脈致能產生電路127係針對來自區域計數器123至 126之時脈u5號，進行用以間隔抽出時脈之致能信號 的產生’並將該信號輸出至遮蔽電路14作為遮蔽信號。 時脈致能產生電路127所產生的遮蔽信號以及時脈選 擇器電路121所選擇的信號，藉由遮蔽電路14相乘以產生 内部系統時脈。 315889 1336569 [發明之功效] 之頻率成為任意的頻 1〇24:Π二Φ本發明可在基準取樣比率(fs)從256至 1024倍之fe圍中選擇内部系統時脈 率 =此，依據數位輸人數據，即可自由選擇M轉換 内部系統時脈’因此可大幅緩和使用上的限制。 此外，藉由將外部系統時脈之作間隔抽出的時序於 LR時脈之1周期内予以均等分 j寸刀配，即可控制失真率的 低0 另外’本發明係可廣泛作為DA轉換器用的時序時脈產 生電路之用，舉凡内建該等DA#換器之行動電話及勝 、_-α自不待言’亦可廣泛應用在家庭劇院系統、AV 放大器等。 【圖式簡單說明】 第1圖係顯示本發明之一實施形態之系統時脈產生 路之構成圖。 第2圖（a)至（e)係第丨圖所使用各種信號的時序圖。 第3圖係放大第2圖所顯示之時序圖。 路圖 第4圖係顯示第1圖所示時序產生電路之詳細構成電 圖 成圖 第5圖係顯示採用△ Σ調變方式之da轉換器之構成 第6圖係顯示採用△ Σ調變方式之AD轉換器之電路構 315889 13 第7圖（A)至（D)係第 圖0 【主要元件符號說明】 10 計數器電路 14 遮敝電路 52 8倍超取樣數位濾波 54 輸出電路 61 前置濾波器電路 63 積分器 65 延遲電路 75 系統時脈產生電路 122 區域計數器控制電路 124 區域B計數器 126 區域D計數器 圖所使用之各種波形之時序 12 時序產生電路 51 輸入介面電路 53 DA轉換器 55 系統時脈產生電路 62 加法電路 64 比較器 66 1位元Μ轉換電路 121 時脈選擇器電路 123 區域Α計數器 125 區域C計數器 127 時脈致能產生電路 315889 14In addition, the system clock generating circuit of the present invention is characterized in that the 1R period of the lR 315889 8 1336569 clock is equally divided, the count value is allocated and configured according to the individual divided areas, and the masking signal is generated according to the configuration. Further, the system clock generating circuit of the present invention is characterized in that the repetition frequency of the external system clock can be arbitrarily selected within a range of 256 or even times the reference sampling ratio (fs). Further, the system clock generation circuit of the present invention is characterized in that the interval extraction timing is set to be every 16 clocks at the time of the 〇 to 15 clocks, and is set to be 16 or 31 clock pulses, depending on the number of clocks that are extracted at intervals. Every 8 clocks, ς 3^ to -63 clocks are set to every 4 clocks, and 64 to ΐ27 clocks are set to every 2 clocks' at 128 or even 255 clocks (per clock). Further, the present invention provides a 转换器 converter having a system clock generation circuit built therein, and a mobile phone having the DA converter built therein. [Embodiment] [Embodiment of the Invention] Fig. 1 shows an implementation of the present invention. The block diagram of the system clock generation path of the form. The circuit is a counter circuit of input LR clock LRCLK, double clock BCLK, bit input data DATA-1N and external system clock SYSCLK =; timing generation circuit 12; and a masking circuit 14 is configured to obtain a predetermined internal system clock SYS_CLK as a masking circuit. The counter circuit 10 is used to count the number of clocks of the LR clock in the i system clock. Circuit 12 is based on the counter Circuit 1 计数 counts 315889 9 1336569 = Generates an external system clock by a predetermined timing, and supplies the signal to the masking circuit 14. The concealing circuit 14 is input with a timing generation number. The concealing system clock of the external material ^V2 from the counter circuit H). The system clock' or the external system clock supplied by the counter circuit 1〇 or the external system clock is masked by n', the clock is intermittently extracted, and then the mask circuit is used. " Output as the internal system clock. The internal system clock is outputted by the output. Fig. 3 and Fig. 3 are timing charts showing the circuit operation of Fig. 1. In addition, Fig. 3 is an enlarged view of the second drawing LR. The action of the period of the vouchers is as shown in Fig. 2, except for the clock of the main station of the standby station, the clock with the reference ==5ΓΜ026 times is generated. Furthermore, among the external systems of the external system = 6 to 1024 times, it can be made to have an arbitrary frequency == system ~ pulse. Therefore, the external system clock is extracted at intervals according to the predetermined extraction timing of the counter circuit 10 of Fig. 1 to generate the internal system clock shown in Fig. 2 (6). In addition, the timing for extracting the interval for suppressing the decrease in the distortion rate must be at the LR clock! Equally distributed during the cycle. Therefore, the example shown in Fig. 2 is a clock in which the one-cycle creation region is divided and spaced, and is equally distributed in the regions. The circuit of the system clock generation circuit shown in the first figure of the month is 315889 1336569. The number circuit of the external system of the LR clock in one cycle (ifs) (the number of clocks) ) to count. Then, the result is a six-peak, timing generation circuit 12.外部 When the number of counts is 256 to 511 fs, the external system clock is supplied to the timing generation circuit as it is. Further, when the number of counts is 512 to 10 〇 23 fs, the system clock of 2 chips is supplied to the timing generating circuit 12. The timing generation circuit 12 is generated by the external number of LR clocks in one cycle (lfs), and the number of counts is used to divide the external system clocks by four steps. Since the timing of the interval extraction must be matched as much as possible in one cycle, the number of clocks extracted at intervals is divided into four equal parts, and as shown in the figure, equally divided into regions A, B, C, and D. Further, the basic timing of the interval extraction based on the necessary number of intervals is set as follows. Interval extraction of several 〇 to 15 clocks per 16 clocks produces 16 to 31 clocks every 8 clocks produces 32 to 63 clocks every 4 clocks produces 64 to 127 clocks every 2 clocks produces 128 to 255 clocks per 1 The clock generates 朊, and the second time 'when the clock is supplied from the counter circuit 10 is 眭' to 511fs, the external system clock is displayed, and when 512 幻 023fs is displayed, the system clock of 2 is displayed. The external system clock of 315889 11 is shielded and extracted at intervals. The signal generated by the masking circuit 14 is used as an internal system clock, which is used as an internal system clock for the Δ ς processing. Fig. 4 is a circuit diagram showing the detailed configuration of the timing generating circuit 12 in the system clock generating circuit shown in Fig. 1. The timing generation circuit 12 is composed of a clock selector circuit 12, a region count = control circuit 122, a region Α counter 123, a region Β counter 124, a region c counter 125, a region D counter 126, and a pulse generation circuit 127. The Lu clock selector circuit 121 is used to select the output of either the external system clock or the divide-by-2 clock based on the count result of the external system clock in the i-cycle at the lr clock. The area counter control circuit 122 is for controlling the start or end of the counting of the respective area A counters U3 to 126. The area A counter 123 is in the area eight section, the area B counter 124 is in the area section, the area C counter 125 is in the area C section, and the area D counter 126 is in the area D section, respectively for generating the clock enable signal. The base counter. The clock enable generating circuit 127 performs generation of an enable signal for intermittently extracting the clock for the clock u5 from the area counters 123 to 126 and outputs the signal to the mask circuit 14 as a mask signal. The masking signal generated by the clock enable generating circuit 127 and the signal selected by the clock selector circuit 121 are multiplied by the masking circuit 14 to generate an internal system clock. 315889 1336569 [Effects of the invention] The frequency becomes an arbitrary frequency 1〇24: Π2 Φ The invention can select the internal system clock rate in the range of the reference sampling ratio (fs) from 256 to 1024 times = this, according to the digit By entering the data, you can freely choose the M conversion internal system clock' so you can greatly ease the restrictions on use. In addition, by dividing the timing of the external system clock interval by the equal division of the LR clock, the distortion rate can be controlled to be low. In addition, the present invention can be widely used as a DA converter. The use of the timing clock generation circuit, the mobile phone with the built-in DA# converter and the win, _-α can not be said 'can be widely used in home theater systems, AV amplifiers and so on. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a system clock generation path according to an embodiment of the present invention. Fig. 2 (a) to (e) are timing charts of various signals used in the second drawing. Fig. 3 is an enlarged timing chart shown in Fig. 2. Figure 4 of the road diagram shows the detailed construction of the timing generation circuit shown in Figure 1. The fifth diagram shows the composition of the da converter using the Δ Σ modulation method. Figure 6 shows the △ Σ modulation method. Circuit diagram of AD converter 315889 13 Figure 7 (A) to (D) is the first figure 0 [Main component symbol description] 10 Counter circuit 14 Concealer circuit 52 8 times oversampling digital filter 54 Output circuit 61 Prefilter Circuit circuit 63 integrator 65 delay circuit 75 system clock generation circuit 122 area counter control circuit 124 area B counter 126 time series of various waveforms used in the area D counter map 12 timing generation circuit 51 input interface circuit 53 DA converter 55 system time Pulse generation circuit 62 addition circuit 64 comparator 66 1 bit Μ conversion circuit 121 clock selector circuit 123 area Α counter 125 area C counter 127 clock enable generation circuit 315889 14