1335564 * -,,, .九、發明說明： 【發明所屬之技術領域】 本發明係關於一種移位暫存器及採用該移位暫存器之 液晶顯不裝置。 【先前技術】 目前薄膜電晶體（Thin Film Transistor，TFT)液晶顯示 ®裝置已逐漸成為各種數位產品之標準輸出設備，然，其需 要設計適當的驅動電路以保證其穩定工作。 通常，液晶顯示裝置的驅動電路包括一資料驅動電路 • 及一掃描驅動電路。資料驅動電路用於控制每一像素單元 . 之顯示輝度，掃描驅動電路則用於控制薄膜電晶體之導通 與截止。二驅動電路均應用移位暫存器作為核心電路單 元。通常，移位暫存器係由複數移位暫存單元串聯而成， 且前一移位暫存單元之輸出訊號為後一移位暫存單元之輸 籲入訊號。 請參閱圖1，係一種先前技術移位暫存器之移位暫存 單元之電路圖。該移位暫存單元100包括一第一時鐘反相 電路110、一換流電路120及一第二時鐘反相電路130。該 移位暫存單元 100之各電路均由 PMOS(P-channel Metal-Oxide Semiconductor，P溝道金屬氧化物半導體）型 電晶體組成，每一 PM0S型電晶體均包括一閘極、一源極 及一汲極。 該第一時鐘反相電路110包括一第一電晶體Ml、一 1335564 ·,., •第二電晶體M2、一第三電晶體M3、一第四電晶體M4、 一第一輸出端V01及一第二輸出端V02。該第一電晶體 Ml之閘極接收該移位暫存單元100之前一移位暫存單元 之輸出訊號VS，其源極接收來自外部電路之高電平訊號 VDD，其汲極連接至該第二電晶體M2之源極。該第二電 晶體M2之閘極及其汲極接收來自外部電路之低電平訊號 VSS。該第三電晶體M3及該第四電晶體M4之閘極均接收 來自外部電路之反相時鐘訊號二者之汲極分別作為該 籲第一時鐘反相電路110之第一輸出端V01及第二輸出端 V02，且該第三電晶體M3之源極連接至該第一電晶體Ml 之汲極，該第四電晶體M4之源極連接至該第一電晶體Ml 之閘極。 該換流電路120包括一第五電晶體M5、一第六電晶 體M6及一訊號輸出端VO。該第五電晶體M5之閘極連接 至該第一輸出端V01，其源極接收來自外部電路之高電平 訊號VDD，其汲極連接至該第六電晶體M6之源極。該第 鲁六電晶體M6之閘極連接至該第二輸出端V02，其汲極接 收來自外部電路之低電平訊號VSS，其源極係該移位暫存 單元100之訊號輸出端VO。 該第二時鐘反相電路130包括一第七電晶體M7、一 第八電晶體M8、一第九電晶體M9及一第十電晶體M10。 該第七電晶體M7之閘極連接至該訊號輸出端VO，其源極 接收來自外部電路之高電平訊號VDD，其汲極連接至該第 八電晶體M8之源極。該第八電晶體M8之閘極及其汲極 均接收來自外部電路之低電平訊號VSS。該第九電晶體 1335564 ,., * .M9之源極連接至該第一輸出端VOl，其閘極接收來自外 部電路之時鐘訊號CK，其汲極連接至該第七電晶體M7 之汲極。該第十電晶體之閘極接收外部電路之時鐘訊號 CK，其源極連接至該第二輸出端V02，其汲極連接至該訊 號輸出端V0。 請一併參閱圖2，係該移位暫存單元100之工作時序 圖。在T1時間内，該前一移位暫存單元之輸出訊號VS由 高電平跳變為低電平，反相時鐘訊號CK由低電平跳變為高 籲電平，則使該第三電晶體M3及該第四電晶體M4截止， 進而使該第一時鐘反相電路110斷開。而該時鐘訊號CK 由高電平跳變為低電平，使該第九電晶體M9及該第十電 晶體M10導通，進而使該第二時鐘反相電路130導通，而 .該訊號輸出端VO初始狀態之高電平經該第十電晶體 M10，使該第六電晶體M6截止，而該第八電晶體M8輸出 之低電平經由該第九電晶體M9，使該第五電晶體M5導 通，進而使其源極之高電平訊號VDD輸出至該訊號輸出 •端VO’故該訊號輸出端VO保持rfj電平輸出。 在T2時間内’該反相時鐘訊號CK由南電平跳變為低 電平，則使該第三電晶體M3及該第四電晶體M4導通， 進而使該第一時鐘反相電路110導通。而該時鐘訊號CK 由低電平跳變為高電平，則使該第九電晶體M9及該第十 電晶體M10截止，進而使該第二時鐘反相電路130斷開。 該輸入訊號VS由尚電平跳變為低電平 > 則使該第一電晶 體Ml導通，其源極之高電平VDD經該第三電晶體M3截 止該第五電晶體M5,且該輸入訊號VS之低電平經該第四 1335564 •電晶體M4導通該第六電晶體M6，使該訊號輸出端VO輸 出低電平。 在T3時間内，該反相時鐘訊號CK由低電平跳變為高 電平’則使該第三電晶體M3及該第四電晶體M4截止， 進而使該第一時鐘反相電路11〇斷開。而該時鐘訊號CK 由尚電平跳變為低電平，使該第九電晶體M9及該第十電 曰曰體M10導通，進而使該第二時鐘反相電路13〇導通。該 訊號輸出端vo之低電平導通該第七電晶體M7，其源極之 .冋電平經該第九電晶體M9截止該第五電晶體M5。同時， 該訊號輪出端vo之低電平亦經該第十電晶體M1〇導通該 第六電晶體M6,該第六電晶體⑽之汲極低電平使該訊號 輸出端VO保持低電平輸出。 在T4時間内，該反相時鐘訊號茂由高電平跳變為低 電平貝使該第二電晶體M3及該第四電晶體導通， =該第一時鐘反相電路11〇導通。而該時鐘訊號Μ ^低電平跳變為高電平’使該第九電晶體⑽及該第十電 曰曰體：10截止’進而使該第二時鐘反相電路斷開。輸 入訊號VS之高電平經該第四電晶體 體M6,而該第二電晶體 戳/弟/、電日日 M3導㈣笛電平經該第三電晶體 M3導通Μ五電㈣M5 ’使其源極 號輸出端VO,使該訊轳銓# # 电十翻出至該訊 高電平。 訊遽輸出端V〇之輸出由低電平跳變為 從作時序圖可見，該移位暫存單元丨 义 位暫存單元於T1時間與T2時間-= 移位暫存單元！⑽於Τ2 I _電千訊遗’而該 -、Τ3時間内輸出低電平訊 1335564 t •號，該二低電平訊號在T2時間存在重疊情況。而該低電 平訊號為有效訊號，即由該複數移位暫存單元1〇〇構成的 移位暫存器輸出的各級有效訊號互相之間有重疊。 另外，該移位暫存器可應用於液晶顯示裝=以及其他 數位電子產品中。例如液晶顯示裝置的資料驅動電路捕 描驅動電路需要該移位暫存器實現列掃描或行掃描的功 ，。然丄該移位暫存器輸出的各級有效訊號互相之間有重 璺，當貧料驅動電路或掃描驅動電路進行逐行 時，會存在相鄰二列或行同時進行掃描之現象，從而導^ 載入訊號產生相互干擾。 【發明内容】 有鑑於此，提供一種輸出有效訊號無重疊之 器實為必要。 子 另提供種可避免訊號干擾之液晶顯示裝置亦為必 要 一種移位暫存器，其包括複數移位暫存單元，每一移 一暫存單元均文外部電路的時鐘訊號、前一級移位暫存單 =之，出訊號及後一級移位暫存單元之反相輸出訊號控 母移位暫存單元包括一第一上拉電路、一第二上拉 電路、-第—下拉電路、—第二下拉電路、—第—反相電 路、一第二反相電路及一輸出電路。該第一、第二上拉電 路第一、第二下拉電路及該輸出電路具有—第一公共節 點一該第一上拉電路、第二下拉電路及該輸出電路具有— 第一公共節點，該第一反相電路連接在該第一、第二公共 11 1335564 .f點之間。該第一、第二上拉電路為該第一公共節點提供 咼電平訊號，該第一、第二下拉電路為該第一公共節點提 供低電平減，該輸出電路在該第―、第二公共節點的控 制下選擇輸出時鐘訊號或低電平訊號，該第二反相電路將 輸出電路的輸出訊號反相後輸出。 種液晶顯示裝置，其包括 ”一… 欣日日顯不面板、一貢料 驅動電路及-掃描驅動電路，該資料驅動電路為該液晶顯 =面板提供資料訊號，該掃描驅動電路為該液晶顯示面板 提供掃描訊號。該資料驅動電路及該掃描驅動電路分別包 括-移位暫存器以控制資料訊號與掃描訊號之輸出時序， 該移位暫存H包括複數移位暫存單元，每—移位暫存 電路的時鐘訊號、前一級移位暫存單元之輸出訊 暫νί 了位暫存單元之反相輸出訊號控制。每-移位 子：70包括一第一上拉電路、-第二上拉電路、-第- 相雷踗万^„ 一第一反相電路、一第二反 一輸出電路’該第_、第二上拉電路、第一、第 :電路m出雷r/有—第一公共節點，該第一上 點。”二r二輸出電路具有一第二公共節 該第:、第二公共節點之間’ 號，兮第ί 為該第—公共節點提供高電平訊 替。#^拉電路為該第—公共節點提供低電平 幹出^=出電路在該第一、第二公共節點的控制下選擇 輪出時鐘訊號或低電平訊號，"』下、擇 的輸出訊號反相後輸出。以―反相電路將輸出電路 與先前技術相比，從工作時序圖可見，各級移位暫存 12 1335564 ·,.. .早元輸出的南電平訊號互相之間均沒有重豐’而該南電平 訊號為有效訊號，即本發明移位暫存器輸出的各級有效訊 號互相之間沒有重疊。 與先前技術相比，本發明移位暫存器輸出的各級有效 訊號互相之間沒有重疊，因此該掃描驅動電路或資料驅動 電路在進行行掃描或列掃描時，其輸出掃描訊號或資料訊 號不會產生訊號干擾，從而提高了本發明液晶顯示裝置的 顯示效果。 【實施方式】 請參閱圖3，其係本發明移位暫存器較佳實施方式之 結構示意圖。該移位暫存器20包括複數結構相同之移位暫 .存單元200，該複數移位暫存單元200依次串聯。每一移 位暫存單元200包括一時鐘訊號輸入端CK、一第一輸入 端VIN1、一第二輸入端VIN2、一輸出端VOUT、一反相 輸出端VOUTB、一高電平輸入端VH及一低電平輸入端 _ VL。每一移位暫存單元200之時鐘訊號輸入端CK接收外 部電路（圖未示）之時鐘訊號CK，其高電平輸入端VH接收 外部電路（圖未示）的高電平訊號VDD，其低電平輸入端VL 接收外部電路（圖未示）的低電平訊號VSS。其第一輸入端 VIN1電連接至前一級移位暫存單元200之輸出端VOUT， 其第二輸入端VIN2電連接至後一級移位暫存單元200之 反相輸出端VOUTB，其輸出端VOUT電連接至後一級移 位暫存單元200之第一輸入端VIN1，其反相輸出端 VOUTB電連接至前一級移位暫存單元200之第二輸入端 13 1335564 ·... VIN2。即前一級移位暫存單元200之輸出訊號為後一級移 位暫存單元200之第一輸入訊號，後一級移位暫存單元200 之反相輸出訊號為前一級移位暫存單元200之第二輸入訊 號，且每一移位暫存單元同時由外部電路的時鐘訊號、高 電平訊號及低電平訊號控制。 請參閱圖4,其係圖3之移位暫存單元之電路示意圖。 該移位暫存單元200包括一第一上拉電路31、一第二上拉 電路32、一第一下拉電路33、一第二下拉電路34、一第 • 一反相器35、一輸出電路36及一第二反相器37。該第一 上拉電路31、第二上拉電路32、第一下拉電路33、第二 下拉電路34及該輸出電路36具有一第一公共節點P1。該 第一上拉電路31、第二下拉電路33及該輸出電路36具有 .一第二公共節點P2。該第一反相器35連接在該第一、第 二公共節點PI、P2之間，該第一、第二上拉電路31、32 為該第一公共節點P1提供高電平訊號，該第一、第二下 拉電路33、34為該第一公共節點P1提供低電平訊號。該 籲第一上拉電路31受該第一輸入端VIN1及該第二公共節點 P2控制，該第二上拉電路32受該第一、第二輸入端VIN1' VIN2控制，該第一下拉電路33受該第一輸入端VIN1控 制，該第二下拉電路34受該第二輸入端VIN2及該第二公 共節點P2控制。該輸出電路36在第一、第二公共節點P1、 P2的控制下選擇輸出時鐘訊號CK或低電平訊號VSS至該 輸出端VOUT，該第二反相器37將輸出端VOUT的訊號 反相後輸入至該反相輸出端VOUTB。 該第一上拉電路31包括一第一電晶體Ml及一第二電 14 1335564 ·... .晶體M2，該第一、第二電晶體Ml、M2係PMOS型電晶 體。該第一電晶體Ml的閘極電連接該第一輸入端VIN1， 其源極電連接該高電平輸入端VH，其汲極電連接該第二 電晶體M2的源極。該第二電晶體M2的閘極電連接該第 二公共節點P2，其汲極電連接該第一公共節點P1。 該第二上拉電路32包括一第三電晶體M3及一第四電 晶體M4，該第三、第四電晶體M3、M4係PMOS型電晶 體。該第三電晶體M3的閘極電連接該第一輸入端VIN1， 籲其源極電連接該高電平輸入端VH，其汲極電連接該第四 電晶體M4的源極。該第四電晶體M4的閘極電連接該第 二輸入端VIN2，其汲極電連接該第一公共節點P1。 • 該第一下拉電路33包括一第五電晶體M5,該第五電 .晶體M5係NMOS型電晶體。該第五電晶體M5的閘極電 連接該第一輸入端VIN1，其源極電連接該第一公共節點 P1，其汲極電連接該低電平輸入端VL。 該第二下拉電路34包括一第六電晶體M6及一第七電 _晶體M7，該第六、第七電晶體M6、M7係NMOS型電晶 體。該第六電晶體M6的閘極電連接該第二公共節點P2， 其源極電連接該第一公共節點P1，其汲極電連接該第七電 晶體M7的源極，該第七電晶體M7的閘極電連接該第二 輸入端VIN2，其汲極電連接該低電平輸入端VL。 該輸出電路36包括一第八電晶體M8、一第九電晶體 M9、一第十電晶體M10及一缓衝器361，該第八電晶體 M8係PMOS型電晶體，該第九、第十電晶體M9、M10係 NMOS型電晶體，該缓衝器361主要用於保持該移位暫存 15 1335564 ·.，. 單元200之輸出波形，避免輸出波形失真。該第八電晶體 M8的閘極電連接該第一公共節點P1，其源極電連接該時 鐘訊號輸入端CK，其汲極電連接該第十電晶體M10的源 極。該第九電晶體M9的閘極電連接該第二公共節點P2， 其源極電連接該時鐘訊號輸入端CK，其汲極電連接該第 十電晶體M10的源極。該第十電晶體M10的閘極電連接 該第一公共節點P1，其汲極電連接該低電平輸入端VL， 其源極藉由該缓衝器361電連接該輸出端VOUT。 • 請一併參閱圖5，其係圖3中移位暫存器20之時序示 意圖。用η表示某一級移位暫存單元200，其前一級及後 一級分別用η-1、η + 1表示。 在Τ1時間内，對於第η級移位暫存單元200，第一輸 . 入端VIN1接收第η-1級輸出訊號V01為高電平，則第一 電晶體Ml截止，第三電晶體M3截止，第五電晶體Μ5 導通。第一公共節點P1被下拉為低電平，則第八電晶體 M8導通、第十電晶體M10截止。第一公共節點P1的低電 鲁平經過該第一反相器35後變爲高電平，即第二公共節點 P2為高電平，則第二電晶體M2截止，第六電晶體M6導 通，第九電晶體M9導通。第二輸入端VIN2接收第η + 1 級反相輸出端的輸出訊號V03為尚電平’則第四電晶體Μ4 截止，第七電晶體Μ7導通，第一公共節點Ρ1穩定保持低 電平訊號，則第二公共節點Ρ2穩定保持南電平訊號。時 鐘訊號CK分別通過第八電晶體Μ8及第九電晶體Μ9分二 路輸入至該緩衝器361，此時該時鐘訊號CK為低電平， 故輸出端VOUT的輸出訊號V02為低電平。 16 1335564 • ·,.. 在T2時間内，對於第η級移位暫存單元200，第一輸 入端VIN1接收第η-1級輸出訊號V01為低電平，則第一 電晶體Ml導通，第三電晶體M3導通，第五電晶體Μ5 截止，因第二公共節點P2仍保持高電平訊號，則第二電 晶體M2截止，第六電晶體M6導通，第九電晶體M9導通。 第二輸入端VIN2接收第n + 1級反相輸出端的輸出訊號 為高電平，則第四電晶體M4截止，第七電晶體M7 導通，第一公共節點Ρ1繼續保持低電平訊號，則第八電 籲晶體Μ8導通、第十電晶體Μ10截止，同時第二公共節點 Ρ2穩定保持高電平訊號。時鐘訊號CK分別通過第八電晶 體Μ8及第九電晶體Μ9分二路輸入至該緩衝器361，此時 • 該時鐘訊號CK為高電平，故輸出端VOUT的輸出訊號V02 為高電平。 在Τ3時間内，對於第η級移位暫存單元200，第一輸 入端VIN1接收第η-1級輸出訊號V01為低電平，則第一 電晶體Ml導通，第三電晶體M3導通，第五電晶體Μ5 _截止。第二輸入端VIN2接收第n + 1級反相輸出端的輸出 訊號為低電平，則第四電晶體M4導通，第七電晶體 Μ7截止，第一公共節點Ρ1被上拉為高電平訊號，則第八 電晶體Μ8截止、第十電晶體Μ10導通。第一公共節點Ρ1 的高電平經過該第一反相器35後變爲低電平，即第二公共 節點Ρ2為低電平，則第二電晶體M2導通，第六電晶體 Μ6截止，第九電晶體Μ9截止。低電平訊號通過該第十電 晶體Μ10後輸入至該緩衝器361，故輸出端VOUT的輸出 訊號V02為低電平。 17 1335564 • · · · '在丁4時間内，對於第n級移位暫存單元200,第一輸 入端VIN1接收第nj級輸出訊號v〇1為低電平，則第一 電晶體Ml導通，第三電晶體M3導通，第五電晶體… 截止’因第二公共節點P2仍保持低電平訊號，則第二電 晶體M2導通’第六電晶體M6截止，第九電晶體M9截止。 第A /、gf點P1被上拉為高電平訊號，則第八電晶體㈣ 截止、第十電晶體M10導通。第二輸人端VIN2接收第η + ι 級反相輸出端的輸出訊號涵為高電平，則第四電晶體⑽ 截止’第七電晶體M7導通，第一公共節點ρι穩定保持高 電平訊號，則第二公共節點p2穩定保持低電平訊號。低 電平訊號通過該第十電晶體議後輸人至該緩衝器3⑴ •故輸出端νουτ的輸出訊號v〇2為低電平。 與先前技術相比，從工作時序圖可見，第n i級移位 暫存單Γ聊僅在T1時間内輸出高電平訊號，第n級移 位暫存單元200僅在T2時間内輸出高電平訊號，第— _級移位暫存單元2〇〇僅在T3時間内輸出高電平訊號，由 b可見各級移位暫存單j 2〇〇輸出的高電平訊號互相之 間均沒有重疊，而該高電平訊號為有效訊號，即本發明移 位暫存器20輸出的各級有效訊號互相之間沒有重疊。 一本發明移位暫存器20的每一移位暫存單元2〇〇都需要 I時鐘訊號、前-級的輸出訊號及後—級的反相輸出訊號 爲控制訊號’並藉由該第一上拉電路31、第二上拉電路 I2、第一下拉電路33及第二下拉電路34控制該第一公共 丨· P1而該第—公共節點P2受該第一公共節點ρι的控 1 ’即該輸出電路36相當於僅受該第一公共節點ρι的控 18 1335564 -制。當該輸出電路36的輪出訊號為時鐘訊號CK時，該時 鐘訊號CK是通過由該第八電晶體M8、第九電晶體奶構 成的二導電通路分別輸出的，因此該移位暫存器2G可容忍 較大的時鐘訊號上升時間或下降時間，可接"部高電平 訊號VDD的最大值及外部低電平訊號vss的最小值的範 圍較先前技術也更寬。同時，該輸出端ν〇υτ的電壓準位 也更爲精確。 f 一移㈣存單元200的第-反相器35及第二反相器 • 37也可分別用一反相電路代替。 該移位暫存器20可用於液晶顯示裝置以及其他數位 電子產品中。請參閱圖6，其係一採用上述移位暫存器之 •液晶顯示裝置之結構示意圖。該液晶顯示裝置2包括一液 .晶顯示面板21、一資料驅動電路22及一掃描驅動電路23, 該貝料驅動電路22及該掃描驅動電路23分別#由複數數 據線與複數掃描線與該液晶顯示面板21連接。該液晶顯示 面板包括一上基板（圖未示）' 一下基板（圖未示）及一夹 持於上基板與下基板間之液晶層（圖未示），且於該下基板 鄰近液晶層一側設置有一用於控制液晶分子扭轉狀態之薄 膜電晶體陣列（圖未示）。該資料驅動電路22及該掃描驅動 電路23分別包括一上述移位暫存器2(^該掃描驅動電路 23在該移位暫存器2〇的控制下依序輸出高電平訊號至該 複數掃描線，以逐列控制該薄膜電晶體矩陣之導通與關斷 狀態。該資料驅動電路22依序輸出資料訊號至該液晶顯示 面板21，以控制其顯示畫面變化。該掃描驅動電路23及 該資料驅動電路22皆利用該移位暫存器2〇控制掃描訊號 19 1335564 與資料訊號之輸出時序，從而實現晝面顯示。 與先前技術相比，本發明移位暫存器2〇輸出的各級有 效訊號互相之間沒有重疊，因此該掃描驅動電路23或資料 驅動電路22在進行行掃描或列掃描時，其輸出掃描訊號或 資料訊號不會產生訊號干擾’從而提高了該液晶顯示裝置 2的顯示效果。 綜上所述，本創作確已符合發明專利之要件，爰依法 提出申請專利。惟’以上所述者鶴本發明之較佳實施方 式，本發明之範圍並不以上述實施方式爲限，舉凡熟習本 2藝之人士援依本發明之精神所作之等效修飾或變化， 白應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 種^前技術移位暫存單元之電路示意圖。 圖3係本發明移位暫存器較佳實m時序不思圖 圖4係圖3之蒋彷蘄;fe - 飞之結構不意圖。 m 早70之電路示意圖。 =5係圖3中移位暫存器之時序示意圖。 圖6係本發明液晶顯示裝 貫轭方式之結構示意圖。 【主要元件符號說明】 20 1335564 液晶顯示裝置 2 移位暫存器 20 液晶顯不面板 21 資料驅動電路 22 掃描驅動電路 23 第一上拉電路 31 第二上拉電路 32 第一反相器 35 第一下拉電路 33 輸出電路 36 第二下拉電路 34 第二反相器 37 移位暫存單元 200 緩衝器 361 211335564 * -,,, 9. Description of the Invention: [Technical Field] The present invention relates to a shift register and a liquid crystal display device using the shift register. [Prior Art] At present, Thin Film Transistor (TFT) liquid crystal display devices have gradually become standard output devices for various digital products. However, it is necessary to design an appropriate driving circuit to ensure stable operation. Generally, a driving circuit of a liquid crystal display device includes a data driving circuit and a scanning driving circuit. The data driving circuit is used to control the display luminance of each pixel unit, and the scan driving circuit is used to control the on and off of the thin film transistor. Both drive circuits use a shift register as the core circuit unit. Generally, the shift register is formed by connecting a plurality of shift register units in series, and the output signal of the previous shift register unit is the input signal of the latter shift register unit. Please refer to FIG. 1, which is a circuit diagram of a shift register unit of a prior art shift register. The shift register unit 100 includes a first clock inversion circuit 110, a converter circuit 120, and a second clock inverting circuit 130. Each circuit of the shift register unit 100 is composed of a PMOS (P-channel Metal-Oxide Semiconductor) type transistor, and each PMOS transistor includes a gate and a source. And a bungee. The first clock inverting circuit 110 includes a first transistor M1, a 1335564, a second transistor M2, a third transistor M3, a fourth transistor M4, a first output terminal V01, and A second output terminal V02. The gate of the first transistor M1 receives the output signal VS of the shift register unit before the shift register unit 100, and the source receives the high level signal VDD from the external circuit, and the drain thereof is connected to the first The source of the second transistor M2. The gate of the second transistor M2 and its drain receive a low level signal VSS from an external circuit. The gates of the third transistor M3 and the fourth transistor M4 receive the drains of the inverted clock signals from the external circuit as the first output terminals V01 and the first of the first clocked inverter circuits 110, respectively. The second output terminal V02 has a source connected to the drain of the first transistor M1, and a source of the fourth transistor M4 is connected to the gate of the first transistor M1. The converter circuit 120 includes a fifth transistor M5, a sixth transistor M6 and a signal output terminal VO. The gate of the fifth transistor M5 is connected to the first output terminal V01, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the sixth transistor M6. The gate of the Lulu transistor M6 is connected to the second output terminal V02, and the drain terminal receives the low level signal VSS from the external circuit, and the source thereof is the signal output terminal VO of the shift register unit 100. The second clock inverting circuit 130 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The gate of the seventh transistor M7 is connected to the signal output terminal VO, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the eighth transistor M8. The gate of the eighth transistor M8 and its drain receive a low level signal VSS from an external circuit. The source of the ninth transistor 1335556, . , * . M9 is connected to the first output terminal VO1, the gate thereof receives the clock signal CK from the external circuit, and the drain thereof is connected to the drain of the seventh transistor M7. . The gate of the tenth transistor receives the clock signal CK of the external circuit, the source of which is connected to the second output terminal V02, and the drain of which is connected to the signal output terminal V0. Please refer to FIG. 2 together, which is a working sequence diagram of the shift register unit 100. During the time T1, the output signal VS of the previous shift register unit is changed from a high level to a low level, and the inverted clock signal CK is changed from a low level to a high level, thereby making the third The transistor M3 and the fourth transistor M4 are turned off, and the first clocked inverter circuit 110 is turned off. The clock signal CK is changed from a high level to a low level, so that the ninth transistor M9 and the tenth transistor M10 are turned on, thereby turning on the second clock inverting circuit 130, and the signal output terminal is turned on. The sixth level of the VO initial state is turned off by the tenth transistor M10, and the low level of the eighth transistor M8 is outputted via the ninth transistor M9 to make the fifth transistor M5 is turned on, and then the source high level signal VDD is output to the signal output terminal VO', so the signal output terminal VO maintains the rfj level output. When the inverted clock signal CK is changed from the south level to the low level during the T2 time, the third transistor M3 and the fourth transistor M4 are turned on, thereby turning on the first clock inverting circuit 110. . When the clock signal CK is changed from a low level to a high level, the ninth transistor M9 and the tenth transistor M10 are turned off, and the second clocked inverter circuit 130 is turned off. The input signal VS is changed from a still level to a low level, and then the first transistor M1 is turned on, and a high level VDD of the source thereof is turned off by the third transistor M3 via the third transistor M3, and The low level of the input signal VS is turned on by the fourth 1355564 • the transistor M4 turns on the sixth transistor M6, so that the signal output terminal VO outputs a low level. During the period of T3, the inverted clock signal CK is changed from a low level to a high level, and the third transistor M3 and the fourth transistor M4 are turned off, thereby causing the first clock inverting circuit 11 to be turned off. disconnect. The clock signal CK is changed from a still level to a low level, so that the ninth transistor M9 and the tenth body M10 are turned on, and the second clocked inverter circuit 13 is turned on. The low level of the signal output terminal vo turns on the seventh transistor M7, and the source 冋 level thereof is turned off by the ninth transistor M9 to the fifth transistor M5. At the same time, the low level of the signal vomit vo is also turned on by the tenth transistor M1 〇 to the sixth transistor M6, and the second low level of the sixth transistor (10) keeps the signal output terminal VO low. Flat output. During the period of T4, the inverted clock signal is switched from a high level to a low level to turn on the second transistor M3 and the fourth transistor, and the first clock inverting circuit 11 is turned on. The clock signal Μ ^ low level jumps to a high level causes the ninth transistor (10) and the tenth electrode body 10 to be turned off and the second clocked inverter circuit is turned off. The high level of the input signal VS passes through the fourth transistor body M6, and the second transistor plate/dipole/, electric day M3 conducts (four) flute level is turned on by the third transistor M3, and the fifth (M) M5 ' Its source number output terminal VO causes the signal ## electric ten to turn out to the high level of the signal. The output of the output terminal V〇 is changed from a low level to a timing diagram. The shift register unit is a bit temporary storage unit at time T1 and T2 time -= shift register unit! (10) Yu Τ 2 I _ electric thousand sequel' and the -, Τ 3 time output low level signal 1335564 t • number, the two low level signals overlap at T2 time. The low signal is a valid signal, that is, the effective signals outputted by the shift register formed by the plurality of shift register units 1 互相 overlap each other. In addition, the shift register can be applied to liquid crystal display devices and other digital electronic products. For example, the data driving circuit of the liquid crystal display device captures the driving circuit, and the shift register is required to perform the column scanning or the line scanning. Then, the effective signals of the levels outputted by the shift register are overlapped with each other. When the lean driving circuit or the scanning driving circuit performs row-by-row, there are two adjacent columns or rows simultaneously scanning, thereby The loading signals generate mutual interference. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a device that outputs an effective signal without overlap. A liquid crystal display device which can avoid signal interference is also a necessary shift register, which includes a plurality of shift register units, each of which shifts the clock signal of the external circuit and the shift of the previous stage. The temporary storage unit has a first pull-up circuit, a second pull-up circuit, a first pull-down circuit, and a first pull-up signal. A pull-down circuit, a first-inverting circuit, a second inverting circuit, and an output circuit. The first and second pull-up circuits, the first pull-down circuit and the output circuit have a first common node, the first pull-up circuit, the second pull-down circuit, and the output circuit have a first common node, The first inverter circuit is connected between the first and second common 11 1335564 .f points. The first and second pull-up circuits provide a first level signal to the first common node, and the first and second pull-down circuits provide a low level subtraction for the first common node, and the output circuit is in the first and the The output of the clock signal or the low level signal is selected under the control of the common node, and the second inverter circuit inverts the output signal of the output circuit and outputs the output signal. The liquid crystal display device comprises: a... a sunday display panel, a tributary drive circuit and a scan drive circuit, wherein the data drive circuit provides a data signal for the liquid crystal display panel, and the scan drive circuit is the liquid crystal display The panel provides a scan signal. The data drive circuit and the scan drive circuit respectively include a shift register to control an output timing of the data signal and the scan signal, and the shift temporary memory H includes a plurality of shift register units, each shifting The clock signal of the bit buffer circuit, the output of the previous stage shift register unit, and the inverted output signal control of the bit buffer unit. Each shifter: 70 includes a first pull-up circuit, - second Pull-up circuit, - phase - phase Thunder ^ ^ a first inverting circuit, a second inverting one output circuit 'the first _, the second pull-up circuit, the first, the first: circuit m thunder r / have - a first common node, the first upper point. The two r-output circuits have a second common section: the second common node, and the second common node provides a high-level relay for the first-common node. The #^ pull circuit is the first-common The node provides a low-level dry-out ^=out circuit to select a round-out clock signal or a low-level signal under the control of the first and second common nodes, and the selected output signal is inverted and outputted. The inverting circuit compares the output circuit with the prior art. As can be seen from the working timing diagram, the shifting temporary storage of each stage 12 1335564 ·,.. The south level signals of the early output are not heavy with each other' The level signal is a valid signal, that is, the effective signals of the output of the shift register of the present invention do not overlap each other. Compared with the prior art, the effective signals of the output of the shift register of the present invention are not between each other. Since the scan driving circuit or the data driving circuit performs line scanning or column scanning, the output scanning signal or the data signal does not cause signal interference, thereby improving the display effect of the liquid crystal display device of the present invention. 3 is a schematic structural diagram of a preferred embodiment of a shift register of the present invention. The shift register 20 includes a plurality of shift temporary storage units 200 having the same structure, and the plurality of shift temporary storage units 200 are sequentially Each shift register unit 200 includes a clock signal input terminal CK, a first input terminal VIN1, a second input terminal VIN2, an output terminal VOUT, an inverting output terminal VOUTB, and a high-level input terminal. VH and a low level input terminal _ VL. The clock signal input terminal CK of each shift register unit 200 receives the clock signal CK of an external circuit (not shown), and the high level input terminal VH receives the external circuit (Fig. The low level signal VDD, not shown, receives a low level signal VSS of an external circuit (not shown), and its first input terminal VIN1 is electrically connected to the previous stage shift register unit 200. The output terminal VOUT, the second input terminal VIN2 is electrically connected to the inverting output terminal VOUTB of the subsequent stage shift register unit 200, and the output terminal VOUT is electrically connected to the first input terminal VIN1 of the subsequent stage shift register unit 200, Its inverting output terminal VOUTB is electrically connected to the previous stage shifting temporary The second input terminal 13 1335564 ·... VIN2 of the memory unit 200. That is, the output signal of the previous stage shift register unit 200 is the first input signal of the shift stage temporary storage unit 200, and the latter stage shift register unit The inverting output signal of 200 is the second input signal of the previous stage shift register unit 200, and each shift register unit is simultaneously controlled by the external circuit clock signal, high level signal and low level signal. 4 is a schematic circuit diagram of the shift register unit of FIG. 3. The shift register unit 200 includes a first pull-up circuit 31, a second pull-up circuit 32, a first pull-down circuit 33, and a The second pull-down circuit 34, a first inverter 35, an output circuit 36 and a second inverter 37. The first pull-up circuit 31, the second pull-up circuit 32, the first pull-down circuit 33, the second pull-down circuit 34, and the output circuit 36 have a first common node P1. The first pull-up circuit 31, the second pull-down circuit 33, and the output circuit 36 have a second common node P2. The first inverters 35 are connected between the first and second common nodes PI and P2, and the first and second pull-up circuits 31 and 32 provide a high level signal for the first common node P1. 1. The second pull-down circuit 33, 34 provides a low level signal for the first common node P1. The first pull-up circuit 31 is controlled by the first input terminal VIN1 and the second common node P2, and the second pull-up circuit 32 is controlled by the first and second input terminals VIN1' VIN2, the first pull-down The circuit 33 is controlled by the first input terminal VIN1, and the second pull-down circuit 34 is controlled by the second input terminal VIN2 and the second common node P2. The output circuit 36 selects an output clock signal CK or a low level signal VSS to the output terminal VOUT under the control of the first and second common nodes P1 and P2, and the second inverter 37 inverts the signal of the output terminal VOUT. Then input to the inverting output terminal VOUTB. The first pull-up circuit 31 includes a first transistor M1 and a second transistor 14 1335564 . . . , a crystal M2. The first and second transistors M1 and M2 are PMOS type transistors. The gate of the first transistor M1 is electrically connected to the first input terminal VIN1, the source thereof is electrically connected to the high-level input terminal VH, and the drain thereof is electrically connected to the source of the second transistor M2. The gate of the second transistor M2 is electrically connected to the second common node P2, and its drain is electrically connected to the first common node P1. The second pull-up circuit 32 includes a third transistor M3 and a fourth transistor M4. The third and fourth transistors M3 and M4 are PMOS type transistors. The gate of the third transistor M3 is electrically connected to the first input terminal VIN1, and the source thereof is electrically connected to the high-level input terminal VH, and the drain thereof is electrically connected to the source of the fourth transistor M4. The gate of the fourth transistor M4 is electrically connected to the second input terminal VIN2, and the drain is electrically connected to the first common node P1. • The first pull-down circuit 33 includes a fifth transistor M5, which is an NMOS type transistor. The gate of the fifth transistor M5 is electrically connected to the first input terminal VIN1, the source thereof is electrically connected to the first common node P1, and the drain thereof is electrically connected to the low level input terminal VL. The second pull-down circuit 34 includes a sixth transistor M6 and a seventh transistor M7. The sixth and seventh transistors M6 and M7 are NMOS type transistors. The gate of the sixth transistor M6 is electrically connected to the second common node P2, the source thereof is electrically connected to the first common node P1, and the drain thereof is electrically connected to the source of the seventh transistor M7, the seventh transistor The gate of M7 is electrically connected to the second input terminal VIN2, and its drain is electrically connected to the low level input terminal VL. The output circuit 36 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and a buffer 361. The eighth transistor M8 is a PMOS type transistor, and the ninth and tenth The transistors M9 and M10 are NMOS type transistors. The buffer 361 is mainly used to maintain the output waveform of the shift register 15 1335564.., the unit 200 to avoid distortion of the output waveform. The gate of the eighth transistor M8 is electrically connected to the first common node P1, and the source thereof is electrically connected to the clock signal input terminal CK, and the drain electrode is electrically connected to the source of the tenth transistor M10. The gate of the ninth transistor M9 is electrically connected to the second common node P2, the source of which is electrically connected to the clock signal input terminal CK, and the drain of which is electrically connected to the source of the tens of transistor M10. The gate of the tenth transistor M10 is electrically connected to the first common node P1, the drain of which is electrically connected to the low level input terminal VL, and the source thereof is electrically connected to the output terminal VOUT by the buffer 361. • Please refer to FIG. 5 together, which is a timing diagram of the shift register 20 in FIG. A stage shift register unit 200 is represented by η, and the previous stage and the subsequent stage are represented by η-1, η + 1, respectively. In the Τ1 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be at a high level, then the first transistor M1 is turned off, and the third transistor M3 is turned off. At the end, the fifth transistor Μ5 is turned on. When the first common node P1 is pulled down to a low level, the eighth transistor M8 is turned on and the tenth transistor M10 is turned off. The low voltage level of the first common node P1 passes through the first inverter 35 and becomes a high level, that is, the second common node P2 is at a high level, the second transistor M2 is turned off, and the sixth transistor M6 is turned on. The ninth transistor M9 is turned on. The second input terminal VIN2 receives the output signal V03 of the nth + 1st inverting output terminal is still level 'the fourth transistor Μ4 is turned off, the seventh transistor Μ7 is turned on, and the first common node Ρ1 stably maintains the low level signal. Then, the second common node 稳定2 stably maintains the south level signal. The clock signal CK is input to the buffer 361 through the eighth transistor Μ8 and the ninth transistor Μ9, respectively. At this time, the clock signal CK is at a low level, so the output signal V02 of the output terminal VOUT is at a low level. 16 1335564 • ·,.. In the T2 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 is low level, then the first transistor M1 is turned on, The third transistor M3 is turned on, and the fifth transistor Μ5 is turned off. Since the second common node P2 still maintains a high level signal, the second transistor M2 is turned off, the sixth transistor M6 is turned on, and the ninth transistor M9 is turned on. The second input terminal VIN2 receives the output signal of the n+1 stage inverting output terminal is high level, the fourth transistor M4 is turned off, the seventh transistor M7 is turned on, and the first common node Ρ1 continues to maintain the low level signal, then The eighth electric ring is turned on, the tenth transistor Μ10 is turned off, and the second common node Ρ2 is stably maintained at a high level signal. The clock signal CK is input to the buffer 361 through the eighth transistor Μ8 and the ninth transistor Μ9, respectively. At this time, the clock signal CK is at a high level, so the output signal V02 of the output terminal VOUT is at a high level. . In the Τ3 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be at a low level, the first transistor M1 is turned on, and the third transistor M3 is turned on. The fifth transistor Μ5 _ cutoff. The second input terminal VIN2 receives the output signal of the n+1 stage inverting output terminal to be low level, the fourth transistor M4 is turned on, the seventh transistor Μ7 is turned off, and the first common node Ρ1 is pulled up to a high level signal. Then, the eighth transistor Μ8 is turned off, and the tenth transistor Μ10 is turned on. The high level of the first common node Ρ1 passes through the first inverter 35 and becomes a low level, that is, the second common node Ρ2 is at a low level, the second transistor M2 is turned on, and the sixth transistor Μ6 is turned off. The ninth transistor Μ9 is turned off. The low level signal is input to the buffer 361 through the tenth transistor Μ10, so the output signal V02 of the output terminal VOUT is at a low level. 17 1335564 • · · · 'In the 4th time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the njth stage output signal v〇1 is low level, then the first transistor M1 is turned on. The third transistor M3 is turned on, and the fifth transistor is turned off. 'Because the second common node P2 still maintains the low level signal, the second transistor M2 is turned on. The sixth transistor M6 is turned off, and the ninth transistor M9 is turned off. When the A/, gf point P1 is pulled up to a high level signal, the eighth transistor (4) is turned off, and the tenth transistor M10 is turned on. The second input terminal VIN2 receives the output signal of the η + ι stage inverted output terminal to be high level, then the fourth transistor (10) is turned off, the seventh transistor M7 is turned on, and the first common node ρι is stably maintained at a high level signal. Then, the second common node p2 stably maintains a low level signal. The low level signal is input to the buffer 3(1) through the tenth transistor. Therefore, the output signal v〇2 of the output terminal νουτ is low. Compared with the prior art, it can be seen from the working timing diagram that the nith-level shift temporary memory only outputs a high-level signal in the T1 time, and the n-th shift temporary storage unit 200 outputs the high level only in the T2 time. The signal, the - _ stage shift register unit 2 输出 only outputs the high level signal in the T3 time, and the high level signals outputted by the b shifting temporary storage unit j 2 各级 are not overlapped with each other. The high level signal is a valid signal, that is, the effective signals of the levels output by the shift register 20 of the present invention do not overlap each other. Each shift register unit 2 of the shift register 20 of the present invention requires an I clock signal, a pre-stage output signal, and a post-stage inverted output signal as a control signal' A pull-up circuit 31, a second pull-up circuit I2, a first pull-down circuit 33 and a second pull-down circuit 34 control the first common 丨·P1 and the first common node P2 is controlled by the first common node ρι That is, the output circuit 36 is equivalent to being controlled only by the first common node ρι 18 1335564. When the output signal of the output circuit 36 is the clock signal CK, the clock signal CK is respectively output through the two conductive paths formed by the eighth transistor M8 and the ninth transistor milk, so the shift register 2G can tolerate a large clock signal rise time or fall time, and the range of the maximum value of the high level signal VDD and the minimum value of the external low level signal vss can be wider than the prior art. At the same time, the voltage level of the output terminal ν 〇υ τ is also more accurate. The first-inverter 35 and the second inverter 37 of the one-shift (four) memory cell 200 can also be replaced by an inverter circuit, respectively. The shift register 20 can be used in liquid crystal display devices as well as other digital electronic products. Please refer to FIG. 6, which is a schematic structural diagram of a liquid crystal display device using the above shift register. The liquid crystal display device 2 includes a liquid crystal display panel 21, a data driving circuit 22, and a scan driving circuit 23. The bead material driving circuit 22 and the scan driving circuit 23 are respectively composed of a plurality of data lines and a plurality of scanning lines. The liquid crystal display panel 21 is connected. The liquid crystal display panel includes an upper substrate (not shown), a lower substrate (not shown), and a liquid crystal layer (not shown) sandwiched between the upper substrate and the lower substrate, and the liquid crystal layer is adjacent to the lower substrate. A thin film transistor array (not shown) for controlling the twist state of the liquid crystal molecules is disposed on the side. The data driving circuit 22 and the scan driving circuit 23 respectively include a shift register 2 (the scan driving circuit 23 sequentially outputs a high level signal to the complex number under the control of the shift register 2 The scan line controls the on and off states of the thin film transistor matrix column by column. The data driving circuit 22 sequentially outputs the data signals to the liquid crystal display panel 21 to control the display screen change thereof. The scan driving circuit 23 and the The data driving circuit 22 uses the shift register 2 to control the output timing of the scanning signal 19 1335564 and the data signal, thereby realizing the face display. Compared with the prior art, the shift register 2 of the present invention outputs each The level effective signals do not overlap each other. Therefore, when the scan driving circuit 23 or the data driving circuit 22 performs line scanning or column scanning, the output scanning signal or the data signal does not generate signal interference, thereby improving the liquid crystal display device 2 In summary, the creation has indeed met the requirements of the invention patent, and the patent application is filed according to law. The scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit diagram of a prior art shift register unit. FIG. 3 is a preferred embodiment of the shift register of the present invention. FIG. 4 is a schematic diagram of FIG. The schematic diagram of the circuit diagram of the early 70. =5 is a timing diagram of the shift register in Fig. 3. Fig. 6 is a schematic view showing the structure of the liquid crystal display conjugate yoke according to the present invention. [Description of main components] 20 1335564 Liquid crystal display device 2 shift register 20 liquid crystal display panel 21 data drive circuit 22 scan drive circuit 23 first pull-up circuit 31 second pull-up circuit 32 first inverter 35 first pull-down circuit 33 output circuit 36 second pull-down Circuit 34 second inverter 37 shift register unit 200 buffer 361 21