TWI334648B - Circuit substrate with embedded photo sensor and method of fabricating the same - Google Patents

Circuit substrate with embedded photo sensor and method of fabricating the same Download PDF

Info

Publication number
TWI334648B
TWI334648B TW96104220A TW96104220A TWI334648B TW I334648 B TWI334648 B TW I334648B TW 96104220 A TW96104220 A TW 96104220A TW 96104220 A TW96104220 A TW 96104220A TW I334648 B TWI334648 B TW I334648B
Authority
TW
Taiwan
Prior art keywords
layer
circuit
core
photosensitive
patterned
Prior art date
Application number
TW96104220A
Other languages
Chinese (zh)
Other versions
TW200834936A (en
Inventor
Chien Hao Wang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW96104220A priority Critical patent/TWI334648B/en
Publication of TW200834936A publication Critical patent/TW200834936A/en
Application granted granted Critical
Publication of TWI334648B publication Critical patent/TWI334648B/en

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

1334648 九、發明說明: 【發明所屬之技術領域】 本發明是有關於-種感光元件之封裝結構,且特別是 有關於一種具有内埋式感光元件之線路基板及其製作方 法。 【先前技術】 以電子構裝技術而言,由於半導體封裝技術已趨於成 熟’愈來愈多感光型晶片(或晶圓)在製作完成之後,送 到晶片封裝廠進行組裝的作業,包括晶圓切割'黏晶、固 化、打線、封膠、植球以及上板,最後再進行成品測試或 功能性測試,以確認產品的製造良率。由於封裝完成後之 感光晶片可與其他控制電路、類比/數位電路(A/D Converter)、和數位訊號處理電路整合在一起,因此在現今 需求量大幅攀升之影像處理市場上,其成本明顯地降低許 多,且體積輕、薄、短、小,不佔空間,符合攜帶方便之 隨身電子裝置之要求。 一般而言’感光元件(或影像感測元件)分為兩大類: 其一為電荷耦合元件(CCD),另一為互補是金屬氧化半 導體(CMOS)元件。無論是CCD影像感測元件或CMOS 衫像感測元件,兩者均具有一光二極體陣列(photodiode array)位於其感光區(illumination area)中,而光二極體 陣列可接收外部影像訊號(或光線強弱訊號),並將影像訊 號轉換為電氣訊號傳遞至一線路基板(substrate)上,以 進行後續之影像處理。 請參考圖1,甘仏_ 示意圖。此知—種感光型W封裝結構的 -感光元件120、^構刚主要包括—線路基板110、 140。其中,减弁 透明封裝膠體130以及一玻璃基板 CMOS影像感^^牛1 甘2〇例如為⑽景繪感測元件或 並與線路基板U。二4 :配置於線路基板U。之表面上, 件120之上方 电性連接°玻璃基板140配置於感光元 受到雜質、微避免感光7^ 12G之感光區122 污染 所組成 填充有透明封裝4 =在感統件12G與玻璃基板140 壬边。一般而言,' 以保護感光元件120免於受到 透月封裝膠體130是由環氧樹脂(epoxy) 裝膠需先穿過玻璃基板140以及透明封 極體陣列(未繪^將=12G之感光區122 ’且由光二 線路基板11。傳遞至丨匕雜換為社訊號,並經由 到此光二極體_ 像處理晶片(未繪示),以得 产。 母—晝素所代表的光通量與色彩飽和 掉約線由:光線穿過玻璃基板140時會損耗 @ 此,會使得感光元件12〇之感光 :此外s由^片条低,進而影響所擷取到之影像的正確 光元件之上方配置有透明封裝膠體⑽ 及玻璃基板140,因么 m ^ 匕’會使得整個封裝結構具有較厚之 V1子度。 【發明内容】 1334648 本發明之目的是提供—錄 一 .=的=,,方法二==;: . 基板令,並使其感光區由線路基板的表面減出來,路 決習知之感光型晶片封裝結構因採臭 二解 光線損耗的問題。 嘴基板所a遇到之 本發明之另-目的是提供—種 之線路基板,此封裝方式是將心_ : 式改先凡件 _,以提供較佳之透光率,且㈣基被 參 mm甘 其整體具有較薄之厚度。 感光元件之二二:方 ⑽ease fihn)。之後,於離形膜上配置_感光 2犋 元件具有一感光區域以及多數個祖執 感光 接塾是面向離形膜。接著光區域及這些 以及:介電層,其中此核:具=配層 《光7L件。再來,Μ合此轉移基板、核心層以 迷 籲之後,移除離形膜以及轉移基板, :層。 綱及這些接塾’其中喪入有感光;==感 電,成-叠合層。再來,於感光元件之感光區^ ^ -保護層。錢,於疊合層之上下兩側分卿成二= J化線路層:及與其電性連接之一第二圖案化線路芦,J 中此弟一圖案化線路層與上述接墊電性連接。 θ其 在本發明之一實施例中,此製作方法在形成第 化線路層及第二圖案化線路層後,更包括移除=、護層圖案 、在本發明之一實施例中,上述壓合轉移基板、核心層 以及介電層之方式包括一熱壓製程。 ,本發明之—實施例中’移除離形膜以及轉移基板的 胳匕括騎~力°熱製程或是—紫外光騎製程,使離形 、以及轉移基板與疊合層分離。 以及實細巾,其巾形絲n線路層 p nS)、+加成法或是全加成法。 中升實施射’轉作方法更包括於疊合層 〔夕數彳叫!:通孔,使第—圖案化線路 案化線路層透過這些導電通孔而彼此電性連接。弟—圖 介電ΐί彳實施射,於_駐配置核心層以及 二及多數個介電層,其中各介電層是位於兩二= 線路層之間。之後,壓合此轉移基板、核心層、介=化 上述圖案化線路層以及介電層。 电層、 在本發明之-實施例中,於形成第一圖案化線 及第二圖案化線路層之後更包括:於第一圖宰化線=以 及第二圖案化線路層上分別形成-第-焊罩層以及^以 焊其中,第1罩層暴露出至少部分之第-Ξϊ 化線路層,而弟二焊罩層暴露出至少部分之第 圖案 路Γ ί後:ί第一嬋罩層所暴露之至少部分的第 ,路層上第-抗氧化層,並且在第二焊罩層= 路之至少部/刀的弟-圖案化線路層上形成一第二抗氧化 8 層。 在本發明之一實施例中,其中形 卜 :抗氧2層的方法包括:分別在第—焊罩層戶 ::與工 ◎P分的第-圖案化線路層以及第二焊罩:2珞至> 分的第二圖案化線路層上電链-鎳/金層1 '、路之至少部 2達^或是其他目的’本發㈣提出—種 ^感先几件之線路基板,包括―核心層、 ,件、-第-圖案化線路層、—第二圖幸u 層具有一開孔。介電層是位於核心 残光元光711件具有—感絲域以及多數個接墊,此 感先兀件疋位於核心層之開孔中,且介電戶之 核心層之間’其中感光區域“些接ΐ由核 曰中暴路出來。第-圖案化線路層配置於核心層上 @ν電通孔貝牙上述核心層與介電層,1中此第 =化線路過這些導電通孔與第二醜化線路層^ 齡f本發明之—實施例中’此具有㈣式感光it件之線 土板更包括一透明保護層,設置於感光區域上。 在本糾之—實補巾,此具有喊絲光元件之線 土板更包括多層圖案化線路層及多層介電層。這些圖案 =線路層是位於介電層以及第二圖案化線路層之間。而各 W電層是位於兩相鄰之圖案化線路層之間。 在本發明之一實施例中,此具有内埋式感光元件之線BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure of a photosensitive element, and more particularly to a circuit substrate having a buried photosensitive element and a method of fabricating the same. [Prior Art] In terms of electronic packaging technology, as semiconductor packaging technology has matured, more and more photosensitive wafers (or wafers) are sent to the wafer packaging factory for assembly operations, including crystals. Round cutting 'sticking, curing, wire bonding, sealing, balling and upper board, and finally finished product testing or functional testing to confirm the manufacturing yield of the product. Since the packaged photo-sensing wafer can be integrated with other control circuits, analog/digital converters, and digital signal processing circuits, the cost is significantly higher in today's demanding image processing market. It is much lighter, lighter, thinner, shorter, smaller, and does not occupy space. It meets the requirements of portable electronic devices that are convenient to carry. In general, photosensitive elements (or image sensing elements) fall into two broad categories: one is a charge coupled device (CCD) and the other is a metal oxide semiconductor (CMOS) device. Whether it is a CCD image sensing element or a CMOS image sensing element, both have a photodiode array in its illumination area, and the photodiode array can receive external image signals (or The light signal is converted to an electrical signal and transmitted to a circuit substrate for subsequent image processing. Please refer to Figure 1, Ganzi _ schematic. It is known that the photosensitive member 120 of the photosensitive type W package structure mainly includes the circuit substrates 110 and 140. The reduced transparent encapsulant 130 and a glass substrate CMOS image sensor are, for example, (10) landscape sensing elements or combined with the circuit substrate U. 2: 4: disposed on the circuit substrate U. On the surface, the upper portion of the member 120 is electrically connected. The glass substrate 140 is disposed on the photosensitive element to be contaminated by the impurity, and the photosensitive region 122 of the photosensitive layer 7^12G is contaminated. The transparent package 4 is filled in the sense element 12G and the glass substrate 140.壬 。. In general, 'protecting the photosensitive element 120 from the moon-permeable encapsulant 130 is epoxy-filled through the glass substrate 140 and the transparent capping array (not shown) The area 122' is transmitted from the optical circuit board 11 to the noisy and replaced by the social signal, and is processed by the photodiode image processing chip (not shown). The luminous flux represented by the mother-alkaline is The saturation of the color is caused by the loss of light when the light passes through the glass substrate 140. This will cause the photosensitive element 12 to be sensitive to light: in addition, the s is low by the strip, thereby affecting the correct optical element of the captured image. The transparent encapsulant (10) and the glass substrate 140 are disposed, so that m ^ 匕 'will make the whole package structure have a thicker V1 degree. [Abstract] 1334648 The object of the present invention is to provide a record of ===, Method 2 ==;: . The substrate is ordered, and the photosensitive area is reduced by the surface of the circuit substrate, and the photosensitive chip package structure of the conventional method is used to solve the problem of light loss due to the odor. Another object of the invention is to provide The circuit substrate is packaged in such a way that the core _: is changed to provide a better light transmittance, and the (four) base is measurable with a thin thickness. The photosensitive element is two or two: square (10) ease fihn ). Thereafter, the photoreceptor is disposed on the release film. The photosensitive member has a photosensitive area and a plurality of photosensitive contacts are facing the release film. Then the light region and these: and the dielectric layer, wherein the core: with the = layer "light 7L pieces. Then, after the transfer substrate and the core layer are combined to be confusing, the release film and the transfer substrate are removed. And the junctions of which are sensitized; == electro-sensing, into-laminated layers. Then, in the photosensitive region of the photosensitive element ^ ^ - protective layer. Money, on the lower side of the superimposed layer, is divided into two = J circuit layer: and one of the electrical connection with the second patterned line reed, J, a younger patterned circuit layer and the above-mentioned pads are electrically connected . θ, in an embodiment of the present invention, after the forming the second layer and the second patterned layer, the method further comprises removing the layer pattern, and in one embodiment of the invention, the pressure is The manner of transferring the substrate, the core layer and the dielectric layer includes a hot pressing process. In the embodiment of the present invention, the release film and the transfer substrate are removed, or the ultraviolet process or the ultraviolet light riding process is used to separate the release film and the transfer substrate from the laminate layer. And a fine towel, a towel-shaped wire n circuit layer p nS), a + additive method or a full additive method. The medium-rise implementation of the shooting method is also included in the superimposed layer. : a via hole through which the first patterned circuit layer is electrically connected to each other through the conductive vias. The brother-figure 彳 彳 彳 彳 彳 彳 彳 彳 驻 驻 驻 驻 驻 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在Thereafter, the transfer substrate, the core layer, the patterned wiring layer, and the dielectric layer are laminated. The electrical layer, in the embodiment of the present invention, after forming the first patterned line and the second patterned circuit layer, further comprises: forming a first layer on the first pattern and a second patterning layer a solder mask layer and a solder layer, wherein the first cap layer exposes at least a portion of the first germanium circuit layer, and the second solder mask layer exposes at least a portion of the first pattern pass: At least a portion of the exposed first, anti-oxidation layer on the road layer, and a second anti-oxidation layer 8 is formed on the second solder mask layer = at least part of the path / the slab-patterned wiring layer. In an embodiment of the present invention, the method for shaping the anti-oxygen layer includes: a first-patterned circuit layer and a second solder mask in the first-welding layer:: and the working layer: 2珞 to the second patterned circuit layer on the power-on-nickel/gold layer 1 ', at least part 2 of the road up to ^ or other purposes 'this hair (four) proposed - the first sense of the circuit board, The layer includes a core layer, a member, a -first patterned circuit layer, and a second layer has an opening. The dielectric layer is located at 711 pieces of core afterglow light with a sensed filament domain and a plurality of pads. The sense element is located in the opening of the core layer, and the photosensitive layer between the core layers of the dielectric household "These connections are caused by the storm in the core. The first-patterned circuit layer is disposed on the core layer of the above-mentioned core layer and dielectric layer of the @ν电通孔贝牙, in which the first pass line passes through the conductive vias and The second ugly circuit layer is the invention. In the embodiment, the wire plate having the (four) type photosensitive member further comprises a transparent protective layer disposed on the photosensitive region. The wire earth plate with the shimmering element further comprises a plurality of patterned circuit layers and a plurality of dielectric layers. The pattern=circuit layer is located between the dielectric layer and the second patterned circuit layer, and each W electrical layer is located in two phases. Between adjacent patterned circuit layers. In an embodiment of the invention, the line having the buried photosensitive element

接’如此’即完成具有内埋式感光元件之線路基板 於感光元件是嵌入於線路基板中,且其感光區域會 位路基板中暴露出來,因此,感光S件之感光區域可直 收光線,使整個封裝結構具有較佳之透光率,且使整 ,線路基板具有較薄之厚度。再者,由於感光元件之接墊 疋直接與線路基板上之圖案化線路層電性連接,而不需利The circuit board with the embedded photosensitive element is embedded in the circuit substrate, and the photosensitive area is exposed in the circuit substrate, so that the photosensitive area of the photosensitive S component can directly receive light. The entire package structure has a better light transmittance, and the entire circuit substrate has a thin thickness. Moreover, since the pads of the photosensitive element are directly electrically connected to the patterned circuit layer on the circuit substrate, it is not necessary to benefit

用打線方式與線路基板電性連接,因此,可有效簡化製程, 以利於產品之量產。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說 明如下。 【實施方式】The wire is electrically connected to the circuit substrate, so that the process can be simplified to facilitate mass production of the product. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment]

圖2Α〜2Η繪示為根據本發明之一實施例的一種具有内 埋式感光元件之線路基板的製作方法之流程剖面圖。首 先’請參考圖2Α’提供一轉移基板21〇,並於轉移基板210 之表面210a上配置一離形膜220,且於離形膜220上配置 一感光元件230,此感光元件230具有一感光區域232以 及多數個接墊234 ’且其感光區域232及接墊234是面向 離形膜220。在本發明之一實施例中,轉移基板21〇可由 玻璃、金屬、玻璃環氧基樹脂(FR-4、FR-5)或雙順丁烯二 酸酿亞胺-三氮雜笨(Bismaleimide-Triazine, BT)所組成。此 外’離形膜220之功用主要是讓感光元件可暫時固定於轉 移基板210上’因此,可採用熱釋放膠膜(thermal release 11 1334648 film)、紫外光釋放膠膜(uv reiease仙句或其他類似之 料,以利於後製程之剝離。 之後,請參考圖2B,於離形膜22〇上依序配置一核心 層242以及一介電層244,核心層242中具有一開孔η, μ谷直^喊就件23Gm _ w—服的塑膠 基板或是已具有線路之基板。此外,介電層2料之材料可 為含有玻璃顆粒的環氧樹脂(Ajinomoto Build_up Film,2A to 2D are cross-sectional views showing a flow of a method of fabricating a wiring substrate having a buried photosensitive member according to an embodiment of the present invention. First, please refer to FIG. 2A to provide a transfer substrate 21A, and a release film 220 disposed on the surface 210a of the transfer substrate 210, and a photosensitive element 230 disposed on the release film 220, the photosensitive element 230 having a photosensitive The region 232 and the plurality of pads 234' and the photosensitive regions 232 and pads 234 thereof face the release film 220. In one embodiment of the present invention, the transfer substrate 21 may be made of glass, metal, glass epoxy (FR-4, FR-5) or bis-maleic acid-Bismaleimide- Triazine, BT). In addition, the function of the release film 220 is mainly to allow the photosensitive member to be temporarily fixed on the transfer substrate 210. Therefore, a thermal release film (thermal release 11 1334648 film), an ultraviolet light release film (UV reiease fairy sentence or the like) can be used. A similar material is used to facilitate the stripping of the post-process. Then, referring to FIG. 2B, a core layer 242 and a dielectric layer 244 are sequentially disposed on the release film 22, and the core layer 242 has an opening η, μ. Gu Zhizhi shouted the 23Gm _ w-suit plastic substrate or the substrate with the circuit. In addition, the material of the dielectric layer 2 material can be epoxy resin containing glass particles (Ajinomoto Build_up Film,

、雙順丁稀二酸酿亞胺_三氮雜苯1氧樹脂(印 或聚酿亞胺(polyimide)等。 接下來’請參相π,利賴壓或是其财式壓合 =多基板210、核心層242以及介電層24, bis-succinic acid diamine-diamine _ triazabenzene 1 oxy resin (printed or polyimide (polyimide), etc. Next 'please phase π, Li Lai pressure or its financial compression = more Substrate 210, core layer 242, and dielectric layer 24

===核心層242與感光元…S 件23g之感光區域232及接墊说, 件230之核心層242以及介電層撕則形 成一豐合層240。右κ拃制加丄=== The core layer 242 and the photosensitive region 232 and the pads of the photoreceptor S component 23g say that the core layer 242 of the member 230 and the dielectric layer tear form a plump layer 240. Right κ system heating

形膜220時,需進行若使用熱釋放膠膜作為離 膠膜作為離形膜220時,則 二放 使轉移基板210以及離^丁1外先知射製程,以 接下來,請表考沈、22G與疊合層240分離。 攻上形成-保護層感光元件⑽之感光區域 材料所組成,亦可以是非透是由透明 在受續製程中免於受損。在科’以保縣光區域232 、在形成保護層250的同時,可於 1334648 疊合層240中形成至少一貫孔TH,以作為後續疊合層24〇 之上表面的電路及下表面的電路二者電性連接之管道。 之後,請參考圖2F,於疊合層240之上下兩側分別形 成一第一圖案化線路層262以及與其電性連接的第二圖案 化線路層264,其中第一圖案化線路層262會鱼 二 230之接塾234電性連接。在此步驟中,可利用圖案化^ 鐘、半加成法、全加成法、賤鑛、物理氣相沉積或化學= 二3方式形成第一圖案化線路層262與第二圖案化 即完成具有内埋式感光元她 264 第;'圖案化線路層262與第二圖案化線路層 成一ΤΗ中形成一導電層,使其形 圄料^ ,第—圖案化線路層如盘第二 :其ΐ 透過導電通孔266而彼此電性: 第安各合且口層4〇上形成第一圖案化線路層262及 弟一圖案化線路層264之方法 ^ ^ 孔™内形成—層化學 /如於®合層上及貫 24?表面之金屬;上形成;二、電再於叠合f 以該化學銅層為電鑛種子層,於疊=層’接著 形成第-圖案化線路層及第日^表面上電鏡 ™内形成導電通孔266,接著線路層以及於貫孔 一道熟刻製程以移除不需該光阻層,然後進行 形成第一圖案化線路層262歲子銅層部份,此外,在 後,可直接於保護層25〇上再开—圖案化線路層264之 形成一層新的保護層,或是 1334648 先將原本的保護層250移除,之後,再於感光區域232上 形成一層新的保護層,以達到保護感光區域232之目的。 而在完成上述具有内埋式感光元件之線路基板2〇〇之 製作流程後,更可利用下列方式於線路基板2〇〇兩側的表 面形成焊罩層及抗氧化層,以保護線路基板2〇〇中的圖案 化線路免於受損及受潮。 一請參考圖2G所示,於第一圖案化線路層262以及第When the film 220 is formed, if a heat release film is used as the release film as the release film 220, then the transfer substrate 210 and the external probe are sprayed, and then the test is performed. 22G is separated from the laminate layer 240. It is composed of the photosensitive region material of the photosensitive layer (10) which is formed by the protective layer. It may also be non-transparent or transparent to avoid damage during the continuous process. At least while the protective layer 250 is formed, the at least consistent hole TH may be formed in the laminated layer 240 as the circuit of the upper surface of the subsequent laminated layer 24 and the circuit of the lower surface. The conduit for the electrical connection between the two. Then, referring to FIG. 2F, a first patterned circuit layer 262 and a second patterned circuit layer 264 electrically connected thereto are formed on the upper and lower sides of the laminated layer 240, wherein the first patterned circuit layer 262 The second 230 is connected to the 234 electrical connection. In this step, the first patterned circuit layer 262 and the second patterning can be completed by patterning, semi-additive, full-addition, antimony ore, physical vapor deposition or chemical=2. Having the embedded photoreceptor 264 first; 'the patterned circuit layer 262 and the second patterned circuit layer form a conductive layer in a ,, such that the shape of the material ^, the first patterned circuit layer such as the second: its电 Electrically connected to each other through the conductive vias 266: a method of forming a first patterned circuit layer 262 and a patterned circuit layer 264 on the first and lower via layers 4 ^ ^ Formation in the hole TM - layer chemistry / On the layer of the layer and on the surface of the surface of the surface of the surface of the surface of the layer; the second layer is formed by the second layer of the metal layer; a conductive via 266 is formed in the surface of the surface electron microscope TM, and then the circuit layer and the through hole are etched together to remove the photoresist layer, and then the first patterned circuit layer 262 is formed. In addition, afterwards, it can be re-opened directly on the protective layer 25—the formation of the patterned circuit layer 264 The new protective layer, or 1,334,648 original first protective layer 250 is removed, then, a new protective layer is further formed on the photosensitive layer region 232, to achieve the purpose of protecting the photosensitive region 232. After the manufacturing process of the circuit substrate 2 having the embedded photosensitive element is completed, the solder mask layer and the anti-oxidation layer may be formed on the surfaces of the two sides of the circuit substrate 2 to protect the circuit substrate 2 by the following methods. The patterned lines in the raft are protected from damage and moisture. Please refer to FIG. 2G for the first patterned circuit layer 262 and the first

二圖案化線路層264上分別形成一第一焊罩層272以及— 第二焊罩層274。此第-焊罩層272暴露出感光元件23〇 之感光區域232及至少部分之第一圖案化線路層崎在圖 2G中1-焊罩層272僅暴露出感光元件23〇之感光區域 232) ’而第二焊罩層274暴露出至少部分之第二圖案化線 路層264。 之後,請參考圖2H,在第一焊罩層272所暴露之第 :圖案化線路層施上形成—抗氧化層(圖中未示),並於 弟二焊罩層274所暴露之第二圖案化線路層264上形成另 一抗氧化層280。在本發明之—實施例中,抗氧化層· =方式’可例如在第二烊罩層274所暴露之第二圖案 、路264上電鍍-錄/金層’以形成抗氧化層28〇。在形 ^元抗氧化層珊之後,可移除掉保護層250,如此,感 230之感光區域232即可直接接收光線,當缺二 =層層250若為透明材質,亦可保留不需移除。至此, 整個具有㈣式感統件之線路基板完整的製 1334648 在上述製作流程中,是以具有雙層線路層之線路基板 為例以作說明,然而,使用者亦可根據不同的使用需求, 而在圖2B中所示之步驟中,於介電層244上配置多層圖 案化線路層以及多個介電層,其中各介電層是位於兩相鄰 的圖案化線路層之間。之後,再壓合此轉移基板21〇、核 心層242、介電層244、所有的圖案化線路層以及介電層, 即可形成具有所需之線路層的線路基板。本發明對於轉移 基板210上所堆疊之圖案化線路層以及介電層的層數不作 任何限制。 综上所述’本發明之具有内埋式感光元件之線路基板 的製作方式,首先,是先將感光元件、核心層以及介電層 配置於一具有離形膜之轉移基板上,其中,感光元件配置 於核心層之開孔中。之後,將轉移基板、核心層以及介電 層壓合在一起。接下來,再移除離形膜及轉移基板,以形 成一嵌入有感光元件之疊合層。最後,於疊合層之上下表 面形成所需之圖案化電路層,且其中一圖案化電路層與感 光元件電性連接,如此,即完成具有内埋式感光元件之線 路基板的製作。 由於感光元件是嵌入於線路基板中’且其感光區域會 由線路基板中暴露出來,因此,整個線路基板具有較薄之 厚度此外’由於感光元件之感光區域可直接接收光線, 因此,整個封裝結構具有較佳之透光率,且可提高其工作 表現。再者’由於感光元件之接墊是直接與線路基板上之 圖案化線路層電性連接,而不需·打線方式與線路基板 15 %性連接,因此,可有效簡化製程,以利於產品之旦 雖然本發明已以較佳實施例揭露如上,然^並=產。 限定本發明,任何所屬技術領域中具有通常知^者(用以 發明之㈣和範_,當可作些許之更動與潤#不 b本發明之賴範圍#視_之申料概_界定者 【圖式簡單說明】A first solder mask layer 272 and a second solder mask layer 274 are formed on the second patterned circuit layer 264, respectively. The first solder mask layer 272 exposes the photosensitive region 232 of the photosensitive element 23 and at least a portion of the first patterned wiring layer. In FIG. 2G, the 1-welding layer 272 exposes only the photosensitive region 232 of the photosensitive element 23). And the second solder mask layer 274 exposes at least a portion of the second patterned wiring layer 264. Thereafter, referring to FIG. 2H, an anti-oxidation layer (not shown) is formed on the first: patterned circuit layer exposed by the first solder mask layer 272, and the second layer is exposed by the second solder mask layer 274. Another oxidation resistant layer 280 is formed on the patterned wiring layer 264. In an embodiment of the invention, the anti-oxidation layer &lt;RTI ID=0.0&gt;&gt;&gt;&lt;/RTI&gt;&gt; can be electroplated-recorded/gold layer&apos; on the second pattern, 264 exposed by the second buffer layer 274 to form an oxidation resistant layer 28A. After the anti-oxidation layer is formed, the protective layer 250 can be removed, so that the photosensitive region 232 of the sensing 230 can directly receive light, and if the second layer 250 is a transparent material, it can be retained without moving. except. So far, the entire circuit board having the (four) type of sensing system is completed 1334648. In the above manufacturing process, the circuit board having the double-layer circuit layer is taken as an example for illustration. However, the user can also according to different usage requirements. In the step shown in FIG. 2B, a plurality of patterned wiring layers and a plurality of dielectric layers are disposed on the dielectric layer 244, wherein each dielectric layer is between two adjacent patterned wiring layers. Thereafter, the transfer substrate 21, the core layer 242, the dielectric layer 244, all of the patterned wiring layers, and the dielectric layer are further laminated to form a wiring substrate having a desired wiring layer. The present invention does not impose any limitation on the number of layers of the patterned wiring layer and the dielectric layer stacked on the transfer substrate 210. In summary, the manufacturing method of the circuit substrate having the embedded photosensitive element of the present invention firstly comprises disposing the photosensitive element, the core layer and the dielectric layer on a transfer substrate having a release film, wherein the photosensitive layer is formed. The component is placed in the opening of the core layer. Thereafter, the transfer substrate, the core layer, and the dielectric laminate are laminated together. Next, the release film and the transfer substrate are removed to form a laminated layer in which the photosensitive member is embedded. Finally, a desired patterned circuit layer is formed on the lower surface of the laminated layer, and one of the patterned circuit layers is electrically connected to the photosensitive element, thus completing the fabrication of the wiring substrate having the embedded photosensitive element. Since the photosensitive element is embedded in the circuit substrate and the photosensitive area is exposed by the circuit substrate, the entire circuit substrate has a thin thickness. In addition, since the photosensitive area of the photosensitive element can directly receive light, the entire package structure It has better light transmittance and can improve its performance. Furthermore, since the pads of the photosensitive element are directly electrically connected to the patterned circuit layer on the circuit substrate, the wire bonding method is not connected to the circuit substrate, so that the process can be simplified to facilitate the product. Although the present invention has been disclosed above in the preferred embodiment, it is produced. The invention is defined in the art, and is generally known in the art (for the invention (4) and the model _, when a slight change can be made and the process of the invention is not limited to the scope of the invention. Simple description of the schema]

= '·,曰不為$知—種感光型晶片封裝結構的示意圖。 圖2八〜2H繪示為根據本發明之一實施 ^感光Tt件之線路基板的製作方法之流程剖面圖二 【主要元件符號說明】 100 晶片封裝結構 110 線路基板 120 感光元件 130 封裝膠體= '·, 曰 is not known as a schematic diagram of a photosensitive wafer package structure. 2 to 2H are schematic cross-sectional views showing a method of fabricating a circuit substrate for a photosensitive Tt device according to one embodiment of the present invention. [Description of main components] 100 chip package structure 110 circuit substrate 120 photosensitive member 130 package colloid

140 :玻璃基板 2〇〇 :具有内埋式感光元件之線路基板 21〇 :轉移基板 220 :離形膜 230 .感光元件 232 ·感光區域 234 =接墊 240 ·豐合層 242 :核心層 16 1334648 244 :介電層 250 :保護層 262 :第一圖案化線路層 264 :第二圖案化線路層 266 :導電通孔 272 :第一焊罩層 274 :第二焊罩層 280 :抗氧化層 Η :開孔 ΤΉ :貫孔140: glass substrate 2: circuit substrate 21 with embedded photosensitive element: transfer substrate 220: release film 230. photosensitive element 232 · photosensitive region 234 = pad 240 · rich layer 242: core layer 16 1334648 244: dielectric layer 250: protective layer 262: first patterned wiring layer 264: second patterned wiring layer 266: conductive via 272: first solder mask layer 274: second solder mask layer 280: anti-oxidation layer :Opening hole : Through hole

1717

Claims (1)

十、申請專利範圍: 元件之線路基板的製作方法, 種具有内埋式感光 匕括下列步驟: 離形,細賴_之,上配置― 一感光元件’其中該感光元件具有 面向該離數個触,且該感統域及該些接塾是 其中 該枝:二:膜上依序配置-核心層以及-介電層, 二層中具有-開孔,以容置該感光元件; 壓合該轉移基板、該核心層以及該介電層; 該核 =該離形膜以及該轉移基板,以暴 之該感光d域及該些接 ^兀件 心層以及該介電層形成一叠合:;欣入有該感U件之 域上形成-保護層;以及 層以及缝電性日、車,下兩側分別形成-第-圖案化線路 m安^ 連接之―第二圖案化線路層,其中該第- 圖案化線路層與該些触電性連接。 &quot; 之線路乾圍第1項所述之具有内埋式感光元件 及今第:門安Γ方法,其中於形成該第一圖案化線路; n案化線路層後,更包括移除該保護層。路層 之線路A# j利减第1項所述之具有内埋式感光元件 以及該i電#法,其中壓合該轉移基板、該核心層 以及H層之方式包括—熱壓製程。 ^34648 4. 如申請專利範圍第丨項所 一 離形丄::基=:=卜光照射製程使該 5. 如申請專利範圍第工項所述 之線路基板的製作方法,其中形 有内埋式感先兀件 及該第二圖案化線路層圖案化線路層以 咖呦、半加成法或是全加成法。圖案化電鍍(鱗如 之線路第it述之具有内埋式感光元件 ,電通孔,使該第—圖案丄個 層透過該些導電通孔而彼此電性連接。/木化線路 之線光元件 以及該介電層之後,更包二==核心層 化線路層以及多數個介電層,其個圖案 鄰之圖宰化pq 、 。’丨电層是位於兩相 層、之後,壓合該轉移基板、該核心 电層、雜@案化線路層以及該些介電声。 8.如申請專利範圍第i項所述之且 二 3路基板的製作方法,於形成該第1案化 。&quot;第二圖案化線路層之後更包括: 、'、曰以及 於該第-圖案化線路層以及該 =成-第-焊罩層以及一第二烊罩二 曰/暴路出該感光區域,而該第二焊罩層暴露出至=部 1334648 分該第二圖案化線路層;以及 路:成第:氧罩化層層所暴露之至— 在該第二焊罩層所成献層的方法包括 電鏡-錄路之至少部分該第二圖案化線路層上 ι〇.種具有内埋式感光元件之線路基板,包括. 一核心層,具有一開孔; °括. 一介電層,位於該核心層之一側; =光元件’具有—感光區域以及多數個接塾 =件疋位於該核心層之該開孔中,且 = ==元件與該核心層之間,其中該感二 二接墊由该核心層中暴露出來; 唸 難電案化線關,配置於純心層上,並與該些 第—圖案化線路層,配置於該介電層上;以及 二數料電通孔,貫料如層触介, ΐ電::線路層透過該些導電通孔與該第二圖案= &amp;如申請專利範圍第10項所述之具有 括—酬紐料置料 件之^基^^:$1°顿毅具有他式感光元 20X. Patent application scope: The manufacturing method of the circuit substrate of the component, the method of having the embedded photosensitive method includes the following steps: the shape is fine, the thinning is _, the upper configuration is - a photosensitive element, wherein the photosensitive element has a facing number Touching, and the sensing domain and the junctions are among the branches: two: the film is sequentially arranged - the core layer and the - dielectric layer, and the second layer has - an opening to accommodate the photosensitive element; The transfer substrate, the core layer and the dielectric layer; the core = the release film and the transfer substrate, forming a superposition of the photosensitive d-domain and the core layer and the dielectric layer :; welcoming the formation of the protective layer on the U-shaped area; and the layer and the seam electrical day, the car, the lower side respectively form a - the first patterned circuit m an ^ connected to the second patterned circuit layer Wherein the first patterned circuit layer is electrically connected to the plurality of contacts. &quot; The line of the inner circumference of the first aspect of the invention has a built-in photosensitive element and the present invention: the method of forming a first patterning line; after the formation of the circuit layer, the removal of the protection Floor. The circuit layer A# j has the embedded photosensitive element and the i-electric method described in Item 1, wherein the method of pressing the transfer substrate, the core layer and the H layer includes a hot pressing process. ^34648 4. As described in the scope of the patent application, a detachment 丄:: base =: = 卜 照 照 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作 制作The buried sensing element and the second patterned circuit layer patterned circuit layer are curcumized, semi-additive or fully additive. Patterned electroplating (the scale of the circuit has a built-in photosensitive element, an electrical via, such that the first layer of the pattern is electrically connected to each other through the conductive vias. And after the dielectric layer, further comprising a == core layered circuit layer and a plurality of dielectric layers, the pattern of which is adjacent to the pattern, the pq, the 'electric layer is located in the two-phase layer, and then pressed Transferring the substrate, the core electrical layer, the hybrid circuit layer, and the dielectric sounds. 8. The method for fabricating the two-way substrate as described in claim i is formed in the first case. &quot;Second patterned circuit layer further comprises: , ', 曰 and the first-patterned circuit layer and the =-------------------------------------------- And the second solder mask layer is exposed to the portion 1334648 to the second patterned circuit layer; and the path: the first: the oxygen mask layer is exposed to - the layer of the second solder mask layer The method includes an electron microscope-recording at least part of the second patterned circuit layer The circuit substrate of the buried photosensitive element comprises: a core layer having an opening; a dielectric layer located on one side of the core layer; the optical element 'having a photosensitive area and a plurality of contacts ???疋 is located in the opening of the core layer, and === between the component and the core layer, wherein the sensing pad is exposed by the core layer; the hard-working electric line is closed, and is disposed in the pure heart And on the layer, and the plurality of patterned circuit layers are disposed on the dielectric layer; and the second plurality of electrical vias are traversed as a layer contact, and the: the circuit layer passes through the conductive vias and the The second pattern = &amp; as described in claim 10 of the patent application, the base material having the cover material is provided with the base material ^^: $1°
TW96104220A 2007-02-06 2007-02-06 Circuit substrate with embedded photo sensor and method of fabricating the same TWI334648B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW96104220A TWI334648B (en) 2007-02-06 2007-02-06 Circuit substrate with embedded photo sensor and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW96104220A TWI334648B (en) 2007-02-06 2007-02-06 Circuit substrate with embedded photo sensor and method of fabricating the same

Publications (2)

Publication Number Publication Date
TW200834936A TW200834936A (en) 2008-08-16
TWI334648B true TWI334648B (en) 2010-12-11

Family

ID=44212010

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96104220A TWI334648B (en) 2007-02-06 2007-02-06 Circuit substrate with embedded photo sensor and method of fabricating the same

Country Status (1)

Country Link
TW (1) TWI334648B (en)

Also Published As

Publication number Publication date
TW200834936A (en) 2008-08-16

Similar Documents

Publication Publication Date Title
TW201133727A (en) Chip package and fabrication method thereof
CN205944070U (en) Fingerprint sensor
TWI228948B (en) Camera module
TWI240338B (en) Structure of image sensor module and method for manufacturing of wafer level package
CN104078479B (en) The wafer-level packaging method of imageing sensor and image sensor package structure
CN106206485A (en) Imageing sensor module and preparation method thereof
TWI329931B (en) Semiconductor device and manufacturing method of the same, camera module
CN102856336B (en) Wafer encapsulation body and forming method thereof
TW200830870A (en) Package module and electronic assembly for image sensor device and fabrication method thereof
TW201103128A (en) Image sensor and the method for package of the same
CN105140253B (en) A kind of backside illuminated image chip die grade 3D stacked structures and packaging technology
TW200933845A (en) Semiconductor package and camera module
TW200952142A (en) Package substrate having embedded semiconductor chip and fabrication method thereof
CN106229325A (en) Sensor module and preparation method thereof
CN101419952A (en) Wafer stage chip encapsulation method and encapsulation construction
CN109274876A (en) Photosensory assembly and its packaging method, lens module, electronic equipment
TW200822313A (en) Sensor type semiconductor package and fabrication method thereof
TWI364096B (en)
TW200950505A (en) Image sensor structure and integrated lens module thereof
TWI384602B (en) Package substrate having embedded photosensitive semiconductor chip and fabrication method thereof
CN109326620A (en) A kind of embedded packaging structure and production method of image sensing chip
JP2010080591A (en) Camera module and method of manufacturing the same
CN101626026A (en) Encapsulation structure and method thereof of image sensing chip
TW200820398A (en) Structure of chip stacked packaging, structure of embedded chip packaging and fabricating method thereof
TWI232557B (en) Camera module and method of fabricating the same

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees