TWI334194B - Dielectric barrier layer films - Google Patents

Description

1334194 Ο) 发明, Invention Description Related Applications This application claims the priority of the application for the US inviting 60/506,128 indium nucleation layer on September 25, 2003. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to dielectric barrier films, and more particularly to dielectric barrier films for use in optical, electrical, tribological, and biological applications formed from layers of advanced materials. [Prior Art] The dielectric barrier layer is becoming increasingly important as a protective layer for organic light-emitting OLEDs and other optical or charging devices. In the past, wall layers have been deposited with suitable electrical, physical, and optical properties to enhance and enhance the operation of other devices. The dielectric barrier layer can be utilized in optical, electrical, or frictional applications. For example, touch screen displays require the protective layer to resist infection by atmospheric pollutants and resist physical wear. A number of thin film deposition techniques for forming such dielectric layers can be utilized for some form of ionic thermal compression or substrate bias thermal compression. Thermal Compression A columnar film structure other than a vacuum chemical vapor deposition (CVD) or physical vapor phase (PVD) film. It is well known that this thermal compression can be achieved by depositing a second ion source that is <impact" See W. Essingeri a ion beam assisted film deposition ion source 临时 Temporary body on the density of the photo-device device pole body (dielectric barrier to protect the device in the transparent protection program contains the program de-deposition (during plus, for example, correction -5 - (2) (2) 1334194 version of the scientific instrument (63) 11-5217 (1992). See also the Hrvoje Zorc Temple's 1998 41st Annual Technical Conference 411 Vacuum Coating Association Journal, pp. 243-247. It deals with the exposure of water vapor to the wavelength shift of the electron beam gasification membrane (e_beam), in particular, compared with the e-beam film of the deposition-guided ion beam source after exposure to 30% temperature at 25 °C. Zorc et al. show that the electron beam gasification film (e-beam) has a factor of about 15 in wavelength shift. DE Morton et al. exhibit a broadband bandpass filter consisting of a SiO2 and TiO2 interleaved layer, in order to provide w. As a low-index material or a dense gas film of titanium dioxide, bismuth pentoxide or bismuth pentoxide, the water vapor stabilized stack 〃, its use, cold cathode ion source "produces oxygen ions, PE Morton et al. in April 1998 18th - 23rd Annual Technical Begging Vacuum coatings, as measured by the optical performance of a single dielectric layer deposited on a substrate mounted on a rotating stencil, the results of Morton et al. indicate that room temperature is resistant to 100% temperature. Morton The light fading coefficient of the sample tested by et al. changed from 0.1 to 1.6 ppt, and there was no significant concentration in the dielectric layer in the defect or light absorption. In addition, Morton et al. applied the energy of the ion beam between 134 and 632 volts. At 5 amps of ion beam current, Morton et al. did not report film thickness or film thickness uniformity data. Therefore, Morton et al. could not describe a film that would operate with a good barrier layer of optical devices. Such as ion coating or tactile reaction deposition. Self-biased physical vapor deposition is a well-known method of providing a hard wear resist film. However, these films are deposited at a bias voltage of several hundred volts and form an ion current to penetrate the surface with the substrate -6 - (3 (3) 1334194 The material produces a osmotic surface treatment of the reaction, or in order to reduce the columnar structure of the film 'they are supplemented with ions. A filter cathode vacuum arc 已 has been used (FCVA - reference one h Ttp://www.nanofilm-systems.com/eng/fcva_technology.htm] forms a dense film from a stream of ions. In this case, ions are generated and separated by a magnetic vector, so that only positive charges The nuclide strikes the substrate. The bias can be pre-set so that the average transfer energy ranges from about 50 to hundreds of volts. The lower ion energy is not reported due to the problem of extracting and guiding the lower energy ion current with space charge density. Although it is very rough due to the re-sputtering method under high ion energy, it can be deposited with a hard protective layer of alumina and other materials such as four-sided volume with this cutting tool and a commercial rotary drilling machine. The coating rate is low due to the limitation of the coated species on the ion current. The best or hardest carbon film is often deposited at the lowest deposition rate, for example, the carbon film is 0.3 nm per second on a substrate having a diameter of 12 Å. By increasing the deposition temperature to above 230 °C, the transport of a ZnO film deposited by FCVA at a wavelength of 600 nm increases from about 50% to over 80% at room temperature for a single film, and the optimum transport is in deposition. Temperature 43 (TC and substrate bias is no greater than about 50 volts and wavelength is about 90% at 60 nm. This high temperature treatment indicates damage to the film repair ion sensing using a thermal tempering procedure. For FCVA deposition with a bias voltage of 200 volts In general, the transmission rate is greatly reduced. The FCVA film deposited in this manner has been expressed as a polycrystalline material. To form a photo barrier layer, the defect structure exhibited in the FCVA layer is too large. In addition, the crystalline film is Ion sputtering depends on the orientation of the spar, resulting in a high surface roughness. The defect structure formed in the protective layer can degrade the optical quality of the film. (4) (4) 1334194 Via film is also provided The diffusion path of atmospheric pollutants impairs the protective properties of the film. The ion-biased film has shown significant progress in protecting electrons and films such as photovoltage, semiconducting and electro-acoustic films from providing satisfactory barriers. Especially using calcium or doping is very counter- Other electrodes of metallic metals and other water-absorbing or reactive materials of organic light-emitting diodes can be protected by such films. However, the most frequently biased filtered vacuum vacuum arc coating technique or FCVA program has been reported to produce particle density. A film that is larger than about 1 defect per square centimeter. This can be a high voltage used in this procedure, and the high re-sputter rate makes the surface rough. Of course, the presence of particles represents a defect through which water vapor or oxygen can be carried out. The diffusion of the surface formed by the FCVA program affects the stress and pattern and also affects the transparency and uniformity of the refractive index. The re-sputtered film can be stripped from the process chamber into a sheet or by an ion beam program. The large electrostatic field present in the film is pulled to the surface of the film. In any case, the particle defect density of particles larger than the film thickness is determined by the fact that the line film cannot be coated on particles larger than the film thickness, so the pinhole density or film is also determined. Other defects caused by intermittent deposition, regardless of the particle size many times the thickness of the film. The ion bias or self-bias energy exceeds In the case of electron volts, the transfer energy of the ions added to the biasing program can exceed the chemical bonding energy of the film. Then, the impacted ions can disperse the atoms of the existing film forward or the atoms of the existing film backwards. Similarly, The ions can be adsorbed into the growing film, or it can be dispersed or absorbed from the surface of the film. Sputtering of existing films and dispersion from existing films prefers an angle of entry of about 45° from the horizontal in the large half-ion coating procedure. The ion beam is guided by a normal incidence of -8 (5) (5) 1334194 to the surface to be coated. However, as noted, the ion energy is exceeded beyond the chemical critical point, and especially beyond The energy of 20 volts is significant for the damage of the film or the substrate caused by the ion energy exceeding the chemical bonding energy, and causes surface roughness, increased light absorption characteristics, and defects. In the case of the FCV A program, the roughness is a film. The increasing thickness increases the roughness of a 50 nm film from about 0.2 nm to about 3 nm for a 400 nm copper film due to self-bias Differential sputtering of the copper ions, the copper film polycrystalline substance indicates the substance of a copper surface roughening. This film will disperse the light, especially at the interface between the two films of different refractive indices. To date, no barrier or dielectric properties of films produced by FCV A have been found. The charging of the deposited film is also a problem of the characteristics of the dielectric of the deposited ion beam. To date, low temperature dielectrics have not been known and there is no ion beam dielectric, which has been shown to provide the electrical qualities required for, for example, a transistor gate layer. The ion beam implants a charge ion in the film, causing a large negative flush band voltage and a field that cannot be passivated at temperatures below about 450 °C. The surface charge of the dielectric layer causes anti-slow accumulation' to prevent the urgency of starting conduction in a transistor application. As a result, low temperature dielectrics, biased or unbiased, have not been proposed or are known to be known for low temperature transistor applications. Therefore, high-quality, dense dielectric layers need to be utilized as barrier layers in optical, electrical, abrasive, and biometric applications. SUMMARY OF THE INVENTION (6) (6) 1334194 According to the present invention, one or more dielectric layers are formed from a layer of oxidized metal material deposited by a pulsed, biased, wide-area material vapor deposition process. A dielectric barrier layer in accordance with the present invention can be formed from at least one highly thermally compressive metal oxide layer. The dielectric barrier layer according to the present invention can be a highly thermally compressed 'highly uniform' ultra-low defect amorphous layer having an ultra-low defect concentration, providing superior performance as an anti-underlying structure and can be deposited to form an electrical, optical, Or a protective layer of physical wear and atmospheric pollution of the upper structure of the medical device. The barrier layer according to the present invention may also be a self-protecting optical layer 'electrical layer' or a friction layer that can be actively utilized in optical or electrical devices. Therefore, the barrier layer according to the present invention comprises a thermally compressed amorphous dielectric layer deposited on a substrate by a pulsed DC, a low-bias physical vapor deposition method, wherein the 'thermally-compressed amorphous dielectric layer is a barrier layer. Further, deposition can be performed on a wide area standard. The method of forming a barrier layer according to the present invention comprises providing a substrate and depositing a highly thermally compressed, amorphous material on the substrate by a pulsed DC, bias, wide standard physical vapor deposition process. , dielectric materials. Moreover, the procedure can include performing a soft metal vapor phase treatment on the substrate. The dielectric barrier stack according to the present invention can comprise any number of individual layers of film. The film comprises one or more barrier layers. In some embodiments, the individual barrier layers can be optical layers. The interleaved layer of low and high refractive index metal oxide materials can be arranged to form, for example, an antireflective or reflective coating film in an optical device. As such, the dielectric barrier according to the present invention provides a protective function and is a functional component of an optical device. For example, in certain embodiments of the present invention -10-(7)(7)1334194, dielectric barriers in accordance with the present invention may be utilized in cavity-enhanced LED applications or in the formation and protection of transistor structures. In addition, the advantageous dielectric properties of the barrier layer in accordance with certain embodiments of the present invention may be utilized as an electrical layer to form a resistive or capacitive dielectric. In certain embodiments, a soft metal may be utilized prior to deposition of a barrier layer (eg, , indium) breath treatment. This venting treatment represents a significant enhancement of the surface roughness of the barrier layer in accordance with embodiments of the present invention and enhances the WVTR characteristics. Referring to the following figures, these and other embodiments of the present invention are discussed and illustrated below. It is to be understood that the general description of the foregoing paragraphs and the following detailed description are for purposes of illustration and explanation only, and the invention is not limited thereto. Moreover, specific descriptions or theories relating to the deposition or performance of the barrier layer in accordance with the present invention or the treatment of soft metal breath are provided for illustrative purposes only and are not to be considered as limiting the scope of the published or claimed items. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description of a preferred embodiment of the barrier layer further illustrates the following pulsed DC, substrate bias, broad standard physical vapor deposition process for deposition in accordance with certain embodiments of the present invention. Barrier layer. Some of the barrier embodiments in accordance with embodiments of the present invention are characterized by high thermal compression, high uniformity, and a non-crystalline layer of particularly low defect concentration and high surface smoothness. Moreover, the barrier layer according to embodiments of the present invention may have advantageous optical and electrical characteristics that allow such barrier layers to be self-protecting in optical or electrical devices in which the layers are formed -11 - (8) (8) 1334194 Optical or Electrical Layers For example, certain barrier layer embodiments in accordance with the present invention may have superior optical transparency characteristics. Moreover, the refractive index of the individual barrier layers is dependent on the deposition material, and thus the multiple barrier layer stacks in accordance with the present invention can form a highly controllable, self-protecting, reflective or anti-reflective coating of the optical device. In addition, the barrier layer according to some embodiments of the present invention may be doped with photoactive impurities to form a photoactive layer that is also a self-protective layer. For example, deposition of bait or mirror rare earth ions can form an optical amplifier or frequency converter. Furthermore, the barrier layer embodiment according to the present invention can be highly advantageous dielectric and thus utilized as a self-protecting electrical layer. For example, certain barrier layers in accordance with embodiments of the present invention can be utilized as a resistive layer. Other embodiments can be utilized as the high dielectric constant layer of the capacitive device. Embodiments of dielectric barrier layers useful for such devices are discussed further below. The oxide film is discussed in the application No. 09/903,050 (the application filed on Dec. 10, 2011) by the name of the "Planar Optics and Method of Making It," by Demaray et al. The RF sputtering method, which is transferred to the same assignor as the present invention, is hereby incorporated by reference in its entirety. And the subject matter that can be utilized in the reactor according to the invention is discussed in the U.S. Application Serial No. 1/1,1,341, filed on March 16, 2002, which is assigned to the same assignee as the present invention. 'The whole case is incorporated into the reference. The method of depositing oxides by pulsed DC, substrate bias, broad-scale physical vapor deposition (PVD) procedures is discussed further in U.S. Application Serial No. PCT/101,863, filed on March 16, 2002. Pulsed, biased procedure ,), the case is transferred to the same assignor as the present invention, and the -12-(9) (9) 1334194 case is incorporated herein by reference in its entirety. 1A and 1B illustrate a reactor apparatus 10 in which a sputtering material is added from a target 1 2 in accordance with an embodiment of the present invention. In certain embodiments, device 10 may be, for example, from an AKT-1600 PVD (400 x 500 mm substrate size) system from Komatsu or from AKT-4300 (600x720) from Komatsu, Inc., Santa Clara, California. The mm substrate size is adapted to the system. For example, an AKT-1600 reactor has three or four deposition chambers connected by a vacuum transfer chamber. These AKT PVD reactors can be modified to supply pulsed DC power to the target and supply RF power to the substrate during deposition of a material. Apparatus 10 includes an object 12 that is electrically coupled to a pulsed DC power supply unit via filter 15. In some embodiments, the target 12 is parallel to the target 12 and is positioned opposite the target substrate 16 to provide a wide area sputtering source to be deposited on the substrate 16. When power is applied to the target 12, the target 12 acts as a cathode and is equivalently referred to as a cathode. Applying power to the target 12 produces a plasma 53 below the target 12. The magnet 20 is scanned across the top of the target 12. The substrate 16 is capacitively coupled to an electrode 17 through an insulator 54. The electrode 17 can be coupled to an RF power supply 18, such as that represented by device 10, for pulsed DC magneto-sputtering, the polarity of the supply supplied by the power supply 14 to the target 12 is oscillating between a negative and a positive potential. During the positive potential, the insulating layer on the surface of the target 12 is discharged and arcing is prevented. For the free deposition of the arc, pulsed DC power supply! The pulse frequency of 4 can exceed the critical frequency of at least part of the material that can be used according to the standard, cathode current -13- (10) (10) 1334194 flow and reverse time. A high-quality oxide film can be produced by using a reactive pulsed DC magnetron sputtering method in the device 1 . The pulsed DC power supply 14 may be any pulsed DC power supply, for example, Advanced Energy Inc.'s AE peak is 10K. With the supply of this embodiment, a pulsed DC power supply of up to 10 kW can be supplied at a frequency between 〇 and 3 50 KHz. The reverse voltage is 10% of the negative voltage. The use of other power supplies will result in different power characteristics, frequency characteristics, and percentage of reverse voltage. The inverse time for this power supply 14 embodiment can be adjusted between 〇 and 5 // s. The filter 15 prevents the bias supply from the power supply 18 from being coupled to the pulsed DC power supply 14. In some embodiments, power supply 18 is a 2 MHz RF power supply and, for example, may be a Nora 25 power supply manufactured by ENI, Colorado Spring Co. Therefore, the filter 15 is a band exclusion filter of 2 Μ Η z. In some embodiments, the filter bandwidth can be as large as 100 KHz. Therefore, the filter 15 prevents the 2 MHz power from being biased to the substrate 16 from damaging the power supply 18. However, RF and pulsed DC deposited films are not completely dense and have a mostly cylindrical structure. These columnar structures are determined by the dispersion loss caused by the structure and the pinholes for the formation of optical applications and barrier layers. The deposited film can be thermally compressed by a viable ion impact by applying an RF bias on the wafer 16 during deposition and can substantially eliminate the columnar structure. In the production of barrier layers according to some embodiments of the invention, for example using a system based on AKT-1 600, a film is deposited on a substrate having a size of about 400 X 5 〇〇-14-(11) (11) 1334194 mm. Above, the active size of the target 12 is about 6 7 5.7 χ 5 8 2.4 8 χ 4 mm. The temperature of the substrate 16 can be maintained between about 50 ° C and 500 ° C. The distance between the target 12 and the substrate 16 can be between about 3 and 9 cm. The process gas (e.g., but not limited to the Ar and 02 mixture) can be inserted into the set chamber 10 at a rate of up to about 200 seem, while the pressure in the equipment chamber 10 can be maintained between about 0.7 and 6 millitorr. The magnet 20 provides a magnetic field force between about 400 and 600 Gauss guided in the plane of the target 12 and moves across the target 12 at a rate of less than about 20 - 30 sec / scan. In some embodiments utilizing the AKT 1600 reaction, the magnet 20 can be a multi-magnet with a track size of about 150 mm x 600 mm. Figure 1C shows a dielectric barrier layer 110 implanted on a substrate 120 in accordance with the present invention. Substrate 120 can be any substrate, such as plastic, glass, twins or other materials. Substrate 120 may further comprise a device or structure that may be protected by barrier layer 110, such as an organic light emitting diode (OLED) structure, a semiconductor junction, or other barrier layer structure. The barrier layer 110 can be a metal oxide wherein the metal can be Al, Si, Ti, In, Sn, or other metal oxides, nitrides, halides, or other dielectrics. For example, by specifying the deposition parameters from the example, 7 kW / 200 W / 200 KHz / 60 Ar / 90 〇 2 / 950 s (7 kW pulsed DC standard power, 200 W substrate, bias power, 200 KHz pulsed The pulse frequency of the DC standard power, 60 seem Ar gas flow, 90 seem 〇2 gas flow, 950 seconds total deposition time), the Ti〇2 deposition of the object can form a high refractive index barrier layer. From one specified at 3 kW/200 W/200 KHz/85 Ar/90 02/ 1 〇 25 (3 kW pulsed DC standard power, 200 W substrate, bias power, 200 Hz for pulse -15- ( 12) (12) 1334194 The pulse frequency of the power of the DC standard, 85 SCCm Ar flow, 90 ug 2 of the total deposition time of 1 025 seconds) 92% A1 and 8% Si in the program (ie 92 - 8 or 92 / The object of 8 layers) may form another example of a low refractive index barrier layer. As discussed further below, the barrier layer according to the present invention can be deposited using a wide range of program parameters. The barrier layer according to the present invention can be formed from any oxide material. For example, 'MgO, Ta2 05, TiO 2 , Ti 407 , Al 2 〇 3 , SiO 2 , concentrated SiO 2 and Y 2 〇 3 . It is also possible to form an barrier layer according to the present invention by using oxygen compounds of Nb, Ba, Sr and Hf. Moreover, the rare earth ion doped barrier layer can be used to produce a photoactive layer. The parameters set herein for depositing a particular layer (e.g., the Ti02 layer and the 92-8 layer discussed above) are merely examples and are not intended to be limiting. Moreover, the individual program parameters are only approximate, and the barrier layers in accordance with the present invention may be formed using a wide range of individual parameters (e.g., power level, frequency, airflow 'and deposition time) in the vicinity of those recited. The dielectric barrier layer 110 is characterized by a high density, uniform, defect-free, amorphous dielectric layer that also has high optical transparency. The film can be deposited in a pulsed DC, substrate biased PVD process from a metal target in an Ar/〇2 gas stream. As discussed further below, certain embodiments of the dielectric barrier layer 11 also have superior surface roughness characteristics. Always, in accordance with the present invention, as discussed further below and with the examples and materials provided, in a MOCON test facility (MOCON refers to Minnesota, Minnesota, Ο C ON Test Services) The dielectric film of the embodiment has a water vapor transmission rate of less than 1 X 1 0 - 2 gm / m7 - / day and often less than 5 x 10 -3 gm / m 2 / day. -16- (13) (13) 1334194 A dielectric barrier stack can be formed by further depositing a barrier layer on the barrier layer MO. Any number of stacked barrier layers can be utilized so that the resulting structure acts not only as a barrier layer but also in other applications in the forming apparatus. Moreover, soft metal gas treatment can be applied before depositing the barrier layer in accordance with an embodiment of the present invention. As explained further below, soft metal breath treatment refers to the exposure of the substrate to soft metal vapor. Figure 2A shows an embodiment of a dielectric stack 120 that can be utilized as a barrier structure and thereby provide optical functionality. Dielectric stack 120 includes multiple barrier layers 101, 102, 103, 104, and 105, in accordance with an embodiment of the present invention. The barrier layers 101, 102, 103, 104, and 105 can be deposited using a deposition process as described in more detail in U.S. Application Serial No. 10/101,863. The depositions described above are generally directed to device 10. Generally, dielectric stack 120 can comprise any number of layers of film. In particular, dielectric stack 120 can include only a single barrier layer. The barrier stack 120 of a special example shown in Fig. 2A comprises five layers of films 101, 102, 103, 1〇4 and 105. In the example of dielectric stack 120 shown in FIG. 2A, dielectric layers 1 〇1, 1〇3, and 010 are formed of a high refractive index material such as titanium dioxide (Ti02). The layers of films 102 and 104 may be formed of a low refractive index material such as alumina (Si 02 ); possibly doped with alumina (e.g., a cation ratio of 92% alumina and 8% alumina, 92-8 films). As shown in Fig. 2A, the barrier stack 120 may be deposited directly on the substrate 100 or deposited on the layer film 107 as shown in Fig. 2D. The film 107 is a layer of film that is protected from atmospheric pollution or physical damage and may comprise an optical or electrical device or another film. The substrate 100 is a substrate on which the layer film 107 or the dielectric stack 120 is formed. In some embodiments, the substrate 1 can also provide a barrier to atmospheric contamination of the layer -17-(14)(14)1334194 film 107. In some devices, a further structure can be deposited over the barrier layer structure 120. Table 1 illustrates deposition parameters for certain example dielectric stack structures 120 in accordance with the present invention. As explained above, the AKT 4 3 00 PVD system using the bias pulsed DC response scanning magneto PVD program as further described in U.S. Patent Application Serial No. 10/101,863, is incorporated herein by reference. Stack 120, which has been previously incorporated by reference. Moreover, the apparatus 10 as described above with respect to Figures 1A and 1B can be assembled in a AKT 43 00 PVD system in a carrier chamber and a degassing chamber, and can be equipped with a plasma shield and a shield heater. As shown in Fig. 2A, the dielectric stack 120 of these examples comprises 5 layers of a 3 Ti02 interlaced layer and 2 layers of 92-8 SiO 2 /Al 203 (92% / 8 % cation concentration). The stacked dielectric stacks 120 shown in Table 1 are deposited directly on the substrate 100. The stacked substrates 100 are first loaded into the carrier of the apparatus 10. The carrier of apparatus 10 is pumped to a base pressure of less than about 5 Torr. The glass or plastic substrate 100 sheet is then transferred to a heating chamber of the apparatus 10 and maintained at a temperature of about 300 ° C for about 2 minutes for any moisture that has accumulated in the degassing substrate 100. For example, for a polymer-based substrate, depending on the plastic substrate used, the preheat step can be eliminated or the preheat step can be performed at a warmer temperature. In some cases, the substrate of the device 10 and the visor heater can be disabled. The base column of Table 1 indicates the composition of the substrate 100 used in the deposition process. In each of the stacks 1 to 6 described in Table 1, the dielectric barrier layer in the dielectric stack 12 is composed of Ding 02/92-8/Ding丨02/92-8/Ding丨02', such as -18. - (15) (15) 1334194 The film films 101, 103 and 105 shown in Fig. 2A are TiO 2 layers and the film films 102 and 104 as shown in Fig. 2A are SiO 2 / Al 203 (92% / 8% cation) concentration). The Ti02 layer is deposited by the parameters shown in the Ti02 deposition program column. Program detail format: target power / bias power / pulse frequency / Ar flow / 〇 2 flow / deposition time. The target power refers to the power supplied to the target 12 of the device 1 . The bias power refers to the power supplied from the bias generator 18 to the electrode 17, wherein the substrate 100 is mounted on the electrode 17 in place of the substrate 16 shown in Fig. 1A and is capacitively coupled to the electrode 17. The flow rates of Ar and 02 across the substrate 100 are then illustrated in units of standard cubic centimeters/min. Finally, assume that there is deposition time. For example, the Ti02 layer of stack number 1 illustrated in Table 1 is a nominal RF power of about 7 kW, a bias power of about 200 W, a pulse frequency of about 200 KHz, an Ar flow rate of about 60 seem, about 90 The 02 flow rate of seem, and the deposition time of about 950 seconds. The thickness measured for a typical Ti02 layer deposited according to the procedure described in the Ti02 deposition program column is shown in Table 1 for the measured thickness Ti02 column. Similarly, as shown in Table 1, the deposition parameters of the alumina/alumina layer depositing each dielectric stack 120 are indicated in the alumina/alumina (92/8) deposition program column as indicated in Table 1. The ion concentration of each of the alumina/alumina layers of the stacked numbers 1 to 6 is about 92% alumina and about 80% alumina. For example, in the stack number 1 described in Table 1, the electricity is about 3 kW. The soil/alumina layer is deposited to the target 12, the bias voltage of the counter electrode 17 is about 200 W, the pulsed DC power supply 14 has a frequency of about 200 KHz, the Ar flow rate is about 85 seem, the 02 flow rate is about 90 seem, and the deposition The time is about 1050 seconds. Usually, in this publication, the dielectric barrier layer called 92/8 film refers to -19 - (16) (16) 1334194 which is deposited by continuous deposition of a substance from 92% alumina / 8%. A barrier layer formed by the electrical barrier layer. A dielectric barrier layer, referred to as a 92 - 8 film, refers to a barrier layer formed in the step from 92% alumina / 8% alumina. For example, a -92-8 film can be formed on a plastic substrate, but a 92/8 film can be formed on a Si wafer or a glass substrate that is less sensitive to heat. In each of the stacks illustrated in Table 1, pulses are applied. Equation 0: The reverse time of the power supply 14 is fixed at about 2_3 microseconds. The distance between the object 12 and the substrate 100 is ~60 μΐη, and the distance between the magnet 20 and the object is 〜4-5 mm. The substrate 100 has a temperature of about 200 ° C and the shielding heater of the device is set to about 250 ° C. The home magnet 20 is set to have an in-situ offset of approximately 20 mm and a scan length of 980 mm. The total pressure in the plasma chamber 53 during deposition of the Ti02 layer is about 5-6 mT. The total pressure in the plasma 53 during the bauxite/alumina layer deposition is about 8 - 9 m T . In accordance with certain barrier stacks of the present invention, 'reactively deposited thin film layers are deposited, or by prior art in the pulsed 'bias deposition process, U.S. Patent Application Serial No. 1/1, 1,086 The barrier layer formed by the illustrated procedure. The pulsed, bias deposition process combines an optical quality vacuum film with a uniquely dense morphology and no columnar defects. The columnar defect has always been a non-biased vacuum film with a uniformity of parts per million and a light refraction and double Control of refraction. Very high resolution ellipticity measurements also exhibit a refractive index of the film that can be attenuated by the attenuation coefficient, which is zero across the visible and near IR regions and is uniform in size per million components, providing substantial Perfect transparency. As a result of the high level of thermal compression and low defect concentration -20- (17) (17) 1334194, it is shown that these very transparent films 40 are more vapor-permeable than the vapor barrier, and also provide superior diffusion barrier protection for the supply of water. Finally, at high voltage stresses, the same film exhibits a higher dielectric breakdown and the result is a low level defect. Figure 8 shows the exposure to high humidity and the high temperature environment for an extended period of time. In the example shown in Figure 8, about 200 mm of TiO 2 was deposited on one of the reactive aluminum layers deposited on a 4 〃矽 wafer. The crystals are maintained in a chamber of about 85 ° and a relative humidity of about 100% for about 500 hours. As can be seen in Fig. 8, no defects were observed on the crystal circle indicating the high-order protection under the reaction aluminum layer. Fig. 9 shows a sample of the alumina/alumina layer according to the present invention after exposure to high humidity for a prolonged period of time in a high temperature environment. In the sample shown in Figure 9, about 10 nm of aluminum was deposited on the -4" germanium wafer. About 100 nm of bauxite/alumina is deposited on the aluminum. Then, the crystals were placed in a pressure oven at about 250 ° C and a saturated vapor of about 3.5 atm for about 160 hours. Again, no defects are visible on the wafer indicating high-order protection under the reactive aluminum layer. In another example, the thin reaction A1 on a Si wafer was tested under the same conditions without the barrier layer and became transparent within a few minutes of testing. The metal oxide film from tens of nanometers to more than 15 micrometers selected by the previously published procedure, as a film, is not only impervious to water vapor and chemical permeation, but also provides protection to a bottom layer or device, preventing gas action or moisture. Entry, as an optical, electrical and/or friction layer or device, imposes substantial manufacturing and environmental limitations on the individual layers of film and device. This subject program has been demonstrated on wide-area substrates of glass and metal and on low-temperature materials such as plastics. - 21 (18) (18) 1334194 Table 4 shows the test by testing an Al2〇3 barrier layer and testing on a - Si wafer. The Vickers hardness (MPa) obtained from a film of Er-doped alumina/citrate (4% by weight alumina/60% alumina). At a 3 kW/100 W/200 KHz/30

The Ar/44 02/t procedure deposits the A1203 barrier layer at 2.2 "s reverse time. 6 kW/100 W/120 KHz/60 with a reversed time of 1.2 //s

The Ar/28 02/t procedure was used to deposit Ah 〇 3 doped with Er and Yb. As can be seen in Table 4, the hardness generally expressed in terms of Vickers is larger than that of the conventionally deposited aluminum film. # Return to Figure 2A, a dielectric stack 120 is deposited on the substrate 1〇〇. Each of the barrier layers 101, 102, 103, 104, and 105 may be an optical layer (i.e., an optically usable layer film). Substrate 100 can be any glass, plastic, metal or semiconductor substrate. The thickness of the layers 101, 102, 103, 104 and 105 of the dielectric stack 120 can be varied to form an anti-reflective coating or a reflective coating. FIG. 2B FIG. 2 shows one of the transparent conductive layers 106 deposited on the dielectric stack 120. The transparent conductive layer 106 can be, for example, a layer of indium tin oxide. 2C illustrates a substrate 100 having a dielectric stack 120 deposited on the top and bottom surfaces of the substrate 100. The second embodiment shown in FIG. 2C includes a layer film 101, 102' deposited on the top surface of the substrate 1. One of the dielectric stacks 120, 104 and 105, and another embodiment of a dielectric stack of layer films 108, 109, 110, 111 and 112 deposited on the bottom surface of the substrate 100. Further, the layer films 108, 100, and 112 may be high refractive index layers (e.g., Ti 2 layer) according to the present invention, and the layer films 1 0 9 and 1 1 1 may be, for example, alumina/alumina layers. Low refractive index layer. An example of dielectric stack 120 deposition parameters can be found in Table 1. As a barrier layer stack according to another example of the present invention which provides good transmission characteristics, a four-layer stacked Ti02/ having a thickness of 12.43 nm, -22 - (19) (19) 1334194 3 6.3 5 nm ' 116.87 nm and 90.87 nm, respectively, is formed. Si02/Ti02/SiO2, deposited on glass, provides high transparency in the wavelength range between approximately 450 nm and 650 rim. The dielectric stack 120 of the protective layer film 107 is shown in FIG. 2D. Layer film 107 is any layer of material that should be protected by a transparent barrier layer. For example, layer film 107 can be a reactive metal such as aluminum, calcium or barium, layer film 107 can be a frangible layer such as a conductive transparent oxide, or layer film 107 can comprise an active optical or electrical device. As discussed above, the individual layers of the dielectric stack 120 provide protection against atmospheric contamination and protect against physical damage to the film 107. In some embodiments, the dielectric layers of dielectric stack 120 (e.g., layers 101, 102, 103, 104, and 105 shown in Figure 2D) are disposed to a thickness to form a transparent or reflective film of a particular wavelength. A skilled artisan can determine the individual film thicknesses in the dielectric stack 120 to form a reflective or anti-reflective film of the dielectric stack 120. In some embodiments in which the film 107 is, for example, aluminum, tantalum, or calcium metal, the device shown in Figure 2D forms a highly stable lens. Figure 2E shows a dielectric stack 120 of a protective layer film 107 in which a layer film 107 has been deposited on the substrate 100. Moreover, the transparent conductive layer 106 has been further deposited on the dielectric stack 120. Fig. 2F shows a structure in which a second barrier stack 120 has been deposited on the bottom surface of the substrate 100. Figure 10 is a cross-sectional SEM image of a dielectric stack in accordance with an embodiment of the present invention. Next, a five-layer Ti02/92-8 stack with a thickness of 550 nm and a thickness of 92-8 bauxite/alumina of 970 nm is shown. The example shown in Figure 10 is a stack of dielectric lenses as used to form microcavity LEDs. Although Figures 2A through 2F illustrate the construction of a five-layer barrier stack 120 and the use of the barrier stack 120 in accordance with the present invention, generally, the barrier stack 120 can be formed from any number of barrier layers. Moreover, the examples of the barrier layers 101, 102, 103, 104 and 105 illustrated in Figures 2A to 2F illustrate examples of optical layers in accordance with the present invention, wherein those optical layers also function as self-protecting barrier layers for which they protect themselves. And above or below there are specific surfaces or devices that deposit them. Moreover, to provide more light active functionality, one or more of the barrier layers 101, 102, 103, 104, and 105 can comprise photoactive dopant ions such as rare earth ions. Moreover, in accordance with the present invention, one or more of the barrier layers 101, 102, 103, 104, and 105 can be a film other than the barrier layer in accordance with the present invention. The barrier layers described in Figures 2A through 2F can be deposited using a pulsed, bias deposition procedure as described in U.S. Application Serial No. 10/101,863 to form a high thermal compression layer having a very low defect concentration material. Figure 3 shows another structure 321 utilizing a dielectric stack of barrier layers in accordance with the present invention. As shown in FIG. 3, structure 321 includes a dielectric stack 3 15 deposited on substrate 316. The substrate 3 16 can be formed, for example, of a glass or plastic material. A transparent conductive layer 314 such as indium tin oxide is deposited on the dielectric stack 315. The layer film 3 1 3 can be, for example, a phosphorous-doped oxide or chloride material, a rare earth-doped concentrated cerium oxide light-emitting device, or organic Luminescent polymer, 0 LED (organic light-emitting diode) or polymer stack &lt;* A metal layer 3 1 2 which may be aluminum and which may be doped or tantalum is deposited on the side adjacent to the layer film 3 1 3 . A second dielectric stack 317 can be formed at the bottom of the substrate 316. The structure 321 illustrated in Fig. 3 is an example of a microcavity-enhanced LED that protects against water and reactive gases that can be diffused by the dielectric stacks 315 and 317 through the substrate 31. When the film 312 is a metal layer, a microcavity, -24-(21) (21) 1334194, is formed between the layer film 312 and the dielectric stack 315. The dielectric stack 315 can externally couple the light emitted from the electro-acoustic layer 313" when the layer film 313 is electrically biased as a transparent conductive layer 3 1 4 acting as an anode and acting as a cathode conductive layer. When the voltage is between 312, the film 313 emits light. The dielectric stack 315 and the dielectric stack 317 layer may be arranged to include light emitted by the interlayer film 317 and the metal layer 312 interlayer film 313 to form an optical etalon arrangement for directing light along the substrate 31. In addition, the dielectric layer 3 17 can be arranged to transmit the light generated by the layer film 313, and thus the monitor arrangement is formed with light that is substantially normally emitted to the substrate 3 16 . Figure 11 illustrates the transmission of data collected from an example of a dielectric stack in accordance with the present invention. The metrology equipment used to collect the results of the data in Figure 11 is a Perkin Elmer Lambda-6 spectrometer. As described above, four samples were measured and each was a 5-layer stacked Ti02 / 92-8. Both samples have the same thickness layer (55 nm Τί〇2 and 1 〇〇 nm 92-8). As illustrated in Figure 11, the two different operations have almost the same transmission spectrum that exhibits the reproducibility of the deposition procedure. The third example has different thicknesses arranged to allow the transmitted light to move toward blue. A fourth example was produced after maintaining the third example at a test condition of 8 5 / 8 5 (85 ° C 8 5 ° C humidity) for 120 hours. It can be observed that humidity and heat do not have a significant impact on the transmission characteristics of the mirror stack, again exhibiting this dielectric stack functionality as a protective layer and an optical layer (ie, no measurable moisture movement). Similar results were obtained after 5 〇 〇 hours of testing under 8 5 / 8 5 conditions without measurable moisture movement. The second diagram shows an example of another structure 633 of a microcavity-enhanced LED junction 321 as described in FIG. 3, which is constructed as shown in Figures 2A through 2F - 25 - (22) (22) 1334194 622 Covered and protected. As shown in Fig. 6, in the structure 321, the film films 314, 313 and 312 have been patterned. Structures 622 can be formed separately on opposite sides of a substrate 619 with dielectric stacks 61 8 and 620. Dielectric stacks 618 and 620 are formed as described in the dielectric stack 120 of Figures 2A through 2F. In order to seal and protect the structure 3 2 1, the structure 6 2 2 is then formed on the structure 3 2 1 to form an epoxy-based resin. For example, the epoxy-based resin layer 621 can be an EVA epoxy resin. FIG. 7 shows another structure 700 having an example of a microcavity-enhanced LED structure 321 as shown in FIG. 3, which is like those of FIGS. 2A to 2F. The structure 623 shown in the figure is covered and protected. The cover structure 623 includes a substrate 619 on which a dielectric stack 620 is deposited, and an epoxy resin is formed on the device 321. Fig. 4 illustrates another example of the barrier layer of the present invention which is used as an electrical layer (i.e., a layer film having an electrical impedance function or a dielectric for a capacitor structure). The structure shown in Fig. 4 illustrates an example of a bottom gate transistor structure 42 in accordance with the present invention. The transistor structure 42 is formed on a substrate 416 which may be a plastic or glass material. In the embodiment illustrated in Figure 4, a dielectric stack 415 in accordance with the present invention is deposited on the top surface of substrate 416 and a second dielectric stack 417 is deposited on the bottom surface of substrate 116 in accordance with the present invention. As noted above, each of dielectric stacks 417 and 415 can comprise a layer of dielectric material having a high and low refractive index. As described above, the high and low refractive index dielectric materials such as Ti 2 and alumina/alumina layers each have a low voltage flat band and a low surface defect, and thus are suitable for a thin film transistor structure. - The semiconductor layer 423 is deposited on the barrier stack 415 and patterned. The semiconductor layer 423 may be, for example, a semiconductor such as chopped or ruthenium or may be a zinc or polymer material. The layer films 424 and -26-(23) (23) 1334194 425 form source and drain layers in contact with the semiconductor layer 423. Layer film 426 may be formed of a material having a dielectric constant, such as any dielectric layer forming dielectric stacks 415 and 41, for example, a high dielectric strength Τι 2 material deposited by the procedures described herein. . The layer film 427 is an inner layer film and the layer film 428 is a gate metal. Figure 5 shows an example of a top gate transistor device 509. The transistor device 592 is formed on a substrate 516 that is protected from physical wear and abrasion of atmospheric contaminants (e.g., &apos;water or gases) and dielectric stacks 515 and 517. Dielectric stacks 515 and 517, such as dielectric stack 120 discussed above, are formed from _ or more layers of optical material. Gate layer 530 is deposited on dielectric stack 515. Layer film 530 can be a metal layer such as aluminum or chromium. A gate oxide layer 531 is deposited over the layer film 530. A semiconductor layer 532 is deposited on the gate oxide layer 531 on the layer film 530. The semiconductor layer 532 can be similar to the layer film 423 of Fig. 4. The layers 5 3 3 and 5 3 4 are source and drain layers, respectively, and are similar to the layers 424 and 42 8 of the device 422 in FIG. 4 and may, for example, be derived from a conductive metal, a conductive oxide, or a conductive polymer. The matter is formed. The dielectric stack with barrier layers in accordance with the present invention can have an atomically smooth film surface regardless of film thickness. Moreover, the dielectric stack with barrier layers in accordance with the present invention has an unmeasurable film transparency that is different from zero. These dielectric stacks represent a new capability for bias barrier film defect levels and barrier protection. Products that require dielectric barrier protection to prevent water and oxygen, such as 0 LED displays, can tolerate a defect per square centimeter. Some examples of barrier layers such as 2.5 nm and thicknesses such as 15 microns have been deposited to exhibit an average surface roughness of about 0.2 nm and represent a non-destructive procedure for the deposition of all thin layers -27- (24) 1334194 The film thickness exhibits the surface of the optical article, representing a high amorphous film which can be achieved by the procedures of the present embodiment. The dielectric barrier layer according to the present invention has been shown to protect the ultra-thin film in pure vapor of 3.5 ATM. Under pressure from 125 to 250 ° C for hundreds of hours, no defects on the 100 nm 矽 wafer, here, the long-term protection of titanium oxide and alumina / silicate barrier layer reaction film, among them The reaction membrane is a pinhole that is free to one. A pinhole with a large area of 75 square centimeters and a 100 nm crystal dielectric barrier will be transferred into a pinhole with a density of one square centimeter. As shown in Figures 8 and 9, there are two wafers, one having a barrier dielectric film having titanium dioxide free of failure. The two crystals are 150 square centimeters. If there are 1 defect on the two wafers, the defect is 0.00666 per square centimeter. However, because the wafer is free of defects, the actual defect density cannot be measured. Then, as shown, the trap density is less than 0.01 3 3 per square centimeter and the majority is less than 0.007. In some embodiments of the present invention, softening such as indium or indium-tin can be performed before depositing the barrier layer as discussed above or more. metal. Most of the soft metal treatment can be used to release the stress between the dielectric substrates. Moreover, the soft metal breath treatment can further effect the growth of the pinhole or the defect-free barrier film, and the formation of the 12A and 12B drawings shows a single barrier layer structure 12A in accordance with the present invention with or without a soft metal atmosphere treatment. One of the barrier layers 1 203 as described above is a direct deposition barrier layer. Reactive aluminum metal in steam hot oxygen. As a result, it can be provided or protected on the circle of two wafers. • The sand acid of about 0.0133 and the total area between the circles will be shown only from the two wafers, and the actual lack of g square centimeter The barrier layer and the substrate are treated as a nucleus free on the substrate. The bottom 1201 sinks 1200. On the base 1201 -28- (25) (25) 1334194. Substrate 1201 can be any suitable substrate material, such as a glass, plastic, or Si wafer. Substrate 1201 may, for example, comprise a QLED structure or other light active structure that requires a high total amount of light processing or may utilize a barrier layer as one of the electrical layers. The barrier layer 1203 can be one or more of the barrier layers described above. As explained in Fig. 12A, the barrier layer 1 203 can develop a surface roughness related to stress during deposition and use. Figure 12B illustrates the results of depositing barrier layer 1203 after soft metal breath treatment in accordance with certain embodiments of the present invention. As shown in Fig. 12B, the stress is significantly reduced, forming a barrier layer with better surface smoothness. The soft metal breath treatment according to some embodiments of the present invention involves exposing the substrate to a soft metal vapor for a short period of time, followed by heat treatment. For example, an indium-tin breath treatment involves exposing the substrate from an indium-tin standard to indium-tin in a pulsed DC process followed by a heat treatment. Direct exposure to indium oxide and tin vapor does not produce the particularly advantageous results described below. The bond is not bonded by a special theory that may be proposed in this publication. In/ Sn breath treatment reduces the stress in the deposited barrier layer and improves surface smoothness and MOCON WVTR performance. In a special example of forming the barrier layer structure 1 200, a soft metal breath treatment embodiment is implemented on a plastic substrate 1201. From the indium tin (90% / 10%) target, for example, an indium/tin breath treatment can be performed. The procedure for performing indium/tin breath treatment can be specified as 7 5 0 W/〇 W/ 200 KHz/20 Ar /〇 〇2/1 leap seconds. In addition, 90% indium/10% tin, using the Pinnacle Plus PDC power supply AKT 1 600 PVD system in the pulsed PVD system 10 with 950 W fixed power operation (Figure 1A) ( -29- (26) (26) 1334194 pulse frequency 200 KHz, reverse time 2.2 / / sec) up to 10 seconds 20 seem Ar flow to operate pulsed DC, bias, wide-scale PVD program" Then, continue to breathe and will Substrate 1201 is transferred into one of the carriers of the AKT 4 3 00 tool and pumps the tool to a base pressure less than about Torr. The substrate was then transferred to a 130 ° C hot chamber at 13 x TC heat treatment for about 25 minutes. Then the substrate 1 2 0 1 (treated with the above indium/tin breath) was transferred to the deposition barrier layer. The second chamber at 1203. As indicated above, the barrier layer 1 2 03 can be formed by depositing one of 92-8 aluminosilicate (92% Si/8% A1) at room temperature. Deposition 92-8 barrier The program parameters of the layer 1 20 3 embodiment can be 3 kW / 200 W / 200 KHz / 85 Ar / 90 02 / x. Therefore, with about 3 kW PDV power, about 200 KHz pulse frequency, and about 2.2 microseconds This procedure is carried out in reverse time. The bias power can be maintained at about 200 W. A gas flow of about 85 seem Ar is used with about 90 seem 02. In the particular embodiment of deposition, the deposition procedure is a power cycle, wherein the ON cycle is about 180 The second is OFF and the OFF cycle is about 00 seconds long, up to 9 cycles. The barrier layer 1 203 is formed to a thickness of about 1600 A. In a special test, a barrier structure 1200 is deposited by the above procedure, and the substrate 1201 has a size of 6 吋 x 6吋三三 plastic film (Dupont (Feijih) PEN film 200 / zm thick, called PEN substrate). Usually, in Any barrier layer may be deposited after the soft metal breath treatment (eg, '92 or 8 or T0 0 2 layers discussed above). As discussed previously, a program example of a barrier layer embodiment in accordance with the present invention is presented herein, but broadly The program parameters can result in a barrier layer in accordance with the present invention. -30- (27) (27) 1334194 Then, the barrier layer structure on the substrate 1 2 Ο 1 can be tested using various techniques. In particular, the stress in the film 1 203 can be measured using Flexus stress measurement technology. The surface roughness can be measured by atomic force microscopy (AFM), and the water vapor transmission rate (WVTR) can be a high pressure, high humidity pressure furnace device. Measured. Figure 13 illustrates a Flexus scanning assembly 1300 that can be used to measure the barrier layer structure 1 200. In the Flexus scanning assembly 1300, a laser beam 1310 is directed to the surface of the barrier layer 1203 by a lens 1312. "By detector 1314 off-target, off-beam sweep 16 light can be 13-diameter angle half-measurement rate 14 polarizer 13 and its 011401 ί 2 3 2 1Λ Ti 1* bottom of the detector. Beam cross check and light And 0 shot. 'Angle reverse 12-way bias 13 partial 03 piece, 12 beam mirror layer light, wall shot 10 system barrier anti-13 off from 12 shots 13 thunder 18 test piece with 13 Mirror package . The film stress in the barrier 1 203 can be calculated using the change in the substrate deformation measured by the Flexus device 1 300 when the optical portion 13 16 is scanned. As shown in the relationship 1 3 1 8 , the reflected beam angle can be monitored during the scan and the inverse of the curvature radius R of the substrate 1201 can be calculated from the angle derivative function as a function of the position in the scan. In some cases, The Flexus device 1 3 00 can utilize a dual wavelength technology to increase the range of film types that can be measured by the tool. Then, because different film types will reflect different wavelengths of light, the Flexus device 1 300 can have more than one laser capable of scanning the wafer 1 3 1 0. Moreover, the reflected laser intensity indicates a good measurement quality. Generally, the low light intensity of the detector 1314 indicates a poor measurement condition. -31 - (28) (28)1334194 In the Flexus device 1300, the stress can be determined using the STONE Y equation. In particular, the measurement of the curvature of the film 123 can be determined by measuring the curvature of the deposited film before the film and the radius of curvature of the deposited film 1203. In particular, according to the Stowey equation, the available stress is where ES/(1-VS) is the biaxial modulus of the substrate 1201, the stress of the substrate 1201, ts is the thickness of the substrate, tf is the thickness of the film, and RS is the curvature. The pre-deposition radius, and Rf is the radius after the curvature. In order to obtain this result, the measurement of the two curvature radii should be performed according to the same tool to minimize the systematic error in the measured | radius. In addition, since the shape of the wafer is unique and the stress is calculated based on the change in the deformation of the substrate, each wafer should have a measurement of the reference line radius. A positive radius indicates tensile stress and a negative radius indicates pressure should be . As shown in Figure I4, the wafer bow can be calculated by measuring the maximum deflection point from the string connecting the end points of the Flexus device 1300. Table 2 lists the stresses measured for the barrier layer 1 2 0 of the several embodiments, wherein the barrier layer 1203 is a 92-8 film as discussed above, and does not have a nucleation layer formed by soft metal breath treatment. [202. As shown in Table 2, Sample 1 was a 1.5 KA 92 - 8 film deposited on a Si wafer substrate with an actual thickness of 1760 0 A. The stress formed at about room temperature is - 446.2 MPa. Sample 2 is a 1.5 KA 92-8 film having a stress of about -460.2 MPa and an actual thickness of 1670 A on the A1 gas deposition. In sample 3, a stress of -3 3 0.2 MPa was deposited with indium gas, and a thickness of 1 860 Å was added to a 1.5 KA 92-8 film having a thickness of 1 860 A, which was almost one MPa lower than any of the other depositions described. . -32- (29) (29) 1334194 Figure 15 shows the compilation of several samples 1 'sample 2, sample 3, as shown in Table 1, above a temperature cycle. The temperature cycle consists of heating from room temperature to 1 60 °C and cooling back to room temperature. In the germanium wafer substrate, it is assumed that the wafer radius does not change with temperature. The stress data in each case is taken at the temperature shown. As can be seen from Figure 15, the 92-8 film deposited on the indium-gas treatment is 92-8 film deposited on top of the deposited aluminum-aerate treatment or deposited on the substrate without 'soft metal odor treatment. The 92_8 film exhibits very little stress. The surface roughness of a film can be measured using an atomic force microscope (AFM). In the AFM, a mini probe is actually scanned on a film surface to bring the probe into contact and along the surface of the film. The probe has a small tip and therefore correctly monitors the surface roughness of a characteristic nanometer. Fig. 16A shows the surface roughness of a PEN substrate (DuPont Teijin PEN film 200 / / m thickness) before depositing a barrier layer according to the present invention. As shown in Figure 16A, the PEN substrate has a mean surface roughness of 2.2 nm on average, a mean square root RMS of 3.6 nm, and a typical maximum roughness of about 41.0 nm. As shown in Fig. 16B, deposition of 1.5 k of 92-8 after indium-tin breath treatment on a PEN substrate resulted in an average surface roughness of 1 · 〇 nm, an RMS roughness of 1.7 nm and a maximum roughness. It is 23.6 nm. As shown in Figure 16C, an indium tin oxide (ITO) atmosphere treatment was performed prior to the deposition of the 1.5 KA 92-8 dielectric barrier film, resulting in an average roughness of 2.1 nm, an RMS roughness of 3.4 nm, and a maximum roughness of 55.4 nm. . The deposition shown in Figure 16C was carried out with a PEN substrate of 125/zm instead of a PEN substrate of 200 m. Therefore, the direct I TO treatment is not implemented and the indium-tin atmosphere is treated as shown in the figure (30) (30) 1334194 16D, and a barrier layer of 1.5 KA is deposited directly on the 125# m PEN substrate to form a barrier layer. The average surface roughness is about 5.2 nm, the RMS roughness is 8.5 nm, and the maximum roughness is 76.0 nm. Therefore, for the surface roughness, although the ITO breath treatment is better than the soft metal treatment at one point, the indium-tin breath treatment results in an optimum surface roughness of an average surface roughness of about 1.0 nm. Figure 17 illustrates a water vapor transmission (WVTR) test apparatus 1 700 that can be used to characterize a barrier film in accordance with an embodiment of the present invention. The sample 1701 is mounted in the apparatus 1 700 in such a manner as to isolate the surface of the substrate 1201 (Fig. 12) from the surface of the barrier layer 1 203 (Fig. 12). A gas free of moisture is supplied to the crucible 1702, one surface of the sample 1701 is contacted, and introduced into the sensor 1 703 which monitors the water vapor from the sample 1701. The wet gas is conducted via 埠1 705 to the opposite side of the sample 1701. An RH probe 1 704 can be utilized to monitor the water capacity of the gas input to 埠1,075. Then, the sensor 1 7 0 3 monitors the water vapor transmitted through the sample 1 70 1 . This test was conducted in Mocon, 7500 Boone Avenue North, Minneapolis, Minnesota, MN 5 5428, in accordance with ASTM F1M9. Instruments that Mocon used for WVTR testing have a detectable transmission range of 0.00006 gm / 100 in2 / day to 4 gm / 100 in2 / day. For example, the lower detection limit of the Mocon 3/31 instrument is about 0.0003 gm / 100 in2 / day. The formation of a 气 1 atmosphere treatment, followed by the deposition of a barrier layer of -1_5 KA 92 - 8 barrier layer on a 2 〇〇; zm PEN substrate The deposition caused the Mocon test WVTR to be 0.0031 gm / 100 in2 / day. Forming an indium-gas treatment, -34- (31) (31) 1334194 followed by a barrier layer of 1_5 KA 92-8 on a 200//m PEN substrate to form a WVTR that is not measurable in the Mocon 3 / 31 instrument ( That is, the transmission rate is less than 0.003 gm / 100 in2 / day). As discussed further above, Figures 16A through D illustrate a soft metal breath treatment (especially an indium breath treatment) that can play a role in determining the surface roughness of the barrier layer deposited in accordance with the present invention. The surface roughness of a barrier layer can also affect the WVTR characteristics of a barrier layer. A smoother barrier layer results in better WVTR performance. As such, Figure 16A shows an unshielded 200y m PEN substrate without barriers. Fig. 16B shows a 200//m PEN substrate having a barrier layer of 92-8 having a thickness of 1 500 A deposited in accordance with the present invention after an indium/tin treatment. Figure 16C illustrates a 20 〇em PEN substrate with a -1500A 92-8 barrier layer deposited after ITO breath treatment. Figure 16D is a 20 〇v m PEN substrate having a 1500A 92-8 barrier layer deposited directly on the substrate. As can be seen, the structure of Figure 16B represents the optimum surface smoothness characteristics. Table 3 illustrates the barrier layer of several examples with surface smoothness characteristics and Mocon WVTR test results. In Table 3, the samples described in columns 1 - 4 are about 2000 A thick - deposited on -700 / / m thick polycarbonate (General Electric Corp. LEXAN) - or on both sides 92 - 8 layers (as mentioned above). This data indicates that the barrier layer structure (columns 1 and 2) coated on both sides is better than the one side structure (columns 3 and 4) in the Mocon WVTR test. Columns 5 through 8 illustrate various depositions on a P EN substrate (columns 5-6 illustrate deposition on a 200/zm PEN substrate and columns 7 and 8 illustrate -125-35-(32) (32)1334194 β m PEN substrate deposition). The indium breath treatment parameters refer to the indium/tin breath treatment as discussed above. As explained earlier, the 1 6 B to 1 6 D graph represents the AFM parameters. As discussed previously, the optimum surface smoothness and optimum WVTR characteristics are indicated in column 6, which is followed by deposition of a 9-2-8 film after indium breath treatment. The data in column 9 indicates that indium breath treatment (indium/tin) has higher power on the thinner (125//m) PEN substrate. Assume that the thermal stress on the 125 /zm PEN substrate is worse than the 200/zm PEN substrate. Further representation of this effect, together with Figures 19A and 19B, is shown in the data of columns 30 through 33. The data in columns 30 and 31 contains an indium/tin treatment on a 200 ym PEN substrate (in WO W) followed by a deposition of about 7.5 KA 92-8 film, as shown in Figure 19A, which produces a Very smooth surface (for example, on average about 1.1 nm) and Mocon WVTR features that are not detectable on Mocon 3/ 3 1 test equipment. Indium/tin treatment, followed by deposition of a 1.5KA 9 2 - 8 film on the 125y m.PEN substrate. The data in 3 2 and 3 3 indicate poorer smoothness (average roughness of about 2.0 nm) and The WVTR test of the Mocon device is approximately 1.7 x 1 (T 2 gm/m 2 /day. The 92-8 deposition described in columns 30 to 33 is performed simultaneously in a single operation. Tables 1 and 2 in Table 3 The data indicates that the indium breath treatment plus 丨25 is deposited on the 1.5 P Ti02 on the m PEN substrate. The data in the columns ι〇 and η represent the indium/tin sinter treatment plus 125&quot; m PEN on the substrate 1. 5 KA 92-8 Deposition. As can be seen in Table 3, the WVTR characteristics of the 92-8 layers are not only the WVTR characteristics of the order of magnitude better than the Ti〇2 layer. The representative smoothness of the columns 12 and 13 is given in the 22A. 2 B shows the representativeness of the columns 1 〇 and 1 -36 - (33) (33) 1334194. As shown in Table 3, the average smoothness of the 92 - 8 layers is much better than that of Ti02. Average smoothness. The data in Tables 14 and 15 illustrate the treatment of indium/tin on a 125/zm PEN substrate followed by a 92-8 film. Columns 14 and 15 can be combined with column 3. 2 Comparing the data in 3 3, it is treated with indium/tin on a 1 2 5 // m PEN substrate, followed by deposition of a 1.5 - 8 film of 1.8 KA. The smoothness between the LEXAN and PEN substrates is In comparison, even if it can be seen by comparing the 2 1 A and 2 1 B diagrams, the amorphous material is different, that is, the barrier layer according to the present invention deposited on the LEX AN substrate means more particles than the barrier layer deposited on the PEN substrate. The data in Tables 1 to 6 show the different program parameters for the indium/tin gas treatment, followed by the deposition of 1. 5 KA 92 -8 on a 200&quot;111 PEN substrate. In one setting, the current is set instead of the power. The data in column 16 is taken as 6 · 1 4 amps of electricity. In the barrier layer of the column of the description of column 1.7, the indium/tin is implemented with an operating power of 1.7 KA. Breath treatment. In the barrier layer described in column 18, the indium/tin gas treatment is performed with an operating power of 75 0 W. In each case, the Mocon WVTR characteristics of the barrier layer formed are lower than for Mo con 3/ 3 1 The detectability of the instrument. The information in Table 1 in columns 1 9 - 29 illustrates the different indium/tin gas treatments and their formation The surface smoothness of the wall layer and its effect on the Mocon WVTR characteristics. The data in columns 1 9-22 are all examples in which the vapor indium layer is replaced by a vapor indium layer instead of the indium/tin gas treatment. The surface roughness feature is illustrated in Figure 18A and represents an average roughness of about 1.1 nm. However, as shown in Fig. 18A, the morphology is very granular, assuming that there are many -37-(34) (34) 1334194 holes, and the MoconWVTR test size is 〇.8gm/m2/day. The data shown in column 2.3 of Table 3 illustrates the case where the 200//m PEN substrate is not preheated by indium/tin gas treatment and before the deposition of 1.5 KA 92-8, as shown in Figure 18C. 1.5 KA 92-8 has an average surface roughness of approximately 5.2 nm and a Mocon WVTR of approximately 0_8 gm/m2/曰, or the same as shown in columns 19-22, as shown by the indium vapor phase data. Therefore, the same characteristics result in the application of indium vaporization treatment. The information described in Tables 24 - 29 is treated as indium/tin at 28 ° C instead of room temperature. As illustrated in Figure 18B, the average surface roughness is 1.1 nme. However, the Mocon WVTR data is approximately 3x10 - 2 gm/m2/day. This is much larger than the enthalpy shown in the similar deposits of columns 30 and 31, which is below the 5x10 - 3 gm/m2/day detectability limit of the Mocon 3/31 instrument. The data in columns 34 and 35 illustrate the deposition of a layer of 1 · 5 KA 3 6 - 6 5 after deposition of indium/tin on a 200//m PEN substrate (ie, deposition with 35 % Si and 65 % A1). ). As illustrated, the Mocon WVTR is 1.4 x 10_1 gm/m2/day, which represents the possible necessity of creating a biasing procedure for the barrier layer according to the present invention. Figure 20 illustrates the film gate oxidation which can also be deposited on the substrate 2001. The barrier layer 2002 for use. The thin film gate oxide 2002 can be deposited as a barrier layer according to the present invention. Such a layer film which is advantageous for protecting moisture and oxygen-sensitive crystal layers is mixed, for example, ruthenium, tin oxide, zinc oxide, or pentabenzene, and is used as a thin oxide electric layer. Substrate 2 00 1 can comprise any electrical device that can be formed, for example, on a wafer, plastic sheet, glass sheet, or other material. The barrier layer 20 02 can be a thin layer of, for example, from -25 to (35) (35) 1334194 from 25 to 500 A. Due to the lack of response to the elimination of titanium oxide, titanium oxide has been known as a preferred material for biological cultivation. In addition, it is preferred that the TiO2 film which is immunologically free of different barrier layers can simultaneously protect a device such as a voltage or charge sensor or an optical device such as a waveguide, and exhibits due to its high dielectric constant or its optical index. Capacitive or optical to the role of the coupling device. Due to the proximity of the sensor provided by a very thin, high-k dielectric such as Ti〇2, a capacitor array can be coupled with a high capacitive density. In fact, a one- or sub-micron array can be used to monitor electrical activity, amplitude, and the direction of very low electrical signals such as those associated with electrical signals in a single axis of a single ganglion. Conversely, it can also be used to electrically couple stimuli to adjacent cells or tissues. With this capacitive barrier layer, high resolution is coupled to the photoreceptor, auditory nerve, or nerve tissue of size 5 to 50 &amp; 11^〇-f a r a d s / m 2 as the only possible and no immune response. Other embodiments of the invention will be apparent to those skilled in the <RTIgt; This publication is not limited to any theory or operational assumptions used to describe any of the results presented. The patent specification and examples are to be regarded as illustrative only, and the true scope and spirit of the invention is represented by the following claims. As such, this application is limited to the following request items. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A and 1B illustrate a deposition apparatus for depositing a barrier layer film according to the present invention. -39- (36) (36) 1334194 Figure 1C illustrates a barrier layer deposited on a substrate in accordance with an embodiment of the present invention. 2A, 2B, 2C, 2D, 2E, and 2F illustrate an example of a dielectric stacking device having a barrier layer according to an embodiment of the present invention. FIG. 3 is a view showing microcavity enhancement using a dielectric layer of a barrier layer according to an embodiment of the present invention. LED structure. Fig. 4 is a view showing a bottom gate transistor device having a barrier layer dielectric stack according to an embodiment of the present invention. Fig. 5 is a view showing a top gate transistor device having a barrier layer dielectric deposition according to an embodiment of the present invention. Figure 6 shows an example of a microcavity-enhanced LED structure similar to that shown in Figure 3, further protected by a dielectric stack of barrier layers in accordance with an embodiment of the present invention. Figure 7 illustrates another example of a microcavity-enhanced LED structure similar to that shown in Figure 3, further protected by dielectric packing of a barrier layer in accordance with an embodiment of the present invention. Fig. 8 shows an example of a barrier layer of τ i 〇 2 according to an embodiment of the present invention, which is exposed to a reaction layer after exposure for a prolonged period of time in a high humidity 'high temperature environment. Fig. 9 is a view showing an example of an alumina/alumina barrier layer in accordance with an embodiment of the present invention, which is exposed to a high-humidity high temperature environment for an extended period of time and deposited on a reaction aluminum layer. Figure 10 is a SEM cross-sectional view showing an embodiment of a barrier layer dielectric stack in accordance with an embodiment of the present invention. (37) (37) 1334194 Figure 11 shows a transmission rate versus wavelength diagram of various barrier layer dielectric stacks in accordance with an embodiment of the present invention. 12A and 12B illustrate a single barrier layer structure deposited with and without a soft metal smear treatment according to an embodiment of the present invention. Figure 13 shows a Flexus stress measurement device that can be used to test a barrier layer. Figure 13 shows the wafer square diagram measured by the Flexus stress measurement equipment. β Figure 15 illustrates the stress at various deposition barrier layers in accordance with an embodiment of the present invention as a function of temperature via one single temperature cycle after deposition. The 16th, 16th, 16th and 16th views represent atomic force microscopy of the surface roughness of certain barrier film films in accordance with an embodiment of the present invention. Figure 17 illustrates a water vapor transmission test that can be used to characterize the barrier layer, which is deposited in accordance with an embodiment of the present invention. Figures 18 to 18D illustrate the effect of different In/Sn breath processing parameters on the surface roughness of the barrier layer deposited in accordance with the present invention. • Figures 19A and 19B illustrate the basal action of surface roughness. Figure 20 illustrates a barrier layer in accordance with the present invention which is further operated with a thin film gate oxide. 21A and 21B illustrate the effect of the substrate composition on the surface roughness of the barrier layer deposited in accordance with the present invention. 22A and 22B illustrate the barrier layer deposition characteristics of the embodiment of the effective surface roughness according to the present invention. The analogy or the same phase has the indications of the same phase. It is in the middle of the figure. This is in -41 - (38) 1334194 [Main component symbol description] 10 Reactor device 12 Target 14 Pulse DC power supply 16 Substrate

17 Electrode 18 Dielectric barrier layer 20 Magnet 25 Filter 53 Plasma 54 Insulator 100 Substrate 101 Barrier layer

102 barrier layer 103 barrier layer 10 4 barrier layer 10 5 barrier layer 106 conductive layer 107 film 10 8 film 109 film 110 film -42 - 1334194 (39) 110 dielectric barrier layer 111 film 112 film 120 substrate 120 dielectric stack 3 12 metal layer 3 13 film 3 14 conductive layer 3 15 dielectric stack 3 16 substrate 3 17 dielectric stack 3 2 1 structure 4 15 dielectric stack 4 16 substrate 422 transistor structure 423 semiconductor layer 424 layer Film 425 film 426 film 427 film 428 film 5 15 dielectric stack 5 16 substrate 5 17 dielectric stack

-43 - (40)1334194 529 Transistor device 5 3 0 Gate layer 53 1 Gate oxide layer 5 3 2 Semiconductor layer 5 3 3 Film 5 34 Film 618 Dielectric stack

6 2 0 Dielectric stack 621 Epoxy resin layer 622 Structure 623 Structure 6 3 3 Structure 700 Structure 1200 Structure 1201 Substrate

1 202 nucleation layer 1 2 03 barrier layer 1 3 00 FLEXUS scanning assembly 13 10 laser beam 1312 lens 13 14 detector 1316 optics 1 7 0 0 water vapor transmission test equipment 1701 sample -44 - (41) 1334194 1702埠1703 Sensor 1704 Probe 1705 埠200 1 Base 2002 Barrier Layer (42) Measured Thickness Bauxite / Bauxite (92-8) (Human) 980 910 1000 1000 1000 1000 Bauxite / Bauxite (92-8 ) Deposition procedure 3KW/200W/200KHZ /85Ar/90O2/1005 3KW/200W/200KHz /85Ar/9002/1006 3KW/200W/200KHZ /85Ar/90O2/1025 3KW/200W/200KHZ /85Ar/90O2/1025 3KW/200W /200KHZ /85Ar/90O2/1025 3KW/-200W/200KHZ /85Ar/90O2/1025 Measured thickness Ti02(A) 580 510 550 550 550 550 Ti〇2 deposition procedure 7KW/200W/200KHZ /60Ar/9002/950s 7KW /200W/200KHz /60Ar/90〇2/835s 7KW/200W/200KHz /60Ar/9002/901s 7KW/200W/200KHz /60Ar/9002/901s 7KW/200W/200KHz /60Ar/9002/901s 7KW/200W/200KHz /60Ar/9002/901s Stacked layer composition Ti02/92-8/ Ti02/92-8/ Ti〇2 Ti02/92-8/ Ti02/92-8/ Ti〇2 Ti02/92-8/ TiOz/92-8 / Ti02 TiOz/92-8/ TiOz/92-8/ Ti〇2 Ti02/92-8/ Ti02/92-8 TiOz/92-8/ T I02/92-8/ Ti02 S bottom 6 microscopic 戦 slide +1 6 吋 wafer i 6 microscope slide + 16 吋 wafer 2 soda glass + 4 micro 戦 slide 2 sodium glass + 4 micro戦 slide 4 microscope slide 3 soda glass + 4 microscope slide - &lt;N m inch (43) 1334194 square (M m) oo 11.74 1 1_ 1.38 10.18 4.36 10.25 film thickness (human) N / A 1760 N/A 1760 N/A 1860 MPa stress N/A -446.2 N/AI -460.2 N/A -330.2 Radius (m) -4.76E+03 -145.978 i_ -4.10E+03 -169.482 -230.249 -67.169 Temperature . C ON (N (N (Ν &lt;= Uns ife pre-deposited 1.5K Λ 92-8 film deposition / indium-free atmosphere treatment pre-deposited aluminum gas deposition, then 1.5K human 92-8 film treatment pre-deposited indium deposition, then 1.5Κ人92-8膜处理&gt; Sample丨 Sample 2 Sample 3

-47 - (44)1334194 AFM result £ 1 cS ® E pQ q — II c —II i — II Splash ^ Pi ms = 5囫~ α卜 Q ^ T i -i 1 ga ^ pi pi cm MOCON WVTR (g /100 吋2/day) 1.1160E-02 8.9900Ε-03 1.2865E-0I 2.6660E-01 9.7805Ε-01 4.6500E-03 6.2310E-01 MOCON WVTR (g/100 吋2/曰) 7.2000E-4 5.8000Ε-4 8.3000E-4 !_ 1.7200E-2 _I 6.3100Ε-2 3.0000E-04 4.0200E-02 Thickness β m 700 700 1_ 700 700 200 200 (N «1 越底材料LEXAN LEXAN LEXAN _. LEXAN 1 PEN Q65 PEN Q65 PEN Q65 Sample Description 2K of Polycarbonate Deposited on Double Sided-A 92-8 ϋ m ® &lt; 1 ^ Aluminium w ^ m ^ i 2K of Polycarbonate 92-8 Poly Carbonate 2K 92-8 aluminum breath (500W 10 seconds + 1300 °C heat treatment) + 1.5K on PEN 92-8 indium breath (760W + 5 seconds + 130 °C heat treatment) + 1.5K on PEN Λ 92-8 Indium-free atmosphere + 丨30°C preheating + 1.5KA on PEN 92-8 Sample 1 (film (coated on both sides)-Α) 2 (film (coated on double)-B 3 (fade film (coated on one side) - A) 4 (film (coated on one side) - Α) 5 (Al + 1.5k.928) 6 (InB + 1.5K928) 7 (I02-MOCON ID: 1619-0003)

-48 - 1334194

Ra = 2.1 nm RMS = 3.4 nm Rmax = 55.5 nm: see Figure 6C Ra = 3.4 nm RMS = 4.2 nm Rmax = 2.9 nm See Figure 22B B c Z _ r- ON &quot;csj &lt;n CQ inch·寸·II ^ II gg 广璐TO CZ t— η U aL U a ^ SC ^ 囫c Pi &lt; ^ ON II ^ t- II ^ ^ 丨丨g目c moving pi pd. ΰ c 3.8595E-01 4.0145 E-01 L———...... 2.8400E-02 3.7000E-02 1.56 2.4900E-02 2.5900E-02 1.8323E-03 2.3871E-03 1.0065E-01 125 125 &lt;N 125 (N PEN Q65 1 1_ PEN Q65 PEN Q65 _ PEN Q65 PEN Q65 ITO breath + 丨 30 ° C preheating + 1.5K on PEN into 92-8 indium breath (1.5KW + 130C preheating) + 1.5K on PEN Λ 92-8 indium breath 92-8 on PEN Indium breath + 92-8 on PEN Indium breath + Ti02 on PEN 8 (I03-MOCON ID: l619-0002) 9(104-MOCON 1D: 1619-0001) ΙΟ(ΡΕΝ-Α ) 1 I(PEN-B) j I2(PEN2-A) -49- 1334194 1 1 draw c r- r- &lt; ί T ^ -!l 2 1 ^ cm B £ i 二_ C —' ON &lt ; ON ·&quot;- d ? II r, ii m Λ ^ C cd C2i CSi Ra= 0.9 nm RMS=1.1 nm Rmax = 9.5 nm See Figure 21A Figure 1.38 2.2000E-01 4.4000E-02 Below detection below detection Below detection 8.9032E-02 1.1494E-02 2.83 87E-03 ! Below detection below detection is below detection 125 125 i_ 125 200 200 200 PEN Q65 LEXAN LEXAN 1 PEN Q65 Batch number PEN Q65 Lot number #1 PEN Q65 Lot number #1 Indium breath + Ti02 on PEN + LEXAN on LEXAN 92-8 iiES+LEXAN 92-8 Indium breath (6.15 person + 5 seconds + 130 °C heat) + I.5K on PEN 92-8 Indium breath (1.5KW + 5 seconds + 130 °C heat) + 1.5 K on PEN into 92-8 indium breath (750 KW + 5 sec + 130 ° C heat) + 1.5 on PEN Λ 92-8 I3 (PEN2-B) M (LEXAN-A) I5 (LEXAN-B) 1 6 (6.1 5 A) 17 (1.5KW) 1 8 (750W)

-50- 1334194

EB c ^ Μ c &lt; 21 II 00 — II 〆 — ιι impi _ s Ξ · Ξ Ξ & 寸 寸 寸 寸 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Rmax = 9.4 nm See Fig. 1 8 A Ra = 1 · 1 nm RMS = 1.4 nm Rmax = 9.4 nm See Fig. 1 8A E = 5 _ C to 卜 U ^ i ιι ^ ^ II κ — II . 5 mouth ^ Off p^. ai c 7.9200E-001 6.1900Ε-01 I 8.7300E-01 6.3700E-01 7.7200Ε-01 5.1097E-02 3.9935E-02 5.6323E-002 4.1097E-02 4.9806Ε-02 200 200 200 200 200 PEN Q65 Lot #l PEN Q65 Lot #1 PEN Q65 Lot #1 PEN Q65 Lot #1 PEN Q65 Lot #1 Self-evaporating 0.037 indium breath + H0 °C preheat + 1.5K on PEN 92-8 Evaporation of 0.037 indium breath + 130 ° C preheating + 1.5K on PEN Λ 92-8 Self-evaporation 0.H3 indium breath + 130 ° C preheating + 1.5K on PEN Λ 92-8 Self-evaporation 0. Π 3 Indium breath + I30 ° C preheating + 1.5K on PEN 92-8 without indium breath + 130 ° C preheating + 1.5KA on PEN 92-8 I9 (.037-A) 20 (.037-13 21(.1 13-A) 22(.1 13-B) 23(MON-A) -51 - 1334194

ε c ;· _ S inch CQ ——II 00 — 丨丨x — II § reduction 〇d 〇d_ Pi ^ E 1 ^ nc ^ cr\ 〇q ——II 00 — 丨丨x — II 銶 2銶pd Snake p £ 1 f囫= inch CQ —-II 00 —11 X — 1 丨 2 2 minus ζ — ί ρί m Ra = 1.1 nm RMS = 1.4 nm Rmax = 9.4 nm See Figure 18B Ra = 1. lnm RMS = 1.4 nm Rmax = 9.4 nm See Figure 8B Figure 1.2200E-02 1.7800Ε-02 3.0300Ε-02 1.8500E-02 3.4200E-02 7.8710E-04 1.1484Ε-03 1_ 1.98548Ε-03 1.1935E-03 2.2065 E-03 200 200 200 200 200 PEN Q65 Lot #1 PEN Q65 Lot #1 PEN Q65 Lot #1 PEN Q65 Lot #1 PEN Q65 Lot #1 Indium breath @280c+130°C heat + PEN on j .5K 92-8 Indium breath @280c+130°c heat + 1.5KA on PEN 92-8 Indium breath® 280c+130°C heat + 1.5K on PEN 92-8 Indium gas 280 @280c+130°C heat 1.5KA 92-8 on PEN Indium breath @280c+130°c heat + 1.5K on PEN 92-8 24 (12-17-03-01-A) 25 (12-17-03-0I- B) ! 26 (I2-17-03-03-A) 27 (12-17-03-03-B) 28 (I2-I7-03-02-A) -52 - 1334194 ρ 1 ^ Β C ^ OS PQ 2τ 1 Ξ II ^ 1 iRR β β β beer; Ra = 1.1 nm RMS = 1.4 nm Rmax = 9.4 nm See Fig. 9A and 18D Fig. ε = ε c inch · layer c σ·\ , ―一· π &lt; —II ^ ^ Μ II § 2 Forging Q ^ 5 轼Ξ Ra= 2.0nm RMS=2.6 nm Rmax = 1 8.0 nm See section 19B and 21B Figure 4.2900Ε-02 Below detection below 1.4000E-02 2.7677Ε-03 Below detection below 9.0323E-04 200 200 200 200 PEN Q65 Lot #1 . PEN Q65 Lot #1 _1 PEN Q65 Lot #2 PEN Q65 Lot #2 Indium gas 悤 @280c+13 (1.5K on TC heat + PEN 92-8 Indium gas 悤 750W 5 seconds + 130 °C preheat + PEN On the 1.5K people 92-8 marriage atmosphere (750W 5 seconds + 丨 30 ΤΤ ^ Ο + ΡΕΝ on the 1.5K Λ 92-8 indium breath (750W 5 seconds + 130 °C ^ 〇 + PEN 1.5K people 92 -8 29 (12-17-032-02- B) 30(165-A) 31(165-13) 32(I67-A) -53- (50)1334194

Ra = 2.0 nm RMS = 2.6 nm Rmax = 1 8.0 nm See Figures 19B and 21B (N Ο * O 〇ώ ώ ώ ο OO &lt; Ν mo oi m m Ο ώ m 〇ώ C^lo 1 tu OS m inch 〇〇Ό & cs (Ν r &lt; CN ΙΟ (N Ό (Ν (y ^ in VO (N ex V〇CN c/ ^ ^ 2 z = ω per Qh Cu Ο 丄 ^ o , mo 2 24, a Read a thought' - read -: π ό Sij vo -N ir! 彡丄丨彡月顿〇«7 臣沄z层Ρ ω wt IS w S 15 + &quot; Magnetic + · One' · _9 2 戚蟊& m ρ &lt; mp &lt; mp &lt; /-s CO /·-N &lt; /-N CQ 卜o Bu O Bu N-✓ mm V-✓ r〇'---· ΓΟ

-54 - (51)1334194

^ Ε □ □ 0.129 0.084 0.194 0.130 π Ο 211.49 230.51 104.03 104.29 19814 22520 I 8123 8996 I-IV [Vickers] 1836 2087 753 834 mn-ai2o3 5mN MN-AI2〇3 5mN 10822-1 5mN 808-0YI0822-I 2.5 mN

-55 -

Claims (1)

1334194 Picking up, applying for patent coverage No. 9 3 1 1 4493 Patent application Chinese patent application scope is replaced by the amendment of the Republic of China on August 30, 1999. 1. A dielectric layer comprising: a thermally compressed amorphous dielectric layer, The dielectric layer is deposited on a substrate by a pulsed DC, substrate biased physical gas deposition with a soft metal atmosphere, wherein the thermally compressed amorphous dielectric layer is a barrier layer. 2. The dielectric layer of claim 1 of the patent application wherein the deposition is carried out with a broad area of the subject matter. 3. The dielectric layer of claim 1 wherein the barrier layer is also an optical layer. 4. The dielectric layer of claim 3, wherein the barrier layer comprises a layer of T i Ο 2 . 5. The dielectric layer of claim 3, wherein the barrier layer comprises a bauxite/sand layer. 6. The dielectric layer of claim 1 wherein the soft metal breath treatment is an indium-tin breath treatment. 7. The dielectric layer of claim 1, wherein the barrier layer is also an electrical layer. 8. The dielectric layer of claim 7, wherein the barrier layer comprises a capacitive layer. 9. The dielectric layer of claim 8 wherein the capacitive layer 1334194 is a Ti02 layer. 10. The dielectric layer of claim 8 wherein the capacitive layer is a bauxite/alumina layer. 11. The dielectric layer of claim 7, wherein the barrier layer comprises an electrical layer. 12. The dielectric layer of claim 11, wherein the resistive layer is an indium-tin metal or oxide. 13. The dielectric layer of claim 1, wherein the barrier layer comprises a friction layer. 14. The dielectric layer of claim 13 wherein the friction layer is a T i Ο 2 layer. 15. For the dielectric layer of claim 13, wherein the friction layer is bauxite/alumina. 1 6. The dielectric layer of claim 1, wherein the barrier layer is a biologically immunocompatible layer. 17. The dielectric layer of claim 1, wherein the biologically immunized compatible layer is Ti02. 18. The dielectric layer of claim 1, wherein the dielectric film is Ti〇2. The dielectric layer of claim 1, wherein the concentration of the target material for forming the dielectric film is 92% A1 and 8% Si. 20. The dielectric layer of claim 1, wherein the material used to form the dielectric film is formed from magnesium metal. 2 1. The dielectric layer of claim 1, wherein the target material - 2334404 material comprises selected from the group consisting of Mg, Ta, Ti, Α1, γ, Zr, Si, Hf, Ba, S r, N b And the combination of materials into a family. 22. The dielectric layer of claim 21, wherein the target material contains a rare earth metal concentration. 23. The dielectric layer of claim 1 wherein the target material comprises a secondary oxidation consisting of Mg, Ta ' Ti, Al' Y, Zr, Si, Hf, Ba, Sr, Nb, and combinations thereof. Things. 24. The dielectric layer of claim 1 wherein the dielectric film has a permeable defect concentration of less than about 1 per square centimeter. 25. The dielectric layer of claim 1, wherein the water vapor transmission rate is less than about 1 x 10 - 2 gm / m2 / Torr. 26. The dielectric layer of claim 1 wherein the light attenuation is less than dB/cm in a continuous film. 27. The dielectric layer of claim 1, wherein the barrier layer has a thickness of less than about 50,000 nm. 28. The dielectric layer of claim 27, wherein the water vapor transmission rate is less than about 1 χ 10 _ 2 gm / m 2 /day. 29. The dielectric layer of claim 1, wherein the barrier layer has a thickness of less than about 1 micron and a water vapor transmission rate of less than about 1 X 1 〇 _ 2 gm / m 2 /day. 30. The dielectric layer of claim 1, wherein the barrier layer functions as a gate oxide of a thin film transistor. 31. A method of forming a barrier layer comprising: providing a substrate; -3- 1334194 performing a soft metal tempering treatment on the substrate; and using a pulsed DC, bias, broad-scale physical vapor sequence, A highly thermally compressed, amorphous, dielectric # _ is deposited on the substrate. 3 2 The method of claim 31, wherein the dielectric tree _ stomach is formed from a target containing 92% of A1 and 8% of Si. 33. The method of claim 31, wherein the dielectric material is formed from a titanium-containing target. 3. The method of claim 31, wherein the dielectric material is a target material selected from the group consisting of Mg, Ta, Ti, A1, Y, Zr, Si, Hg, Ba, Sr, Nb, and a combination of materials. 3 5 · The method of claim 31, wherein the soft metal breath treatment is an indium/tin breath treatment.