TWI333812B - A layout of print circuit board - Google Patents

Description

1333812 099 〇July 19 Amendment Replacement Page 6 Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a printed circuit board wiring structure, and more particularly to reducing crosstalk between differential signals and improving signals The quality of the printed circuit board wiring architecture. [Prior Art] [0002] In printed circuit board circuit design, differential lines are more and more widely used in high-speed circuit design. The most critical signals in the circuit are generally transmitted by differential lines, and the differential apostrophes are compared with ordinary single-ended signals. Its advantages are reflected in the following three aspects: [0003] a) strong anti-interference ability, external common-mode signal can be completely canceled on the differential line with good coupling performance; [0004] b) can effectively suppress electromagnetic interference, two polar In contrast, the externally radiated electromagnetic fields cancel each other out, and the closer the coupling, the less electromagnetic energy is released to the outside world. [0005] C) Timing positioning is accurate. Since the switching change of the differential signal is located at the intersection of the two signals, unlike the ordinary single-ended signal, which depends on the two threshold voltages, the process is less affected by temperature, which can reduce the timing error and is more suitable. Circuits for Low-Amplitude Signals [0006] The wiring of differential wire pairs requires equal lengths of differential pairs during routing. This is to ensure that the coupling impedance between the differential lines is constant along the entire differential pair. However, when the differential pair is connected to the integrated wafer 1C, refer to the first figure. Now take the differential wire pair to access the ESD integrated chip IP4220CZ6 (Philips) as an example. The wiring structure includes a 0993259271-0 094130350 Form No. A0101 Page 3 / Total 11 pages 1333812 On July 19, 099, the integrated wafer mounting area 10' of the strip rectangle is replaced by the replacement, and the four via holes '2', 3', 4' are mounted on the integrated chip of the strip rectangle. In the region 10'; six pads IC01'~IC06' are located on both sides of the long side of the integrated wafer mounting region for soldering the pins corresponding to the integrated wafer. Wherein, in the first differential wire pair 100', the first differential line 10 first passes through the pad IC06', and then passes through the via hole 接入 from the component layer to the solder layer, the second The differential line 102' passes through the pad IC01' and passes through the via 2' from the component layer to the solder layer; in the second differential pair 200', the third differential line 202' passes through the pad IC04' then passes through the via 3' from the component layer to the solder layer, the fourth differential line 201' passes through the pad IC03', and the solder layer is accessed from the component layer through the via 4'. It can be seen that, according to the above wiring structure, the trace of the pad IC01' to the via 2' will cause a large difference in the trace length between the first differential line 101' and the second differential line 102'. The trace of the pad IC03' to the via 3' will cause a large difference between the trace length of the third differential line 202' and the fourth differential line 20', and the difference in the length of the trace will result in a differential pair of wires. The common mode interference signal between the differential signals is enhanced, which seriously affects the transmission quality of the signal. Therefore, it is necessary to improve the existing wiring architecture to eliminate the above disadvantages. SUMMARY OF THE INVENTION [0008] In view of the above technical content, it is necessary to provide a printed circuit board wiring structure that can reduce crosstalk between differential signals and improve signal transmission quality when a differential wire pair is connected to an integrated chip. [0009]

A printed circuit board wiring architecture comprising an integrated wafer mounting area 094130350 Form No. A0101 Page 4 of 11 0993259271-0 1333812 Correction of replacement pages for multiple pads, complex vias and complex differential pairs, The pads are respectively located on two sides of the integrated chip mounting area, and the pins of the integrated chip are correspondingly soldered to the pads, and the vias are used for connection between the layers of the printed circuit board, wherein the same The hole is disposed at a pad adjacent to one side of the integrated wafer mounting region; the differential wire of the differential wire pair passes through the corresponding pad and then passes through the corresponding via. [0010] The present invention enables the differential wire pairs to be connected to the integrated chip when the differential wires are equal in length to each differential line in the trace, thereby reducing crosstalk between differential signals.

Improve the quality of signal transmission. [Embodiment] Referring to the second figure, a preferred embodiment of the printed circuit board wiring frame of the present invention, the present invention uses a differential wire pair to access the electrostatic protection integrated chip IP 4 2 2 0 C Z 6

For example, the printed circuit board wiring architecture of (Philips), the differential signal enters the solder layer from the component layer through the differential wire pair. In this embodiment, the differential signal is accessed from above the integrated wafer. The printed circuit board wiring structure includes a strip. Rectangular integrated wafer mounting area 10, six pads IC01~IC06, four vias 1, 2, 3, 4 and two differential wire pairs 100 and 200. The pads IC01~IC06 are respectively located on two sides of the long side of the integrated chip mounting region 10, wherein the pads IC01~IC03 are located on one side of the integrated chip mounting region 10, and the pads IC04~IC06 are located at the other side One side; the signal pins of the integrated chip corresponding to the integrated chip mounting area 10 are respectively soldered to the pads IC01, IC03, IC04, IC06, and the power pin and the ground pin respectively correspond to the pad IC02 And IC05. The vias 1, 2, 3, 4 are used for connections between the layers of the printed circuit board, wherein the vias 1, 2, 3, 4 are placed adjacent to the pads 094130350 Form No. A0101 Page 5 / Total 11 pages 0993259271-0 1333812 On July 19, 2008, the nuclear replacement page IC01~IC03. In the differential wire pair 100, the first differential line 101 passes through the pad ICO6 and then passes through the via 1 to access the solder layer from the component layer of the printed circuit board. The second differential line 102 passes through the pad IC01. And then passing through the via 2 to access the solder layer from the component layer of the printed circuit board; in the differential pair 200, the third differential line 202 passes through the pad IC04 and then passes through the via 3 from the printed circuit The component layer of the board is connected to the solder layer, and the fourth differential line 201 passes through the pad IC03 first, and then passes through the via 4 to access the solder layer from the component layer of the printed circuit board.

[0012] If in this embodiment, the differential signal is accessed from under the integrated wafer, the differential wire still needs to be connected to the wafer, and then passes through the via to reach the solder layer, and the via can be located adjacent to the transistor. Pad IC 〇4 ~ IC 06. [0013] The printed circuit board wiring structure can eliminate the difference in the length of the first differential line 101' and the second differential line 102' in the prior art; and the third differential line 202' and the The difference between the lengths of the four differential lines 201', and because of the opposite polarity of the signals in the differential wires, the differential wire pairs of the same length can completely cancel the common mode interference of the differential pair 100, 200. Signals to reduce crosstalk between differential pairs and improve signal transmission quality. [0014] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0015] The first figure is a wiring diagram of a conventional technique; 094130350 Form No. A0101 Page 6 of 11 0993259271-0 1333812 July 19, 1999, according to the replacement page [0016] The drawing is a wiring diagram of a preferred embodiment of the printed circuit board wiring structure of the present invention. [Main component symbol description] [0017] [Practical] [0018] Via: 1, 2, 3', 4' [0019] Integrated wafer mounting area: 10' [0020] Pad: IC01', IC02 ' ' IC03' , IC04 ' ' IC05 ' , IC06 '

[0021] First differential wire pair: 100' [0022] Second differential wire pair: 200' [0023] First differential line: 101' [0024] Second differential line: 102' [0025] Fourth difference line: 201'

Third differential line: 202' [0027] [Invention] [0028] Via: 1, 2, 3, 4 [0029] Integrated Wafer Mounting Area: 10 [0030] Pad: IC01, IC02, IC03 , IC04, IC05, IC06 [0031] Differential wire pairs: 100, 200 [0032] First differential line: 101 094130350 Form number A0101 Page 7 / Total 11 pages 0993259271-0 1333812 July 19, 2017 Page [0033] Second Differential Line: 102 [0034] Third Differential Line: 2 0 2 [0035] Fourth Difference Line: 201

094130350 Form No. A0101 Page 8 of 11 0993259271-0

Claims (1)

1333812 - Rev. 7, July 19, 2017. Replacement page 7. Patent application scope: 1. A printed circuit board wiring architecture comprising an integrated chip mounting area, a plurality of pads, a plurality of vias, and a plurality of differential wire pairs, the pads Located on opposite sides of the integrated chip mounting area, the pins of the integrated chip may be soldered to the pads, and the vias are used for the connection between the layers of the printed circuit board, and the improvement is: A via is disposed adjacent the pad on one side of the integrated wafer mounting region; the differential wires of the differential pair pass through the corresponding pad and through the corresponding via. 2. The printed circuit board wiring structure of claim 1, wherein the pair of differential wires pass through the vias from a component layer of the printed circuit board to the solder layer. 3. The printed circuit board wiring structure of claim 1, wherein the integrated wafer is an electrostatic protection integrated wafer. 094130350 Form No. Α0101 Page 9 of 11 0993259271-0