九、發明說明： 【發明所屬之技術領域】 本發明係指一種用於一互補金氧半導體影像感測器之控制電 路，尤指一種藉由耦接至每一列驅動電路之一第一負載單元及一 第一負載單元，控制列驅動電路所輸出之驅動訊號延遲率的控制 電路。 【先前技術】 互補式金氧半導體〈Complementary Metal-oxide Semiconductor ’ CMOS〉影像感測器為常見的固態影像感測元件， 且隨著半導體技術的進步’ CMOS影像感測器已有日漸取代載子IX. Description of the Invention: [Technical Field] The present invention relates to a control circuit for a complementary MOS image sensor, and more particularly to a first load unit coupled to one of each column of driving circuits. And a first load unit, the control circuit for controlling the delay rate of the driving signal output by the column driving circuit. [Prior Art] Complementary Metal-oxide Semiconductor's CMOS image sensor is a common solid-state image sensing device, and with the advancement of semiconductor technology, CMOS image sensors have gradually replaced carriers.
耦合裝置〈Charge-CoupledDevice，CCD〉的趨勢。由於CMOS 影像感測器是以傳統的半導體製程製作，因此具有製作成本較低 以及元件尺寸較小的優點’此外，CMOS影像感測器還具有高量 子效率〈QuantumEfficiency〉以及低雜訊〈Read-〇utNoise〉等優 勢，因此已廣泛地應用在個人電腦相機〈PCCamera〉以及數位相 機〈DigitalCamera〉等電子產品上。一般而言，CMOS影像感測 器由複數個像素單元〈Unit Pixel〉所組成，並形成一像素陣列〈pixei Array〉。其中，每一像素單元包含有一感光二極體〈ph〇t〇di〇de〉 以及三或四個金氧半導體〈Metal Oxide Semiconductor，MOS〉電 晶體。感光二極體用來感應入射光線，並累積入射光線所產生的 光電荷〈Photo-generated Charge〉’而金氧半導體電晶體則是用來 根據一驅動訊號控制對應的像素單元。 1333325 請參考第1圖’第1圖為先前技術(：]^〇5影像感測器之一像素 單70 10之電路示意圖。像素單元1〇係為一四電晶體架構〈F〇ur Transistor Pixel〉之像素單元，其包含有一感光二極體pD、一轉 移電晶體〈Transfer Transistor > TX、-重置電晶體〈Reset Transist〇r〉 RX、一驅動電晶體〈Drive Transistor〉DX以及一選擇電晶體〈select Transistor〉SX。感光二極體pD用來感測光照的強度，並累積入 射光線所產生的光H轉移電晶體τχ时根據，移控制訊 號，將累積於感光二極體PD之光電荷轉移至一浮動節點FD。重 置電晶體RX用來根據一重置訊號，重置浮動節點FD之電壓至一 特定電壓’例如：電源電歷VDD。驅動電晶體DX則用來根據浮 動節點FD之電壓，其可以是重置電晶體狀導通時之電源電壓 VDD或者是由感光二極體PD轉移至浮動節點FD之光電荷所產 生之電壓，輸出對應之電流訊號至選擇電晶體sx。最後，選擇電 晶體sx根據一選擇驅動訊號，由輸出端ριχ一〇υτ輸出對應於感 光二極體PD所感測光照強度之電壓訊號ν〇υτ。其中，轉移控制 訊號、重置訊號及選擇驅動訊號可由一列解碼器〈R〇w Dec〇der〉 所產生，於此不贅述。 在先前技術中，當轉移控制訊號關閉轉移電晶體τχ時，若轉 移控制訊號的下降時間〈FallingTime〉太短，感光二極體^所 累積之光電荷將無法完全被轉移至浮動節點FD，因此會導致區分 雜訊〈PartitionNoise〉的產生’進而影響CM〇s$像感測器之性 能。同樣地，在重置訊號導通或關閉重置電晶體狀時，亦有類 6 1333325 似的問題產生。此外，當同一列之像素單元過多時，對於列驅動 電路來說，每一像素單元所對應之負載大小並不一致，因此每一 像素單元之轉移控制訊號或重置訊號的延遲率會有差異產生。同 樣地，此像素間的差異亦會影響CM〇S感測器之表現。因此，為 了改善CMOS感測器之表現’必須降低轉移控制訊號或重置訊號 之延遲率，也就是增加轉移控制訊號或重置訊號的下降時間及上 升時間。 針對上述問題，美國專利公開號第2〇〇6〇1865〇4A1號「CM〇s IMAGE SENSOR FOR REDUCING PARTITION NOISE」揭露-種 消除區分雜訊的CMOS影像感測器，其係藉由串接複數個N型金 軋半導體〈N-channel Metal-Oxide-Semiconductor，NMOS〉電晶體 於每-列驅動電路〈RGwDrivef〉中，罐每-列軸電路之電阻 值乂增加轉移控制訊號之下降時間，進而降低區分雜訊的產生。The trend of the coupling device <Charge-CoupledDevice, CCD>. Since the CMOS image sensor is fabricated by a conventional semiconductor process, it has the advantages of lower fabrication cost and smaller component size. In addition, the CMOS image sensor has high quantum efficiency (Quantum Efficiency) and low noise <Read- 〇utNoise> has been widely used in electronic products such as PC camera <PCCamera> and digital camera <Digital Camera>. In general, a CMOS image sensor is composed of a plurality of pixel units <Unit Pixel> and forms a pixel array <pixei Array>. Each of the pixel units includes a photodiode <ph〇t〇di〇de> and three or four metal oxide semiconductor (MOS) transistors. The photodiode is used to sense the incident light and accumulate the photo-generated charge generated by the incident light. The MOS transistor is used to control the corresponding pixel unit according to a driving signal. 1333325 Please refer to Fig. 1 'Fig. 1 is a circuit diagram of a pixel single unit 70 10 of the prior art (:]^5 image sensor. The pixel unit 1 is a four-crystal crystal structure <F〇ur Transistor Pixel a pixel unit comprising a photodiode pD, a transfer transistor <Transfer Transistor > TX, a reset transistor <Reset Transist〇r> RX, a drive transistor <Drive Transistor> DX, and a selection The transistor <select Transistor>SX. The photodiode pD is used to sense the intensity of the light, and accumulates the light generated by the incident light. When the light is transferred to the transistor τ, the control signal is accumulated in the photodiode PD. The photocharge is transferred to a floating node FD. The reset transistor RX is used to reset the voltage of the floating node FD to a specific voltage according to a reset signal, for example: the power supply VDD. The driving transistor DX is used to float according to the The voltage of the node FD, which may be the power supply voltage VDD when resetting the transistor-like conduction or the voltage generated by the photo-charge of the photodiode PD to the floating node FD, and outputting the corresponding current signal to the selection Selecting the transistor sx. Finally, selecting the transistor sx according to a selection driving signal, the output terminal ριχ-〇υτ outputs a voltage signal ν〇υτ corresponding to the light intensity sensed by the photodiode PD. The signal and the selection of the driving signal can be generated by a column of decoders <R〇w Dec〇der>, which will not be described here. In the prior art, when the transfer control signal turns off the transfer transistor τχ, if the falling time of the control signal is shifted < FallingTime> is too short, and the photocharge accumulated by the photodiode can not be completely transferred to the floating node FD, thus causing the noise generation <PartitionNoise> to be affected, which in turn affects the performance of the CM〇s$ image sensor. Similarly, when the reset signal is turned on or off to reset the transistor shape, there is also a problem like the type 6 1333325. In addition, when there are too many pixel units in the same column, for the column driver circuit, each pixel unit The corresponding load sizes are not consistent, so the delay rate of the transfer control signal or the reset signal of each pixel unit may be different. Similarly, the image The difference between the two will also affect the performance of the CM〇S sensor. Therefore, in order to improve the performance of the CMOS sensor, it is necessary to reduce the delay rate of the transfer control signal or reset signal, that is, to increase the transfer control signal or reset the signal. Fall time and rise time. In response to the above problem, US Patent Publication No. 2〇〇6〇1865〇4A1 "CM〇s IMAGE SENSOR FOR REDUCING PARTITION NOISE" discloses a CMOS image sensor for eliminating noise. By connecting a plurality of N-channel Metal-Oxide-Semiconductor (NMOS) transistors in a per-column drive circuit <RGwDrivef>, the resistance value of the tank per-column circuit is increased by the transfer control. The fall of the signal, which in turn reduces the noise generation.
…而由於此方式必須絲—列驅動電路巾’魏增加複數個N ，金氧半導體電晶體，因此列解碼器的面積將大幅地增加，導致 晶片生產成本的提高。以兩百萬像素之CMOS縣感測器為例， 般來說其係由每列〗嶋個像素單元及每行12⑻個像素單元之 象=車騎喊〈即16⑽χι雇〉，因此若藉由上述之方式，最少 -、、曰2ί)_Ν型金氧半導體電晶體，列解瑪器的面積將大幅 地增加。 除此之外’美國專利公開號第2〇〇7〇0011〇1Α1號 (ς ) 7 1333325 . 「PR0GRAMMABLE ^E/FALL TIME CIRCUIT」中另揭露藉一 -種可程式化上升及下料間之桃，其係由控她接於列驅動電 路之N型金氧半導體電晶體及p型金氧半導體電晶體之偏壓，調 整轉移控舰贼重置峨之延辭〈SlewRate〉，崎低區分雜 訊的產生。然而，此方法同樣地會增加電路的面積，糾一兩百 萬像素之CMOS影像感測器為例，其必須同時增加12〇〇個？型 金氧半導體電晶體及_個N型金氧半導體電 •積越來越小，列一積的增加將大幅增加線路伟局= 【發明内容】 因此，本發明之主要目的即在於提供一種用於一互補金氧半導 體影像感測器之控制電路。 本發明揭露-種用於-互補金氧半導_像感測器之控制電 路，其包含有-第-負載單元；一第二負載單元；以及一驅動單 元’搞接於該第-純單元及該第二負載單元之間包含有複數 個列驅動電路，分別對應於該互補金氧半導體影像感測器之一列 像素單元，用來根據該第一負載單元及該第二負載單元之阻抗 值，控制該複數個列驅動電路所輸出驅動訊號之延遲率。 【實施方式】 5月參考第2圖’第2圖為本發明用於-互補金氧半導體 〈C〇mplementary Metal 0xide Semic〇nduct〇r ’ cm〇s〉影像感測 1333325 器之控制電路20之功能方塊圖。控制電路2〇包含有一第一負載 单元21、一第一負載单元22以及一驅動單元23。驅動單元23係 由列驅動電路DRIVE(O)〜DRIVE⑻所組成’耦接於第一負載單元 21及第二負載單元22之間，用來根據第一負載單元21及第二負 載單元22之阻抗值’控制列驅動電路DRIVE(O)〜DRIVE(n)所輸 出驅動訊號之延遲率〈SlewRate〉。其中，列驅動電路drive(〇) 〜DRTVE(n)係以並聯方式連接於第一負載單元21及第二負載單 元22之間’亦即每一列驅動電路之電源端與地端皆分別轉接於第 負載單元21及第二負載單元22。此外，列驅動電路 〜DRIVE(n)可分別對應於CMOS影像感測器之一列像素單元，用 來控制對應之列像素單元之運作。較佳地，本發明控制電路2〇係 設置於CMOS影像感測器之一列解碼器〈RowDec〇der〉中，而 列驅動電路DRIVE(O)〜DRIVE(n)則用來控制對應之列像素單元 之轉移電晶體〈TransferTransistor〉之開關，或是對應之列像素單 元之重置電晶體〈ResetTransistor〉之開關。 因此，藉由耦接至每一列驅動電路之第一負載單元21及第二 負載單元22，本發明控制電路20可根據第一負載單元21及第二 負載單元22之阻抗值，控制列驅動電路DRIVE(〇)〜DRIVE(n)所 輸出驅動訊號之延遲率，以降低區分雜訊的產生。相較於先前技 術，本發明藉由耦接於驅動單元23外部之第一負载單元21及第 一負載單元22 ,可取代串接於每一列驅動電路之N型金氧半導體 〈N-channel Metal-Oxide-Semiconductor，NMOS〉電晶體或取代輕 9 1333325 接於每一列驅動電路用來偏壓之N型金氧半導體電晶體及p型金 氧半導體電晶體，以大幅地降低列解碼器〈Rowdec〇de〇之晶片 面積，進而節省生產成本。值得注意的是’第一負載單元21及第 二負載單元22可視實際需求而分別存在，舉例來說，若只欲控制 列驅動電路DRIVE⑼〜DRIVE(n)所輸出驅動訊號之下降時間& 〈Falling Time〉時，控制電路20只需存在第二負載單元22 ;相 反地’若只欲控制列驅動電路DRIVE⑼〜DRIVE(n)所輪出驅動訊 號之上升時間〈RisingTime〉’則控制電路2〇只需存在第一負載 單元21。 ' 此外，本發明亦可針對不同的列像素單元控制方式，對列驅動 電路DRIVE(O)〜DRIVE⑻進行分組，以避免驅動訊號之延遲率因 同時驅動兩條以上之列像素單元而改變。請參考第3圖，第3圖 為本發明控制電路2G之-實施例示意圖。糊來說，若—次欲驅 動兩相鄰之聽素單元，則可將對應於偶數條之列驅動電路 DRIVE(O)、DRIVE(2)...DRIVE(n)包含於一第一控制電路 24 ;而 將對應於奇數條之列驅動電路DRIVE⑴、DRIVE⑶〜DRiVE(n^ 包含於-第二控制電路25。其中，第一控制電路及第二控制電路 之架構及操作方式皆與第！圖中之控制電路2〇類似，於此不贅 述。如此一來，本發明不但可節省列解碼器之晶片面積，還可具 有彈性之驅動方式。 請參考第4〜7圓’第4〜7圖為本發雜制電路2()之其他實 1333325 •施例不意圖。第4圖說明了每一列驅動電路DRIVE(0)〜DRIVE(n) 可以一互補金氧半導體形式之反相器〈CMOS Inverter〉實現，並 以並聯方式輕接於第一負載單元21及第二負載單元22之間。第5 〜7圖則說明了第—負載單元21及第二負載單元22可以電阻或電 晶體等不同的方式實現。在第5圖中，第-負載單元21及第二負 載單兀22分別為一電阻，而其阻值可根據實際驅動訊號延遲率之 需求來加以調整。在第6圖中，第一負載單元21及第二負載單元 • 22則分觀—互補金氧半導體電晶體實現，並可藉由電晶體之寬 長比〈W/LRatio〉來調整其負載值。最後，在第7圖中，第一負 載單元21及第二負載單元22同樣地分別以一互補金氧半導體電 晶體實現，不_地方在於電晶體之偏壓可藉由程式化的方式控 制，以達到控制驅動訊號延遲率之目的。 綜上所述’藉由耦接至每一列驅動電路之第一負載單元及第二 鲁貞鮮元，本發㈣於⑽⑽影佩·之控概路可根據第一 負載单7G及第二負載單元之負載值，控制列驅動電路所輸出驅動 訊號之延遲率’以降低區分雜訊的產生。相較於先前技術，本發 明可大幅地降低列解碼器之晶片面積，進而節省生產成本。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 1333325 【圖式簡單說明】 第1圖為先前技術CMOS影像感測器之一像素單元之電路示咅 圖。 第2圖為本發明躲—互補金氧半導體影佩測器之控制電路 之功能方塊圖。 第3圖為本發明控制電路之一實施例示意圖。 第4〜7圖為本發明控制電路之其他實施例示意圖。 【主要元件符號說明】 10 像素單元 PD 感光二極體 TX 轉移電晶體 RX 重置電晶體 DX 驅動電晶體 SX 選擇電晶體 FD 浮動節點 VDD 電源電壓 GND 地端 PIX-OUT 輸出端 VOUT 電壓訊號 20 控制電路 21 第一負載單元 22 第二負載單元 1333325 23 驅動單元 DRIVE(0；)〜DRIVE(n) 列驅動電路 24 第一控制電路 25 第二控制電路 R1、R2、R3、R4 負載單元 (5 ) 13...and because this method requires a plurality of N-type MOS transistors to be added to the wire-column drive circuit, the area of the column decoder will be greatly increased, resulting in an increase in wafer production cost. Take a two-megapixel CMOS sensor as an example. Generally speaking, it is a pixel unit of each column and 12 (8) pixel units per row. In the above manner, the minimum -, 曰2 )) Ν type MOS transistor, the area of the column damper will be greatly increased. In addition, 'US Patent Publication No. 2〇〇7〇0011〇1Α1(ς) 7 1333325. "PR0GRAMMABLE ^E/FALL TIME CIRCUIT" is also disclosed as a programmatic rise and fall between Peach, which is controlled by the bias voltage of the N-type MOS transistor and the p-type MOS transistor that controls her connection to the column driver circuit, adjusts the transfer control ship thief to reset the 延 延 〈 〈 〈 〈 〈 〈 〈 〈 〈 The generation of noise. However, this method will also increase the area of the circuit. For example, a CMOS image sensor with one or two megapixels must be added at the same time. Type MOS semiconductor transistors and _ N-type MOS semiconductors have become smaller and smaller, and the increase in the number of products will greatly increase the line of the road = [Summary] Therefore, the main object of the present invention is to provide a use A control circuit for a complementary MOS image sensor. The invention discloses a control circuit for a complementary gold-oxygen semiconductor image sensor, comprising: a -th-load unit; a second load unit; and a driving unit 'engaged to the first-pure unit And the second load unit includes a plurality of column driving circuits respectively corresponding to the column of pixels of the complementary MOS image sensor for determining impedance values of the first load unit and the second load unit And controlling a delay rate of the driving signal output by the plurality of column driving circuits. [Embodiment] Referring to FIG. 2 in FIG. 2, FIG. 2 is a control circuit for the image sensing 1333325 of the present invention for a complementary metal oxide semiconductor (C〇mplementary Metal 0xide Semic〇nduct〇r ' cm〇s>) Functional block diagram. The control circuit 2A includes a first load unit 21, a first load unit 22, and a drive unit 23. The driving unit 23 is composed of a column driving circuit DRIVE(0) to DRIVE(8) coupled between the first load unit 21 and the second load unit 22 for the impedance of the first load unit 21 and the second load unit 22. The value 'control column drive circuit DRIVE (0) ~ DRIVE (n) output drive signal delay rate <SlewRate>. Wherein, the column drive circuits drive(〇)~DRTVE(n) are connected in parallel between the first load unit 21 and the second load unit 22, that is, the power supply end and the ground end of each column drive circuit are respectively transferred. The first load unit 21 and the second load unit 22 are provided. In addition, the column driver circuits ~ DRIVE(n) can respectively correspond to a column of pixel units of the CMOS image sensor for controlling the operation of the corresponding column of pixel units. Preferably, the control circuit 2 of the present invention is disposed in a column decoder (RowDec) of the CMOS image sensor, and the column driver circuits DRIVE(0) to DRIVE(n) are used to control the corresponding column of pixels. The switch of the cell transfer transistor <TransferTransistor>, or the switch of the reset transistor (ResetTransistor) of the corresponding column of pixel units. Therefore, the control circuit 20 of the present invention can control the column driving circuit according to the impedance values of the first load unit 21 and the second load unit 22 by being coupled to the first load unit 21 and the second load unit 22 of each column of driving circuits. DRIVE (〇) ~ DRIVE (n) The delay rate of the drive signal output to reduce the noise generation. Compared with the prior art, the present invention can replace the N-type metal oxide semiconductor N-channel metal connected in series with each column driving circuit by the first load unit 21 and the first load unit 22 coupled to the outside of the driving unit 23. -Oxide-Semiconductor, NMOS>Chip or Substitute Light 9 1333325 is connected to each column of driver circuit for biasing N-type MOS transistors and p-type MOS transistors to greatly reduce column decoder <Rowdec晶片de〇's wafer area, which in turn saves production costs. It should be noted that the first load unit 21 and the second load unit 22 may exist separately according to actual needs. For example, if only the falling time of the drive signal outputted by the column drive circuits DRIVE(9) to DRIVE(n) is controlled, < In the case of Falling Time>, the control circuit 20 only needs to have the second load unit 22; conversely, if only the rise time (RisingTime> of the drive signal of the column drive circuit DRIVE(9) to DRIVE(n) is controlled, the control circuit 2〇 Only the first load unit 21 needs to be present. In addition, the present invention can also group the column drive circuits DRIVE(0) to DRIVE(8) for different column pixel unit control modes to prevent the delay rate of the drive signal from being changed by simultaneously driving more than two columns of pixel units. Please refer to FIG. 3, which is a schematic diagram of an embodiment of the control circuit 2G of the present invention. For the paste, if the two neighboring listener units are to be driven, the drive circuit DRIVE(O), DRIVE(2)... DRIVE(n) corresponding to the even number of columns can be included in a first control. The circuit 24 is connected to the odd-numbered column drive circuit DRIVE(1), DRIVE(3)~DRiVE(n^ is included in the second control circuit 25. The structure and operation mode of the first control circuit and the second control circuit are the same! The control circuit 2 in the figure is similar, and will not be described here. In this way, the present invention not only saves the wafer area of the column decoder, but also has an elastic driving mode. Please refer to the 4th to 7th rounds '4th to 7th The figure is the other real 1333325 of the hybrid circuit 2 (). The embodiment is not intended. Figure 4 illustrates that each column of the driver circuit DRIVE(0) ~ DRIVE(n) can be a complementary MOS semiconductor inverter < CMOS Inverter> is implemented and connected in a parallel manner between the first load unit 21 and the second load unit 22. The fifth to seventh diagrams illustrate that the first load unit 21 and the second load unit 22 can be resistors or transistors. In a different way, in the fifth figure, the first load unit 21 and the second negative The load cells 22 are respectively a resistor, and the resistance value can be adjusted according to the requirement of the actual driving signal delay rate. In the sixth figure, the first load unit 21 and the second load unit 22 are divided into complementary gold. The oxygen semiconductor transistor is realized, and the load value can be adjusted by the width to length ratio (W/LRatio) of the transistor. Finally, in FIG. 7, the first load unit 21 and the second load unit 22 are similarly respectively A complementary MOS transistor is implemented, in which the bias of the transistor can be controlled by a programmatic manner to achieve the purpose of controlling the delay of the driving signal. In summary, by coupling to each column drive The first load unit of the circuit and the second reckless element, the fourth (4) of the (10) (10) shadow control control circuit can control the output driving signal of the column driving circuit according to the load value of the first load sheet 7G and the second load unit The delay rate is used to reduce the generation of noise. Compared with the prior art, the present invention can greatly reduce the wafer area of the column decoder, thereby saving production costs. The above is only a preferred embodiment of the present invention. according to The average variation and modification of the scope of the invention should be within the scope of the present invention. 1333325 [Simplified Schematic] FIG. 1 is a circuit diagram of a pixel unit of a prior art CMOS image sensor. 2 is a functional block diagram of a control circuit of a hiding-complementing MOS film shadow detector of the present invention. Fig. 3 is a schematic view showing an embodiment of a control circuit of the present invention. Figs. 4 to 7 are other implementations of the control circuit of the present invention. Example Schematic [Description of main component symbols] 10 pixel unit PD photodiode TX transfer transistor RX reset transistor DX drive transistor SX select transistor FD floating node VDD supply voltage GND ground PIX-OUT output VOUT voltage Signal 20 control circuit 21 first load unit 22 second load unit 1333325 23 drive unit DRIVE (0;) ~ DRIVE (n) column drive circuit 24 first control circuit 25 second control circuit R1, R2, R3, R4 load unit (5) 13