TWI332151B - System and method for clock signal synchronization - Google Patents

Description

1332151 IX. Description of the Invention: [Technical Field] The present invention generally relates to a system for signal calibration and a method of 'involving a clock for an oscillator in data communication" The system and method of locking to the data flow. [Prior Art] A conventional data communication circuit requires a precise timing component to provide a reference frequency to an external device connected to the host via a signal transmission bus. The precise timing component in the communication circuit typically includes a crystal oscillator. The clock signal of the crystal shock component is adjusted based on the internal timer to match the input signal flow from the host with the clock signal. Usually, the phase lock loop (phase lock 1〇叩, abbreviated as PLL) or delay lock loop (DLL) in the timer has data training, phase shift, phase selection, etc. The function of adjusting and locking the clock signal. Crystal oscillators are expensive. Internally based timers typically have a long trim sequence to adjust the PLL or DLL. This long trim sequence may not be suitable for modern applications such as Universal Serial Bus (USB) applications. Another method for locking the clock signal to the input data flow includes generating a clock signal by a current controlled oscillator (ICO) or a voltage controlled oscillator (vc〇) to analyze the rate of the input data flow in at least two cycles. To generate two or more control signals, and then adjust the frequency of the clock signal in response to the control signal. The frequency of the clock signal is adjusted to operate in an analogous manner, and generally includes at least two steps, a coarse adjustment step, and a subsequent fine adjustment step. 1332151 or (10) 疋 要 要 要 要 曰 曰 曰 曰 曰 曰 曰 曰 曰 特定 特定 特定 特定 特定 特定 特定 特定 特定 特定 特定 特定This analogy is multi-step, slow and complex. Analogy adjusts the nature of the circuit "Relieve this, and do not over-private and temperature 呈 ,, rang. Complex processing and circuit performance and reliability may be required. The program changes its mind and raises the tone. So there is a cost-effective system and a clock signal.

The process of calibrating with the data signal will be beneficial to the right brake J ^ bamboo raft. People expect the system to be simple and the Shixi area to be effective. It is also expected that calibration x will be caught early and reliable. It is also advantageous for the system and the process to be unaffected by changes in the wafer manufacturing process and the selected conditions. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a system (101) for clock signal calibration is provided, which includes a data analyzer. (1(4) and a calibration clock signal generator (1G5) connected to the Rc shaker (1G3). The data analyzer (104) generates a digital control signal indicating that the reference of the RC oscillator (103) is at the input The number of cycles in the eight-bit cycle of the token package. The calibration signal clock generator (1〇5) uses the digital control signal to lock the clock signal to a packet of the same bit rate as the weight & package. The various embodiments of the present invention are described with the The present invention is not intended to be exhaustive or to limit the scope of the invention.

1 is a block diagram showing a precision timing component or clock signal calibration system 101 in accordance with the present invention. For example, FIG. 1 illustrates system 101 being part of a universal serial bus (USB) device 100 and for generating a packet calibration that is received from a host (not shown in FIG. j) via USB bus 110. Clock Signal "In Figure 1, component 102 represents a portion of USB device 100 that is different from clock signal calibration system 101. Element 1 〇 2, which is also referred to as a data processing element 'may include USB control circuitry and other components of USB device 100. A USB control circuit, sometimes referred to as a USB drive, is used to control the transfer of data between the host and an external or slave device (e.g., USB device 100) via the USB bus. The USB device 1 can be any type of device that communicates with the host via the USB bus 110. Examples of USB devices 1 include, but are not limited to, a USB mouse for moving a cursor on the main computer screen and a command to the host computer, such as a USB hard disk drive, USB CD_R〇M, USB rewritable CD, USB rewritable DVD, USB flash memory, etc.), USB multimedia devices (eg USB CD player, USB DVD player, USB MP3 player, etc.). The USB bus 11 is connected between the USB device 1 and the host or the host device. As is known in the art, the USB busbar 11() includes four wires or wires, two of which are data transmission (D+) line Π2 and complementary data transmission (D-) line 114, and the other two are power lines J 丨5 and the ground line 丨丨 7. In accordance with an embodiment of the present invention, the clock signal calibration system 101 is built on an integrated circuit wafer that implements some or all of the functions of the USB device 100. The clock signal calibration system 101 includes an oscillating device 103 serving as a reference signal generator, a data sequence analyzer 1-4, and a calibrated clock signal generator 〇5. In accordance with the present invention, oscillator 1 提供 3 provides a reference frequency signal to data sequence analyzer 104 and calibration clock signal generator 〇5. The data sequencer ι〇4 identifies and analyzes the input data flow and generates digital control signals. In response to the digital control signal from the data sequencer 1〇4 and the reference frequency signal from the oscillator 1〇3, the clock signal generator 1〇5 generates a clock signal that is calibrated or locked to the input data flow. In a specific embodiment, the ## generator 1〇5 includes counters 1〇6 and 1〇8 as shown in FIG. The operation of the material signal sequence analyzer 104 and the calibration clock signal generator 1 in accordance with a preferred embodiment of the present invention will now be described with reference to Figs. In accordance with a preferred embodiment of the present invention, oscillator 103 is a resistive capacitance (RC) oscillator that generates a fixed frequency signal. The RC oscillator 1〇3 is simple and inexpensive compared to other types of oscillating circuits such as crystal oscillators, ICO, VC0, and the like. Moreover, the RC oscillator 1〇3 footprint (f00i: print) is small, that is, its 矽 area is very efficient. It should be mentioned that although the oscillator 1〇3 is described herein as a helium oscillator, it is not intended to limit the scope of the invention. Other types of clock sources, such as clocks on other wafers, crystal oscillators, ceramic oscillators, ICO, VC0, etc., can also be used as the oscillator 103 in system 101 in accordance with the present invention. Fig. 2 is a timing chart showing the scepter pack 2 in the USB communication protocol according to the present invention. For example, Figure 2 shows the top ten bits of the token package during low speed data transfer in accordance with the USB 1.1 version protocol. For the full-speed data transfer in the USB丨 version protocol, the voltage levels on the D+ and D- lines are opposite to the voltage levels shown in Figure 2. The first eight digits of the scepter pack 200 form a calibration (sync) field, and the last two 1332151

The bit is the packet identification word (pid) field portion of the token pack 200. The top ten digits of the 2nd scepter pack on the D+ line are 1〇1 〇101110. Figure 2 also shows a wave 210 corresponding to such a value. The edge in wave 210 represents a change in the bit value in the token pack 200. The rising edges 201, 203, 205, and 207 of the wave 210 correspond to a voltage level that changes from low to high on the D+ line or a bit value that changes from 〇 to 1. Similarly, the falling edges 202, 204, 206, and 208 of the wave 210 correspond to the D+ line from high.

To a low-varying voltage level or a bit value that varies from 丨 to 〇. Before the host transmits the token pack 200, the USB device 1 is in an idle state, wherein the voltage on the d + line is a low level corresponding to the value of the clamp bit, and the voltage on the line on the £ _ corresponds to 1 bit The value is high. A rising edge 201 in wave 210 indicates the arrival of the token pack 200. 3 is a flow chart showing a process 300 for digitally analyzing a packet of information in accordance with the present invention. For example, the material analysis process 300 can be performed in the data sequence analyzer 1 to generate a digital control signal for the clock signal generator 1 〇 5 as shown in FIG.

Referring also to Figures 1, 2 and 3', when the first power is applied, component 1 〇 2 transmits the weight & number to data sequence analyzer 1 〇 4 and calibration clock signal generator 105. In the USB protocol, the re-signal is indicated by setting and the voltage level on the D-line is low for a predetermined period of, for example, 10 milliseconds (ms). In response to the re-signal, the data sequence analyzer 1〇4 is initialized in step 301. Once the initialization is completed, the data sequencer 1〇4 sets the digital control signal to a predetermined initial value. According to a specific embodiment, the digital control signal has eight bits and the predetermined initial value is 1 28 . In the following step 302, the data sequence analyzer 1〇4 detects the information packet 1332151

In a specific embodiment, the EOP is signaled by a USB bundle (ΕΟΡ). The voltage levels on the D+ and D- lines on a bus bar according to the present invention are indicated to remain low during a predetermined period, e.g., equal to or greater than one bit period. After the E〇p signal, the USB bus goes into an idle state and waits for the host to send a packet.

When in the spatial state, the data sequence analyzer 1〇4 detects the incoming packet. In accordance with a preferred embodiment of the present invention, the beginning of the input packet is indicated by a change in the voltage levels on the D+ and D_ lines of the U S B bus. For example, a rising edge 2〇1 (shown in Figure 2) in wave 200 represents a change in voltage level from low to high in the D+ line and indicates an incoming packet. After detecting the input packet, the data sequence analyzer 1〇4 attempts to identify the type of the information packet in step 3〇4. Specifically, in step 3〇4, the data sequence analyzer 104 verifies whether the round-in package is a token package. In a specific embodiment of the present invention, the data sequence analyzer 104 responds to the information packet to satisfy three preset conditions to identify the input packet as a token package. The first condition is that in the wave 210 representing the voltage level on the 〇+ line, the first falling edge (2 〇 2 in Fig. 2) and the second upper

The duration or interval between the rising edges (edge 203 in Figure 2) is approximately equal to the duration or interval between edge 203 and the second falling edge (along 204). The second condition is that in wave 210, the duration between the first falling edge (along 2〇2) and the second falling edge (/.204) is substantially equal to between edge 204 and the third falling edge (along 206) The duration. The third condition is that the duration between the first falling edge (edge 202) and the third falling edge (along 2〇6) in wave 21〇 is approximately equal to the edge 206 and the fourth falling edge (along 2〇8) The duration between the two. According to the invention, any timing signal can be used to measure the duration. For example, in a preferred embodiment of the invention, the reference 1332151 frequency signal from the RC oscillator 1〇3 is used for time measurement. In general, the higher the frequency of the reference frequency signal, the more accurate the time measurement will be. According to a preferred embodiment, if the difference between the two durations is less than about ten percent (10%), they are considered to be approximately equal. According to another preferred embodiment, if the difference between the two durations is less than about five percent (5%), they are considered to be approximately equal. Other standards are within the spirit of the invention' and are also within the scope of the invention. In accordance with an embodiment of the invention, a reference frequency signal from Rc oscillator 1〇3 is used for measuring time and verify conditions in process 300. It should be understood that the process 300 is not limited to identifying the input packets using the conditions described with reference to steps 3〇4 described herein. Other schemes can also be used to identify incoming packets. Preferably, the packet identification does not depend on the first edge of the wave corresponding to the packet, such as edge 2 in Figure 2 (Π, because the first edge of the packet is often unstable. Responding to the input packet is not right The wand, then process 3〇〇 returns to step 3〇3 and waits for subsequent input packets. If the input packet is identified as a token package, process 300 proceeds to step 305. In step 305, process (10) gives digital control Signal Assignment Value. In accordance with an embodiment of the present invention, the value just assigned by the process is equal to the first falling edge (edge 202) and the fourth falling edge (along m) of the RC oscillator 103 in the wave 21 of the token pack. The number of periods of the reference frequency signal generated during the interval duration. This time interval is equal to eight times the bit period of the token pack. In particular, the time interval occupies the scepter pack 2 _ second digit tenth The duration of the start of the bit is attached to the calibration process 4 described below with reference to Figure 4, which is used to generate a known signal that is calibrated with the input packet. How the digital control signal is used to generate the number 1332151, the data analysis process 300 can be given in step 305 The bit control signals are assigned different values. The assigned value preferably represents the relationship between the data rate of the incoming packet and the reference frequency signal. Additionally, the assigned value preferably does not depend on the time of the first edge (e.g., edge 201 in wave 210) This is because it may be unstable.

After assigning a value to the digital control signal, process 3 returns to step 3〇2 and waits for a new incoming packet. In response to the new input packet, the process 3 repeats steps 3〇3, 304, and 305 to identify the information packet, and in response to the information packet as the token package, assigns a value to the digital control signal. In accordance with a preferred embodiment of the present specification, the digital control signal is used to calibrate or lock the clock signal to the data flow to the data flow.

4 is a flow chart showing a process 400 for digitally calibrating a clock signal with a communication packet in accordance with the present invention. For example, process 400 can be performed in calibration clock signal generator 105 to generate a clock signal that is locked to the flow of data transmitted from the host via USB bus 110 of FIG. According to an embodiment of the invention, the process 400 digitally generates the information packet calibration in the data flow by calculating the number of cycles of the reference frequency signal of the RC oscillator 103 using the digital control signal of the data sequence analyzer 1〇4. Clock signal. In a preferred embodiment of the invention, process 400 is initiated after power up. Once initiated, in step 402, counters 1 〇 6 and 108 in calibration clock signal generator 105 (shown in Figure 1) are initialized and set to zero in response to a reassertion signal from component 1 〇 2. After the initialization, the process 4 0 0 ' is repeated from the step 4 0 3 of detecting the change of the bit value as shown in Fig. 4 and described below. In a preferred embodiment, the cycle time of process 400 is equal to the period of the RC oscillator 103 1332151 test frequency signal. The higher the frequency of the reference frequency signal, the more cycles the parent unit time will be and the more accurate the calibration. At the beginning of the cycle of the oscillator 103, the process 400 checks the 仏旎 level of the component ι〇2 lnn a ^ in step 403 to see if the USB device 疋aL receives or waits for The host's information package. If the _device (10) η or (4) host's information packet' then the process gamma detects whether the voltage on the ΙΗ or D- line in the bus bar 110 is flat or not. While still 6 devices are coming from

The change in the voltage level in the voltage level when the host receives the data flow indicates the change in the value of the input data. The detected bit can be a bit in the token pack or a bit in any other packet after the token pack in the data flow. In response to detecting a change in voltage level, the process proceeds to the beginning of the period of the period in which the calibration clock signal 2 is generated, e.g., the rising edge. Thus, the start of the month 'J cycle of the clock signal is aligned with the start of the bit period of the input packet or locked to the beginning of the bit period of the input packet. After the start of the calibration clock signal is generated in step 4〇4, process 400 returns to step 4〇2, and counters 1〇6 and 1〇8 are reset to zero. Process 4 is ready for the next cycle. A constant voltage level indicates that the bit value does not change. This may correspond to two situations. The first case is that the time lapse from the previous cycle of process 400 is not equal to the duration of one or more bits of the rounded packet, since successive bits in the input packet may have the same Bit value. In the second case, the USB device 1 is sending the data flow to the host. In response to this, the counts of the counters 1〇6 and 1〇8 are incremented by one in step 406. In the subsequent step 407, the process 4 checks whether the count Cm of the counter 106 satisfies the equation (1):

Cl06 = Dx^/8 1332151 In 弋(1), the value of the digital control signal generated in the process goo described above with reference to Fig. 3, N is a positive integer. The count Cl06 that does not satisfy equation (1) indicates that the time lapse from the calibration clock signal (4) is not equal to the multiple of the bit period of the input or output data flow. In response to this, the process gamma checks in step 4 whether the count Ci 〇 8 of the counter 1 〇 8 in the calibration clock generator 105 satisfies the equation (2): ° 〇 Ci 〇 8 = £) / 16 ^ satisfies the equation (2) The count cm indicates that the time lapse from the start of the calibration clock signal is not equal to half of the bit period of the process flow. In response thereto, process 400 returns to step 4〇3 for the next cycle. If the number is full; ^ (7), it means from the calibration clock gate

The time lapse of : is equal to - half of the bit period of the packet. Back; 2: Over (4) 0 In step 412, the # before the cycle of the calibration clock signal is generated as a falling edge. Thus, the intermediate edge of the period in the clock signal and the midpoint of the =bit period are calibrated or locked to the packet order bit period to the cow:4. After the middle edge of the calibration clock signal is calibrated, the process 4〇. Return 2 Miscellaneous 3 for the next cycle. In another embodiment, the process is complete; an optional step is included: when the step (4) is the current week of the calibration clock signal: after the middle edge of the clock and after returning to the step to perform the lower state, the counter 108 is counted. Reset to zero. Quasi-==Γ7, satisfying the count of equation (1)—the time transition of the start of the start of the ;; is equal to the number of bit periods (four) of the input or output data =. In response to this process example, the end of the current cycle of the chime signal is generated at the step of the process, for example, another rising edge. School - Week The end of the predecessor is also used as the starting point for the calibration clock signal. In addition, the counter C1.8 is incremented in step 414 and then in step 415, the process deletes the check count~

Tian Cong: When the equation (1) is satisfied, the count c"6 does not satisfy the equation (3): the time transition from the beginning of the calibration clock signal is not equal to eight times the bit period of the data Ά. In response to this situation, process 400 returns to step 403 to advance to the next cycle. If a" satisfies equation (3), then the time lapse from the start of the calibration clock signal is equal to the bit of the input data flow, and the response of the month is repeated, the process returns to the start step 402 and the counter 1G6 and 〇8 reset to zero. After step 402, the clock signal calibration process 400 proceeds to step 4G3 and repeats for the lower _cycle of the octet period. According to the present invention, the calibration clock signal is not limited to the above. For example, step 409 is not limited to whether the verification count satisfies equation (2). In a further embodiment, process 4 可以 can verify in step 4 (10) whether the count Cm of the number counter 1 〇 6 is satisfied, etc. Equation (4): (4) (5) ^*106 = Μ /16 or Equation (5): C106 = Dx(2M + \)/\β In equations (4) and (5), μ denotes In these alternative embodiments, the calibration clock signal generator 1〇5 requires only one counter, such as counter 106. 1332151 " Additionally, the process 300 described above with respect to Figure 3 is not limited to digitally controlling the L number The value D s is again set to be equal to eight of the input token packs by the shock banker 1〇3 Bit - The number of cycles of the reference frequency signal generated during the duration of the period. The value D of the digital control signal can be set equal to the duration of any number of bit periods equal to the input token package by the oscillator 1〇3 The number of cycles of the generated reference frequency apostrophe. Generally, the large value D is preferably used for high precision calibration. As described above with reference to Figures 2 and 3, the beginning of time preferably does not correspond to the beginning of the first bit' This is because it may be unstable. Limiting the end of the duration • It is also preferred that it does not exceed the tenth position of the token pack. This is because the top ten digits of the token pack are predetermined and easily identifiable in the USB protocol. Therefore, the duration of the eight-bit period is due to its large 1) value, easy to identify, and easy to perform a binary operation on the number of multiples of four, eight, sixteen, etc., thereby being preferred. The calibration clock signal generated in the process 4 is locked to the data flow on the 70 pieces 102 of the USB device 100. The calibration clock signal enables the component 102 to properly perform the following functions, such as reading data from the host, Recording and processing = batting, sending data and commands to the host, etc. As noted above, the USB device 1GG can be a USB mouse, a USB DVD player, a (four) playback device, a USB rewritable optical memory, a USB hard disk. Driver, USB flash memory printer, etc. Calibrating the clock signal enables the component to perform a variety of functions. Moonlight The clock signal calibration system or process according to the present invention can be used with any digital data transmission device. Device U)G is only used An example of the purpose of the explanation. It should be understood now that the clock signal and the data signal are provided for 1332151

A system or process that is quasi- or locked to a data signal. The calibration system in accordance with the present invention can include such an oscillator and a simple digital circuit that is simple and cost effective. This system has the characteristics of small wafer size, reliable operation and cost-effectiveness. The calibration process in accordance with the present invention involves digital operations that can be implemented in only one signal exchange. Therefore, it is simple, fast, reliable, and not susceptible to changes in the manufacturing process and operating conditions.

Although specific embodiments of the invention have been described above, they are not intended to limit the scope of the invention. The invention includes modifications and variations to the described embodiments that are obvious to those skilled in the art. For example, although the book (b) incorporates a protocol for low-speed signal transmission to describe the quasi-process, the present invention also includes clock signal calibration systems and processes in various data transmission protocols at various speeds. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a clock signal calibration system according to the present invention; FIG. 2 is a timing chart showing a token packet in a universal serial bus communication protocol according to the present invention. 3 is a flow chart showing a process for digitally analyzing a packet according to the present invention; and FIG. 4 is a diagram showing digitally calibrating a clock signal and a packet according to the present invention. Flow chart of the process. 1332151 _ [Main component symbol description] 101 ... clock signal calibration system 100 ..... tandem bus (USB) device 110 ... USB bus bar 102 . ........USB device component 112.........data transfer (D+) line 114 ..........complementary data transfer (D-) line 115 ... .......Power line 117.......... Ground line 103 .......... Oscillator 104 .......... Data Sequence Analyzer 105..........calibration clock signal generator 106, 108... counter % 18

Claims (1)

X. Patent Application Range: 1. A method for calibrating a clock signal and a data flow, comprising the steps of: generating a reference signal; generating a value equal to the reference signal being predetermined in a packet including the data flow The number of cycles of the duration of the number of bit periods; by calculating the number of the reference signal in the data flow by the value and the predetermined number, which is simpler than the phase of each phase The change in the bit value in the data flow uses a count to generate a clock signal that is calibrated with the data flow. The method of claim 1, wherein the step lock for generating the reference signal comprises a damping MU to the domain earthquake signal. If the application recites the method described in item 1, the step of generating the new value includes grading the eight-digit 7-cycle periodicity in the information package of the reference information. The number of lions is mentioned. The method of claim 3, wherein the step of generating a numerical value comprises: generating a material from the information packet of the reference money surface data to a tenth bit from the beginning to the tenth The stated value of the number of cycles for the duration of the start. The method of generating the numerical value according to the first aspect of the invention, wherein the step of generating the value comprises: according to the information package of the general manager A step of. The method of claim 5, wherein the step of said packet being a token package comprises the step of analyzing a first ten bits of said packet. The method of claim 6, wherein the step of analyzing the first ten bits of the information packet comprises analyzing a voltage level on a universal serial bus data transmission line. The method of claim 5, wherein the step of identifying the information 权 as a token package further comprises the step of comparing a plurality of intervals indicating a change in a bit value in the information packet. The method of claim 8, wherein the step of comparing the wave_multiple intervals comprises the following steps: whether the interval between the second class of the third type and the second edge of the second type is substantially Equal to the interval between the edges of the second type; whether the first edge of the first type of the type and the second edge of the first type are larger than the first a section between the second edge of the face and the third edge of the first type; and - the first edge of the type of the face and the second edge of the first type The interval between the three edges of the building (four) and the fourth edge of the first type. 10. Along the second aspect of the first type, as described in claim 9, wherein the two are substantially equal to each other, and the (four) interval includes two intervals that differ by less than ten percent (four). 11. The method of claim 1, wherein the step of generating a clock signal setting is zero; detecting a change in a bit value in the data flow; 12. responsive to the change in the bit value: generating a first edge for the period of the clock signal; and setting the count to zero; responding to the bit value unchanged: incrementing the count by one; Said count being equal to said value, said said count being set to zero; responsive to said count being equal to an odd multiple of said value divided by said predetermined number of times 'generating a second edge for said period of said clock signal And generating a third edge in response to the counting being equal to a multiple of the value divided by the predetermined number ' for the period of the clock signal; and returning to detecting the bit value in the data flow The steps to change. The method of claim 11, wherein: the step of generating a first edge for the period of the clock signal comprises generating a rising edge of the escaped clock signal; wherein the period of the clock signal is The step of generating a second edge includes generating a falling edge of the clock signal; and 22 1332151, the step of generating a third edge for the period of the clock signal comprising generating a rising edge of the clock signal. 13. The method of claim n, wherein the step of detecting a change in a bit value in the data flow comprises detecting a package in accordance with a general arrangement bus schedule agreement Subsequent: The change in the bit value of the button towel. 14. The method of claim i, wherein the step of generating a clock signal comprises the steps of: setting a first count and a second count to zero; detecting a change in a bit value in the data flow; And detecting the change in the bit value, generating a first edge of the clock signal and setting the first count and the second count to be zero; in response to the undetected reward value change: the first count Adding one, and incrementing the second count by one; generating a second edge of the clock signal in response to the second count being equal to the value divided by twice the predetermined number; 23 in response to the The first count is equal to a multiple of the value divided by the number of pre-turns, a third edge of the clock signal is generated, and the second count is set to zero; and the first count is equal to the value And setting the first count and the second count to zero; and returning to the step of the change of the verified financial value. The method of claim 14, wherein: the step of generating the first edge of the clock signal comprises generating a start edge for a period of the clock signal; the generating the clock signal The second edge of the m includes generating an intermediate edge for the period of the age number; and D generating the end of the cycle generation of the object number. The method of claim 15, wherein the end of the generation period for the said read letter further comprises a subsequent beginning of the clock signal. 17. I33215L The method of the method of claim 1 includes the steps of: resetting the count to zero; detecting a change in the bit value in the data flow; responding to the change in the bit value: Generating a starting edge of the clock signal; and returning to the step of counting the weight zero; and responding to the bit value unchanged: incrementing the count by one; 'wherein the generated clock signal is responsive to the count being equal to a multiple of the value divided by the predetermined number: generating an end edge of the clock signal; responsive to the count being equal to the value 'returning to the a step of resetting the count to zero; and returning to said step of detecting a change in a bit value in said data flow; 25 1332151 responsive to said count being equal to a multiple of said value divided by twice said number of said preview : generating an intermediate edge of the clock signal; and returning to the step of detecting a change in a bit value in the data flow; and returning to the step of detecting a change in a bit value in the data flow. 18. The method of claim 17, wherein the detecting the change in the bit value in the data flow comprises detecting a subsequent information packet in the data flow subsequent to the token package The bit value of the bit. 19. The method of claim 17, wherein: the step of generating a start edge of the clock signal comprises generating a rising edge of the clock signal; the generating an intermediate edge of the clock signal The step of generating a falling edge of the clock signal; and the step of generating an end edge of the clock signal includes generating a rising edge of the clock signal. The method of claim 17, wherein the step of generating an end edge of the clock signal comprises generating the , ', for the current lion of the clock. The starting edge of the generation of the W and the job of the job. 21. A kind of clock signal calibration system (1〇1), including: data registration bus (11〇); reference signal generation H(10)), secret reliance rate signal; number ^ beech knife hacking (104) Connected to the data log bus (11〇) and to the reference signal generator (10), the digital data analyzer (10) for generating a value equal to the reference signal generator (10) The number of cycles of the predetermined period of the bit period of the information packet in the data flow on the data registration bus (1)〇), and the number of cycles in the digital calibration period; Connected to the material registration bus (10), to the reference signal generator (10), and to the digital data analyzer (10), the digital calibration clock signal generator The value of the digital data analyzer (10), and the change of the value of the bit 27 1332151 in the data flow in response to each period of the fixed frequency signal is generated by using the counting method and the data flow school Quasi-clock signal. 22. The clock signal calibration system (ι〇ι) according to claim 21, wherein the digital calibration clock signal generator (1〇5) comprises a counter (1〇6) for equalizing A rate count of the frequency of the fixed frequency signal of the reference signal generator (1〇3). 23. The clock signal calibration system (101) according to claim 22, wherein the digital calibration clock signal generator (1〇5) is used to generate a calibration method by performing a calibration method comprising the following steps Clock signal: setting the counter (106) to zero; detecting a change in a bit value in the data flow; Responding to a change in the bit value: generating a first edge for a period of the clock signal; and setting the count to zero; responding to the bit value unchanged: incrementing the count by one; responding to the count Equal to the value, setting the count to zero; 28 1332151 generating a second edge for the period of the clock signal in response to the count being equal to an odd multiple of the value divided by twice the predetermined number And - in response to the counting being equal to a multiple of the value divided by the predetermined number, generating a third edge for the period of the clock signal; and - returning to the detecting the bit in the data flow The step of changing the value. 2^ The clock signal calibration system (1〇1) according to claim 22, wherein the digital calibration clock signal generator (105) is used to generate a calibration method by performing a calibration method including the following steps Clock signal: 'Set the count of the counter (106) to zero; detect a change in the bit value in the data flow; Φ in response to the change in the bit value: generate a starting edge of the clock signal; Returning to the step of setting the count of the counter (106) to zero; and responding to the bit value unchanged: • adding the count to one; 29 1332151 responsive to the count being equal to a multiple of the value Dividing by the predetermined number: - generating an end edge of the clock signal; responsive to the counting being equal to the value 'returning to the step of setting the count of the counter (106) to zero; and returning to the Determining a step of detecting a change in a bit value in the data flow; generating a clock signal in response to the count being equal to a multiple of the value divided by twice the predetermined amount The intermediate edge; and \ return to the step scale that detects a change in the bit value in the data flow. The clock signal calibration system (101) of claim 22, wherein the digital calibration clock signal generator (105) further comprises a second counter (108), and for performing by performing the following a calibration method of the step to generate the clock signal: setting a first count of the counter (106) to zero. setting a second count of the second counter (108) to zero. 30 detecting the data flow Change in the position value; call the change in the job title of the prosecutor, the first edge of the remnant, and set the first count and the second count to zero; in response to the change in the bit value is not detected. Adding the first count by one and incrementing the second count by one; • generating a second of the clock signal in response to the second count being equal to the value divided by twice the predetermined number In response to the first count being equal to a multiple of the value divided by the pre-turn number 1, generating a third edge of the clock signal, and setting the second count to zero; and responding to the A count equals the value, • Fresh opposite the first count of the second counter 7 scales; and returns to step detects the bit values of the data flow of the variation. 26. A device (1) for receiving data from a host and transmitting data to a host, comprising: a data processing component (1) connected to the host; and a digital calibration unit (101), including : 31 vibrator (103); digital data analyzer (104) connected to the data processing component (102) and connected to the oscillator (1〇3), the digital data analysis Is (104) For generating a control signal, the value of the control signal being equal to the duration of the predetermined frequency period of the fixed frequency signal of the oscillator (103) in the information packet in the data processing flow on the data processing component (102) a number of cycles in time; and a digital calibration clock signal generator (105) coupled to the data processing component (102), to the oscillator (1〇3), and to the digital data analyzer (1〇4) 'The digital calibration clock signal generator (105) is responsive to the control signal and is responsive to a change in a bit value in the data flow for each cycle of the fixed frequency signal Counting method Data flow calibration of the clock signal. The device (100) of claim 26, wherein the data processing component (102) is for moving a cursor on a screen of a host computer connected thereto via a universal serial busbar and The host computer issues a command. The device (100) of claim 27, wherein the digital calibration clock horn generator (1〇5) includes a counter (1〇6), and is configured to generate a weight method by 32 a clock signal, the calibration method comprising the steps of: setting a count of the counter (106) to zero; detecting a change in a bit value of the data flow command; responding to a change in the bit value: # is the clock signal a period of generating a first edge; and setting the count to zero; responding to the bit value unchanged: increasing the count by one; setting the count in response to the count being equal to a value of the control signal Zero in response to the count being equal to an odd multiple of the value of the control signal divided by twice the number of times, generating a second edge for the period of the clock signal; and responsive to the A count equal to a multiple of the value of the control signal divided by the predetermined number ' is the clock 钤. The period of 15 生成 generates a third edge; and 33 1332151 returns to the step of detecting a change in the bit value in the data flow. 29. The device (100) of claim 27, wherein the digitally calibrated clock signal generator (105) comprises a counter (106) and for generating the clock signal by performing a calibration method, The calibration method comprises the steps of: • setting a count of the counter (106) to zero; detecting a change in a bit value in the data flow; responding to a change in the bit value: - generating a start of the clock signal a starting edge; and returning to the setting (1 (6) the step of counting zero; and in response to the bit value unchanged · adding the count -; relying on the responsibility Dividing the multiple by the predetermined number: generating the time-span_end edge; in response to the count being equal to the value of the control signal, returning to the step of setting the count of the counter (106) to zero And returning to said detecting a change in a bit value in said data flow; responding to said count being equal to a multiple of said value of said control signal divided by said predetermined number of two times The intermediate edge of the clock signal; and the step of returning to the detecting the change of the bit value in the data flow. The device (100) of claim 27, wherein the digital calibration clock The signal generator (105) includes a first counter (106) and a second counter (1〇8), and is configured to generate the clock signal by performing a calibration method, the calibration method comprising the steps of: setting the first The first count of the counter (106) is zero; setting the second count of the second counter (108) to zero; detecting a change in the bit value in the data flow; in response to detecting the change in the bit value: a first edge of the clock signal; setting a first count of the first counter (106); and setting a second count of the second counter (10) to zero; in response to not detecting the change in the bit value: Adding the first count of the first counter (10) to one; incrementing the second count of the second counter (108) by one; in response to the second calculating the bribe Dividing the value by two times the predetermined number: generating a second edge of the clock signal; In response to the doubling - the multiple of the value of the numerator number is divided by the predetermined number: a third edge of the clock signal is generated; and 5 is further set to the second count crying f 105?, λ* The second count of r-C108) is zero; response; the first tip is equal to the value of the control wheel number: 36 1332151 f* · l 设置 setting the first counter (106) The first count is zero; and the second count of the second counter (108) is set to zero; and the step of detecting a change in the bit value in the data flow is returned. 37