1330878 九、發明說明： . 【發明所屬之技術領域】 , 本發明係關於一種雙鑲敌(duai damascene)結構的製作方法，尤 指一種利用一氧化碳與去離水以有效清介層洞内之蝕刻後殘留物 的雙鑲嵌結構製作方法。 【先前技術】 雙鑲嵌製程（dual damascene process)是一種能同時形成 •一金屬導線以及一插塞(plug)之上下堆疊結構的方法以用 來連接半導體晶片中各層間的不同元件與導線，並利用其 周圍的内層介電材料（inter-layer dielectrics)與其他元件相 隔離。其中’以金屬銅作為雙鑲嵌結構内導電材料的銅雙 鑲嵌技術為最常見的雙鑲嵌結構。銅雙鑲嵌技術搭配低介電常數 介電層為目前所知對於高積集度、高速(high_speed)邏輯積體電路 晶片製造以及針對〇· 18微米以下的深次微米(deep sub micr〇)半導 籲體製程最佳的金屬内連線解決方案。由於銅具有低電阻值(比銘低 30/。)以及較佳抗電致遷(electr〇migrati〇n㈣对如㈤的特性，且低介 電常數材料可幫助降低金屬導線之間的RC延遲(RC delay)，因此 銅金屬雙鑲嵌内連線技術在積體電路製程中顯得日益重要。目 雙鑲敗製程基本上有所謂的溝渠優先(trench-first)雙鑲嵌、介 層’同優先(via-first)雙鑲嵌、部份介層洞^partiai_via)雙鑲喪，以及自 仃對準(self-aligned)雙鑲嵌等選擇。其中，介層洞優先(via-first)雙 鑲嵌即是利用數道微影及蝕刻步驟，先定義介層洞，隨後再於介 5 1330878 層洞上方定義出溝渠，構成一體之雙鑲嵌結構。 • 請參考第1圖至第4圖，第1圖至第4圖為習知介翻優 鑲嵌製程的雜示意圖。如第丨圖所示，半導财置⑴包含有— 基底12，而基底12表面由下而上依序設有一導 層18以及-光阻層20。其中，導電層14表面可另設有一餘刻= 止層16。進行-微影製程以圖案化光阻層2〇，使得光阻層如: 有一介層洞圖案22。 ” 接著如第2圖所示，經由介層洞圖案22蝕刻介電層a，直至 蝕刻停止層16的表面，以形成介層洞24。然而，在韻刻製程中， 會於介層洞24側壁或介層洞24底部角落形成殘留物％，其中殘 留物26通常為包含碳、石夕、氮、氟及鈦等原子的高分子㈣或並 他雜質。殘留物26會覆蓋於介層，洞24表面，產生反應室記憶效 應（chamber memory effect)，影響到後續製程的臨界尺寸與元件 | 品質’例如介層洞24内所形成接觸插塞之品質。 請參看第3圖，接著進行一灰化製程以去除光阻層2〇。在習知 技術中，通常利用氧氣（oxygen，〇2)來去除光阻層2〇。此外， 灰化製程也可藉由氧氣結合氮氣（nitr〇gen，N2)，或結合少量四 氟化碳(tetrafluoromethane ’ CFO來進行。雖然此灰化製程能有效去 除光阻層20以及破壞殘留物26的高分子鍵結，然而卻往往在介 電層18上另留下光阻殘留物3〇。然而，此灰化製程也無法有效去 6 1330878 除含氟殘留物26。另一方面，雖然以氧氣結合約4至 • 進行灰化製程之方法有助於去除高分子殘留物26，然而使用含1 •氣體來去除光阻層20之方法也很容易在介層洞24的側壁或底部 角落以及介電層18表面留下含氟殘留物28、32，這些殘留物^、 3〇、32亦會影響到後續製程效果以及接觸插塞的電性表現。因此， 習知技術通常必須使用成本很貴的液體溶劑來清洗半導體裳置’ 1〇 ’待殘留物28、30、32清除後，再製作溝渠結構。 _ 請參考第4圖，接著於介電層18上形成一圖案化之光阻層（圖 未示）’該圖案化之光阻層具有溝渠圖案，然後經由溝渠圖案钱刻 介電層18，而於介電層18上部形成溝渠結構34。最後移除圖案 化之光阻層以及部分钮刻停止層16，以在介層洞24内暴露出導電 層14，完成雙鑲嵌孔洞之製作。 由上述可知，在製作介層洞時很容易於介層洞表面形成殘留 •物’而以四既化碳等含氟氣體去除光阻層時，也容易在介層洞或 介^層表面形賴㈣，上述殘留物都必須使賊本很高的溶劑 來’月洗然而’溶劑或化學材料通常是半導體製程中耗費成本最 ^關鍵之―’因此，如何改料知雙職餘方法崎低製程 成本，仍然為業界S需研究的重要課題。 【發明内容】 本發月之主要目的在於提供一種利用一氧化碳 7 1330878 monoxide ’ CO)以及去離子水water)來除去光卩且 殘留物的雙職結讎作方法，以解決上述g知雙鑲嵌結構製作 方法中必須使用南成本溶劑來清洗介層洞之問題。 根據本發明之申請專利範圍，雙鑲嵌結構的製作方法係先提供 -基底’在基底表面包含有—導電層、一第—蝴停止層、一介、 電層以及光阻層依序設於該基底表面。然後圖案 阻層’以於第_光阻層定義出—介層棚案，再進行—第 製程，經由介層__除部分介電層，直至暴露恤刻停止^， 而於介電層内形成-介層洞結構。接著，進行一第一灰化製程曰以 移=第一光阻層，射灰化製程係藉由提供含有-氧化碳之氣體 而完成。然後於介層洞結構内形成填隙高分子材料（卿仙 接著，圖案化 漢圖“_人$霉木圖案進仃一第二蝕刻製程，經由溝 尔圖案而_介魏’以於介電層之均形成—溝渠結構， 渠結構暴露$介層職構。Μ移 、 中所暴露㈣第-侧停止層。^植相及介層洞結構 根之申料職圍，另财—輯料制結構之方 構半導趙裝置，其表面包含-經由侧而形成之 ^ 設於—介電層中，且介相結構喊有侧後殘留 内通入含有-氧化碳之氣體。導魏置，最後於反應室 8 1330878 • 砂轉明方法制含有-氧化碳喊體來it行灰化製程，因 • 此犯有助於清除介層洞中的殘留物，避免因殘留物而影響後續製 作雙鑲嵌、，Ό構内的導電材料時發生記憶效應饱以），改 變製程的臨界尺相及雙職結制導電性。再者，在灰化製程 之後，本發明方法另可以去離子水代替習知技術中以高成本的液 體溶劑來清洗介層洞，可以大幅降低製程成本，以提高產品利潤。 _ 【實施方式】 清參考第5圖至第13圖’第5圖至第13圖為本發明雙鑲後結 構製作方法之第—實補的製程示意圖，其巾本發明雙鑲嵌結構 的製作方法為-介層缝先方法。首先提供—包含有—基底^之 半導體襄置50，其中半導體裝置5〇可為一半導體晶圓。基底^ 表面包含有-導電層54、一侧停止層％以及一介電層％，其 中導電層54較佳為包含銅或其他金屬材料的導電層，触刻停止層 • %可包含氮化石夕材料。此外，介電層58之上可另設有如氮氧化石夕 等塾層（圖未示）。接著，於介電層冗表面塗佈—層第一光阻層 6〇並進仃一微影製程而圖案化第一光阻層60 ’以於第-光阻居 60上形成介層洞圖案62。 然後如第6圖所示，進行一第一_製程’經由介層洞圖案62 而钱刻介電層58，於介電層58⑽成—介制64。此時，料 祕的側壁表面與底部角落通常會留下餘刻後殘留物的，其通常 9 1330878 為包含m敦及鈦等材料之高分子物質。 • 接著’進行一第—灰化製程以移除第一光阻層60。請參考第7 f苐-灰化製程可藉由製程裝置1〇〇來進行。製程裝置1〇〇包 反應至102 無線電（radio frequency ’ RF)產生器106、 氧化炭供應源108以及一氧氣（〇xygen，〇2)供應源11〇。反 應至1〇2包含有—晶81承座112，用以承載半導體裝置5〇，而無 、線電產生益106連接於晶圓承座112。為了有效清除殘留物66， 本發明方法係於第-灰化製程中提供含有一氧化碳之氣體來清除 第光阻層60。如第8圖所示，第一灰化製程係藉由一氧化碳供 應源108提供2G至_標準糾每分鐘(趣祕eubi_to咖 permmute ’ sccm)的一氧化碳，進行約15至％秒的灰化製程，壓 力約30至1〇〇毫托耳（mTbrr)，總功率約測至麵瓦特。此 外，在第-灰化製程中另可同時提供約2〇〇至_鮮毫升每分 鐘的氧氣。由於在第-灰化製財通人—氧化碳作為反應氣體， • ®此能有效改善含有氟碳化合物(C取含氟之殘留物的的清除 效率’使得第-灰化製程前下較少殘留物66於介層洞科之内， 耸反鹿夫nr · CO + F2 -> C0F2 (gas) 也不會造成氮化矽 再者以氧化碳為反應氣體之第一灰彳卜制名。 蝕刻停止層56的損失。 1330878 清參考第9圖，接著進行一第二灰化製程，於反應室i〇2中通 入約200至2000標準毫升每分鐘的氧氣，壓力約2〇〇至8〇〇毫托 耳，總功率為約5〇〇至2000瓦特，製程時間為約4〇至9〇秒。然 後如第10圖所不，進行一去離子水清洗製程，以完全清除介層洞 64内的殘留物66。如前所述，由於本發明係於第一灰化製程中通 入一氧化％i至反應室1〇2，因此能抑制氟碳殘留物，以及改善氟碳 殘留物的清除效果’所以本發在灰化製程後提供去離子 水’便可有效清除介層洞64以及介電層58表面的殘留物66。在 其他實施例巾，本翻方法可在去離子水清洗製程之前，先進行 :晶背清洗製程。在特定機台中，晶背清洗製程_程會先將半 導體裝置5G或半導體晶醜面，彻硫畔補清洗晶背，之後 再將半導體裝置50 _正面’財離子水清洗铸體裝置5〇的 正面’此步驟同樣能有效清除殘留物66 ’因此能取代上述另外提 供去離子水以移除殘留物66之流程。 請參考第11圖，於基底52上塗佈一填縫高分子層68，並填滿 介層洞64。填縫高分子層68 一般由適應365奈米光源之光阻劑 〇-Linephotoresist)所構成。填縫高分子層68的塗佈類似一般光 阻塗佈製程，其後並加以烘烤硬化。接著進行—回_製程將 ，縫高分子層68回侧至-預定深度。織再於基底50上塗佈 八第一練層7〇，並填滿介層洞64内沒有填縫高分子材料的部 刀。進行—第二微影製程以圖案化第二絲層7G，於第二光阻層 /Q 70内形成-溝渠圖案72。 如第12圖所示，進行一第二蝕刻製程，經由溝渠圖案72蝕刻 )| 9 6至一預定深度，以於介電層58中形成一溝渠74。狹德 移除第…、傻 一九隍層7〇以及介層洞64内的填縫高分子層68，並暴露 ^餘刻停止層56。最後如第13圖所示，去除蝕刻停止層56，並 β藉由化學氣相沉積製程或濺鍍製程而於溝渠74 形成導雷爲a J ^ ^ 电增78，導電層78可為銅或鋁等金屬材料，便完成雙鑲栌 結構76之製作。 人 έ士明參考第14圖至帛19圖H4圖至第19圖為本發明雙鑲嵌 -構製作方法之第二實施例的製程示意圖。首先提供—半導體裝 置150 ’其包含有一基底152，以及一導電層154、一第一侧停 止層156二一下介電層158、一第二银刻停止層16〇、一上介電層 =、一氮氧化雜層164及一氧化石夕塾層166由下而上依序設於 -表面其中’第一餘刻停止層156可為氮化石夕層，第二 停止層⑽可為氮氧切層，而導電層154較佳為金屬層。 然後’於乳化梦塾層脱表面形成圖案化之第一光阻層⑽，其中 Ϊ八^阻層168包含有一介層洞圖案。進行一第一侧製程，經 由"層移除暴露出的上介電層⑹、第二_停止層· Π:電’直至第i刻停止層158表面，以形成介層洞 170。此時，介層洞17G側壁表面會形成殘留物172。 12 氣==_ 一第-灰化製程，提供-氧化魏 ^166*' ^ 啊移除部分殘留物172。而氧化矽墊 =表面f下部分光阻殘留物^接_ 導體健150進行—第二灰化製程。缝進行一 上_2 & (全清除介層洞170内以及氧化轉層166 上的殘留物172和光阻殘留物174，如第17圖所示。 ★請參考第18圖，於介層洞⑺内填人填縫高分子層⑺，其可 糟由-般纽塗佈製程以及烘烤硬化而形成。接著回侧填縫高 分子層Π2 ’於介層洞17〇内形成一凹口。再於基底152表面塗佈 第光阻層174’進行微影製程以圖案化第二光阻層174而形成 溝渠圖案176。然後如第19圖所示，進行第二侧製程，經由溝 渠圖案176移除部分氧化輕層166、氮氧化轉層164以及上介 電層162 ’直至第二侧停止層16〇 ’以形成雙鑲紐洞178。最 後移除第二光阻層174以及填縫高分子層172，再絲暴露出的第 一蝕刻停止層156。之後，可於雙鑲嵌孔洞178中形成金屬導電層 (圖未示），便完成金屬雙鑲嵌結構的製作。 由於本發明清潔介層洞之方法係於灰化製程中通入一氧化碳 做為反應氣體，其能抑制含有氟碳化合物之殘留物，改善殘留物 的清除效率。所以，在灰化製程之後，本發明僅需利用去離水便 可有效清除介層洞内的殘留物，而不需使用習知技術中的高成本 液體溶劑來清洗介層洞，可以大幅降低製程成本。再者，因為一 1330878 氧化碳氣體灰化製程能有效移除介層洞表面的殘留物，所以能於 後續製程中保有較佳之臨界尺寸，例如打開氮化矽蝕刻停止層以 及於介層洞内形成導電材料等製程。此外，本發明清潔介層洞之 方法可以應用於其他包含蝕刻及灰化的製程中，以清除的蝕刻後 殘留物’例如溝紐先雙鑲嵌或部份介相雙鑲嵌技術。 以上所述僅林發明之難實關，驗本發明 所做之均等·與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第4®為習知介層珊先雙 第5圖至第η圖為本發明雙鎮嵌結構1^^程示意圖。 的製程示意圖。 方去之第一實施例 第1)圖至第19圖為本發明雙鑲嵌結構製 的1程示意圖。 χ料之第二實施例 10 14 20 24 34 52 【主要元件符號說明】 半導體裝置 導電層 光阻層 介層洞 溝渠結構 基底 12 基底 18 介電層 22 介層洞圖案 26、28、3〇、32 半導體裝置 導電層 50 殘留物 54 13308781330878 IX. INSTRUCTIONS: [Technical field] The present invention relates to a method for fabricating a duai damascene structure, and more particularly to a method for effectively resolving post-etching residues in a layer of holes using carbon monoxide and deionized water. The method of making a dual damascene structure. [Prior Art] A dual damascene process is a method of simultaneously forming a metal wire and a plug upper and lower stacked structure for connecting different components and wires between layers in a semiconductor wafer, and It is isolated from other components by its surrounding inter-layer dielectrics. Among them, the copper dual damascene technique using metallic copper as a conductive material in a dual damascene structure is the most common dual damascene structure. Copper dual damascene technology with a low-k dielectric layer is known for high-accumulation, high-speed logic IC chip fabrication and deep sub micr〇 for 〇·18 μm or less The best metal interconnect solution for the process. Since copper has a low resistance value (30/min lower than that of Ming) and better resistance to electrical mobility (electr〇migrati〇n(4) pairs, such as (5), and low dielectric constant materials can help reduce the RC delay between metal wires ( RC delay), so the copper metal dual damascene interconnect technology is becoming more and more important in the integrated circuit process. The double-inlay process basically has the so-called trench-first dual-embroidery, and the layer is the same as the priority. -first) Dual inlays, partial vias ^partiai_via) Double insets, and self-aligned dual inlays. Among them, via-first dual-embedded is the use of several lithography and etching steps to define the via hole first, and then define the trench above the layer hole of the 3 1330878 layer to form an integrated dual damascene structure. • Please refer to Figures 1 to 4, and Figures 1 to 4 are schematic diagrams of the conventional inlay process. As shown in the figure, the semiconductor package (1) includes a substrate 12, and the surface of the substrate 12 is provided with a conductive layer 18 and a photoresist layer 20 from bottom to top. Wherein, the surface of the conductive layer 14 may be additionally provided with a residual layer = a stop layer 16. A photolithography process is performed to pattern the photoresist layer 2 such that the photoresist layer has a via pattern 22. Next, as shown in FIG. 2, the dielectric layer a is etched through the via pattern 22 until the surface of the etch stop layer 16 is formed to form the via hole 24. However, in the rhyme process, the via hole 24 is formed. The bottom corner of the sidewall or via hole 24 forms a residue %, wherein the residue 26 is usually a polymer (tetra) or an impurity containing atoms such as carbon, stellite, nitrogen, fluorine, and titanium. The residue 26 covers the interlayer. The surface of the hole 24 creates a chamber memory effect that affects the critical dimensions of the subsequent process and the quality of the contact plugs formed in the vias. For example, see Figure 3, followed by a The ashing process is performed to remove the photoresist layer. In the prior art, oxygen (oxygen, 〇2) is usually used to remove the photoresist layer 2. In addition, the ashing process can also be combined with nitrogen by oxygen (nitr〇gen). , N2), or in combination with a small amount of tetrafluoromethane 'CFO. Although this ashing process can effectively remove the photoresist layer 20 and destroy the polymer bond of the residue 26, it is often on the dielectric layer 18. Another photoresist residue is left 3 〇. However, this ashing process cannot effectively remove the fluorine residue 26 from 6 1330878. On the other hand, although the method of ashing with oxygen is about 4 to • the method of ashing is helpful to remove the polymer residue 26, 1 • The method of removing the photoresist layer 20 by gas also easily leaves fluorine-containing residues 28, 32 on the sidewalls or bottom corners of the via hole 24 and the surface of the dielectric layer 18, and these residues ^, 3, 32 are also It will affect the subsequent process effect and the electrical performance of the contact plug. Therefore, the conventional technology usually has to use a very expensive liquid solvent to clean the semiconductor skirt '1〇' after the residue 28, 30, 32 is removed, and then A trench structure is formed. _ Referring to FIG. 4, a patterned photoresist layer (not shown) is formed on the dielectric layer 18. The patterned photoresist layer has a trench pattern and is then patterned through the trench pattern. The electrical layer 18 forms a trench structure 34 on the upper portion of the dielectric layer 18. Finally, the patterned photoresist layer and a portion of the stop layer 16 are removed to expose the conductive layer 14 in the via hole 24 to complete the dual damascene hole. Production. As can be seen from the above When a via hole is formed, it is easy to form a residue on the surface of the via hole, and when the photoresist layer is removed by a fluorine-containing gas such as carbon tetracarbonate, it is also easy to form a layer on the surface of the via hole or the layer (4). Residues must be used to make the thief's high solvent 'month wash'. Solvents or chemical materials are usually the most costly in the semiconductor process - so how to change the cost of the double-work process is still low, still It is an important subject for the research of the industry S. [Invention] The main purpose of this month is to provide a dual-joint method for removing light and residue by using carbon monoxide 7 1330878 monoxide 'CO) and deionized water (water) In order to solve the above problem, it is necessary to use a south cost solvent to clean the via hole in the method for fabricating the dual damascene structure. According to the patent application scope of the present invention, the dual damascene structure is provided by first providing a substrate-containing conductive layer, a first butterfly stop layer, a dielectric layer and a photoresist layer on the substrate surface. surface. Then, the pattern resist layer is defined by the first photoresist layer, and then the process is performed, and the dielectric layer is removed through the interlayer __ until the exposed layer is stopped, and is in the dielectric layer. Forming - a via structure. Next, a first ashing process is performed to shift = the first photoresist layer, and the ashing process is performed by supplying a gas containing carbon monoxide. Then, a gap-filling polymer material is formed in the via-hole structure (Qingxian Next, patterned Hantu "_人$Moldwood pattern into a second etching process, through the ditch pattern and _ Jie Wei' for dielectric The formation of the layers - the structure of the ditches, the structure of the canal exposed to the mesostructure. The migration, the exposure (4) the first side of the stop layer. ^ The phase of the planting and the layer of the structure of the roots of the application, additional wealth - materials The structure of the semi-guided semiconductor device, the surface of which comprises - is formed in the dielectric layer through the side, and the phase structure is shattered with a side residual gas into the gas containing carbon monoxide. Finally, in the reaction chamber 8 1330878 • The sand-transfer method contains a carbon monoxide body to make the ashing process, because this crime helps to remove the residue in the interlayer hole and avoid the subsequent production due to the residue. Double-inlaid, the memory effect occurs in the conductive material in the structure, changing the critical dimension of the process and the electrical conductivity of the dual-position. Furthermore, after the ashing process, the method of the present invention can replace the ionized water instead of the habit Knowing the technology to clean the interlayer hole with a high cost liquid solvent, Significantly reduce the cost of the process to increase the profit of the product. _ [Embodiment] Referring to Figures 5 to 13 of the 'Fig. 5 to Figure 13 is a schematic diagram of the process of the method for manufacturing the double-inlaid structure of the present invention. The method for fabricating the dual damascene structure of the present invention is a via-slice method. First, a semiconductor device 50 including a substrate is provided, wherein the semiconductor device 5 can be a semiconductor wafer. Conductive layer 54, one side stop layer %, and a dielectric layer %, wherein conductive layer 54 is preferably a conductive layer containing copper or other metal material, and the etch stop layer may contain nitride material. In addition, dielectric A layer of ruthenium oxide such as arsenic oxide may be additionally disposed on the layer 58 (not shown). Then, the surface of the dielectric layer is coated with a layer of the first photoresist layer 6 and patterned into a lithography process. A photoresist layer 60' forms a via pattern 62 on the first photoresist layer 60. Then, as shown in FIG. 6, a first process is performed to pass through the via pattern 62 to form a dielectric layer 58. , formed in the dielectric layer 58 (10) - 64. At this time, the sidewall surface of the material secret And the bottom corner usually leaves the residue after the residue, which is usually 9 1330878 is a high molecular material containing materials such as m Dun and titanium. • Next 'to perform a first - ashing process to remove the first photoresist layer 60 Please refer to the 7th f苐-ashing process can be carried out by the process device 1 . The process device 1 is reacted to 102 radio (radio frequency 'RF) generator 106, carbon oxide supply source 108 and an oxygen gas. (〇xygen, 〇2) The supply source 11〇. The reaction to 1〇2 includes a crystal 81 socket 112 for carrying the semiconductor device 5〇, and no, the line generating benefit 106 is connected to the wafer holder 112. In order to effectively remove the residue 66, the method of the present invention provides a gas containing carbon monoxide to remove the photoresist layer 60 in the first ashing process. As shown in FIG. 8, the first ashing process performs a ashing process of about 15 to % seconds by supplying carbon monoxide from the carbon monoxide supply source 108 to 2 G to _ standard correction per minute (eubi_to coffee permmute 'sccm). The pressure is about 30 to 1 Torr (mTbrr) and the total power is measured to the surface watt. In addition, oxygen can be supplied from about 2 Torr to _ fresh ML per minute in the first ashing process. Since the first-ashing process is less effective in the first-ashing process, it is effective in improving the removal efficiency of fluorocarbon-containing compounds (C-containing fluorine-containing residues). Residue 66 is within the mesopores, and the anti-Lufu nr · CO + F2 -> C0F2 (gas) will not cause the first ash of the tantalum nitride with carbon oxide as the reaction gas. The loss of the etch stop layer 56. 1330878 Referring to Figure 9, followed by a second ashing process, about 200 to 2000 standard milliliters of oxygen per minute is introduced into the reaction chamber i〇2, and the pressure is about 2 Torr to 8 Torr, total power is about 5 〇〇 to 2000 watts, and the process time is about 4 〇 to 9 〇 seconds. Then, as shown in Figure 10, a deionized water cleaning process is performed to completely remove the interlayer. Residue 66 in the cavity 64. As described above, since the present invention is capable of suppressing fluorocarbon residues and improving fluorocarbon residues by introducing oxidized %i into the reaction chamber 1〇2 in the first ashing process. The removal effect of the object 'so that the hair is supplied with deionized water after the ashing process' can effectively remove the interlayer hole 64 And the residue 66 on the surface of the dielectric layer 58. In other embodiments, the method can be performed before the deionized water cleaning process: the crystal back cleaning process. In a specific machine, the crystal back cleaning process will firstly semiconductor Device 5G or semiconductor crystal ugly surface, cleaning the crystal back with sulfur, and then cleaning the front side of the semiconductor device 50 _ front side 'rich ion water cleaning casting device 5' This step can also effectively remove the residue 66 'can therefore replace The above process further provides deionized water to remove the residue 66. Referring to Figure 11, a caulking polymer layer 68 is applied to the substrate 52 and filled with a via hole 64. The caulking polymer layer 68 is generally It consists of a photoresist (Linephotoresist) adapted to a 365 nm source. The application of the caulking polymer layer 68 is similar to the general photoresist coating process, followed by bake hardening. Then, the process is carried out, and the polymer layer 68 is slit back to a predetermined depth. The woven fabric is further coated with a first layer of 7 〇 on the substrate 50, and filled with a knives having no caulking polymer material in the via hole 64. A second lithography process is performed to pattern the second wire layer 7G to form a trench pattern 72 in the second photoresist layer / Q 70. As shown in FIG. 12, a second etching process is performed to etch a |6 6 to a predetermined depth via the trench pattern 72 to form a trench 74 in the dielectric layer 58. Narrow removes the ..., stupid, nine-layer layer 7 and the caulking polymer layer 68 in the via hole 64, and exposes the residual stop layer 56. Finally, as shown in FIG. 13, the etch stop layer 56 is removed, and β is formed into a drain 74 by a chemical vapor deposition process or a sputtering process to form a lightning flux of a J ^ ^, and the conductive layer 78 may be copper or The metal material such as aluminum completes the fabrication of the double-inlaid structure 76. έ 明 明 明 Referring to Figures 14 to 19, Figures H4 to 19 are schematic views of the process of the second embodiment of the dual damascene fabrication method of the present invention. First, a semiconductor device 150' includes a substrate 152, a conductive layer 154, a first side stop layer 156, a lower dielectric layer 158, a second silver stop layer 16A, and an upper dielectric layer. The nitrous oxide layer 164 and the oxidized stone layer 166 are sequentially disposed on the surface from bottom to top, wherein the first residual stop layer 156 may be a nitride layer, and the second stop layer (10) may be nitrogen oxide. The layer is cut, and the conductive layer 154 is preferably a metal layer. The patterned first photoresist layer (10) is then formed on the emulsified nightmare layer, wherein the barrier layer 168 comprises a via pattern. A first side process is performed to remove the exposed upper dielectric layer (6), the second _ stop layer Π: electricity ' to the surface of the ith stop layer 158 via the layer to form the via 170. At this time, the residue 172 is formed on the surface of the sidewall of the via hole 17G. 12 gas == _ a ashing process, providing - oxidized Wei ^ 166 * ' ^ ah remove some of the residue 172. The yttrium oxide pad = part of the photoresist residue under the surface f _ _ conductor 150 - the second ash process. The slit is subjected to a _2 & (total removal of the residue 172 and the photoresist residue 174 in the via 170 and the oxidized transition layer 166, as shown in Fig. 17. ★ Please refer to Fig. 18, in the via hole (7) Filling a caulking polymer layer (7), which can be formed by a conventional coating process and bake hardening. Then, the backfilling polymer layer '2' forms a notch in the interlayer hole 17〇. Then, a photoresist layer 174' is coated on the surface of the substrate 152 to perform a lithography process to pattern the second photoresist layer 174 to form a trench pattern 176. Then, as shown in FIG. 19, a second side process is performed, via the trench pattern 176. The partial oxidation light layer 166, the nitrogen oxide conversion layer 164, and the upper dielectric layer 162' are removed to the second side stop layer 16A' to form a double inlaid hole 178. Finally, the second photoresist layer 174 is removed and the caulking is high. The molecular layer 172 is re-exposed to the first etch stop layer 156. Thereafter, a metal conductive layer (not shown) may be formed in the dual damascene hole 178 to complete the fabrication of the metal dual damascene structure. The method of the hole is to pass carbon monoxide as a reaction gas in the ashing process, and The residue containing fluorocarbon is inhibited, and the removal efficiency of the residue is improved. Therefore, after the ashing process, the present invention only needs to use the deionized water to effectively remove the residue in the via hole without using conventional techniques. The high-cost liquid solvent to clean the via hole can greatly reduce the process cost. Moreover, because a 1330878 carbon oxide gas ashing process can effectively remove the residue on the surface of the via hole, it can be preserved in subsequent processes. Preferably, the critical dimension is, for example, opening a tantalum nitride etch stop layer and forming a conductive material in the via hole. Further, the method of cleaning the via hole of the present invention can be applied to other processes including etching and ashing to remove Residue after etching, such as ditch first double damascene or partial interfacial dual damascene technology. The above mentioned only the invention is difficult to achieve, the equalization and modification of the invention should be covered by the present invention. [Simplified Schematic] Fig. 1 to 4® are the schematic diagrams of the two-town embedded structure of the present invention. The parties to a first embodiment of the first embodiment) FIGS. 1 to 19 of the present picture shows a schematic view of the process of the invention is made of a dual damascene structure. Second Embodiment 10 14 20 24 34 52 [Description of Main Components] Semiconductor Device Conductive Layer Photoresist Layer Dielectric Ditch Structure Substrate 12 Substrate 18 Dielectric Layer 22 Via Pattern 26, 28, 3〇, 32 Semiconductor device conductive layer 50 Residue 54 1330878
56 触刻停止層 58 介電層 60 第一光阻層 62 介層洞圖案 64 介層洞 66 殘留物 68 填縫高分子層 70 第二光阻層 72 溝渠圖案 74 溝渠 76 雙鑲嵌結構 78 導電層 100 製程裝置 102 反應室 106 無線電產生器 108 一氧化碳供應源 110 氧氣供應源 112 晶圓承座 114 反應物供應管線 150 半導體裝置 152 基底 154 導電層 156 第一 1 虫刻停止層 158 下介電層 160 第二蝕刻停止層 162 上介電層 164 氮氧化矽墊層 166 氧化矽墊層 168 第一光阻層 170 介層洞 172 殘留物 174 光阻殘留物 176 溝渠圖案 178 雙鑲嵌孔洞 1556 etch stop layer 58 dielectric layer 60 first photoresist layer 62 via pattern 64 via hole 66 residue 68 fillet polymer layer 70 second photoresist layer 72 trench pattern 74 trench 76 dual damascene structure 78 conductive Layer 100 Process Device 102 Reaction Chamber 106 Radio Generator 108 Carbon Monoxide Supply Source 110 Oxygen Supply Source 112 Wafer Bearing 114 Reactant Supply Line 150 Semiconductor Device 152 Substrate 154 Conductive Layer 156 First 1 Insect Stop Layer 158 Lower Dielectric Layer 160 second etch stop layer 162 upper dielectric layer 164 yttrium oxynitride pad layer 166 yttrium oxide pad layer 168 first photoresist layer 170 via hole 172 residue 174 photoresist residue 176 trench pattern 178 double damascene hole 15