TWI330844B - High-bandwidth magnetoresistive random access memory devices - Google Patents

Description

1330844 P51950188TW 23746twf.doc/n IX. Description of the invention: [Technical field of the invention] t The present invention generally relates to a high frequency wide magnetoresistive random access memory (MRAM 'magneticoresistive random access memory) Its method of operation. [Prior Art] MRAM devices have been proposed for use as, for example, static random access memory (SRAM), dynamic random access memory (DRAM), dynamic random access memory (DRAM), and flash memory. An alternative to the conventional memory device of flash memory. The device uses a magnetoresistance effect to store data. The magnetoresistance effect refers to the phenomenon that the resistance of a material changes with the magnetic field felt by the material. Compared with these conventional memories, MRAM devices show superiority in terms of speed, integration density, power consumption, radiation hardness, and durability. 1 illustrates an exemplary MRAM device including an array of memory cells. Only the memory cell 1〇2 of one of the memory cells is shown. The MRAM device 1 includes a plurality of write bit lines 1〇4 and a plurality of write characters. Word line 106. The write bit line 1〇4 and the write word line 丨〇6 are substantially perpendicular to each other. Each memory cell corresponds to a write bit line 1〇4 with " and a write word line 106. The memory cell 102 includes a fixed magnetic domain 1〇8, a free magnetic domain 11〇, and a tunneling barrier 112 sandwiched between the fixed magnetic domain 108 and the free magnetic domain 11〇. The dental barrier 112 can include, for example, oxidized (Al2〇3) or magnesium oxide (MgO). 1330844 P51950188TW 23746twf.doc/n The fixed magnetic field 108 may comprise a fixed ferromagnetic or synthetic anti-ferromagnetic (SAF) structure. 1 is fixed; the magnetic region 108 includes a three-layer SAF structure including two ferromagnetic layers 114 and 116 sandwiching the antiferromagnetic coupling. The ferromagnetic layers ^ 114 and 116 may include, for example, guar iron (CoFe), iron (NiFe) or cobalt iron boron (CoFeB). The antiferromagnetic coupling spacer layer U8 may include, for example, ruthenium (Ru) or copper (Cu). The thickness of the antiferromagnetic coupling spacer layer 118 is selected such that the ferromagnetic layers 114 and 116 are antiferromagnetically coupled to each other. Free magnetic region 110 may include a previous free magnetic layer or SAF structure. Figure 1 depicts the non-free magnetic region]____ contains two ferromagnetic layers 120 and 122 which are antiferromagnetically sandwiched between the spacer layers 124. The ferromagnetic layers 120 and 122 may include, for example, cobalt iron (coFe), cobalt iron boron (CoFeB), or nickel iron (NiFe). The antiferromagnetic detachment spacer layer 124 may include, for example, ruthenium (Ru) or copper (Cu). The thickness of the antiferromagnetic splicing spacer layer 124 is selected such that the ferromagnetic layers 120 and 122 are antiferromagnetically connected to each other. If the magnetic moments of the ferromagnetic layers 120 and 122 are significantly different, the SAF structure can be equivalent to a single free magnetic layer. An antiferromagnetic pinned layer 126, a buffer layer 128, a bottom electrode 130, and a dielectric layer 132 are sequentially provided between the fixed magnetic region 108 and the write word line 106. The antiferromagnetic pinned layer 126 may comprise, for example, a chain spur (ptMn) or a silver sulphide (Mnlr). The buffer layer 128 may include, for example, nickel iron (NiFe), nickel iron chromium (NiFeCr), or iron deposit (NiFeCo). A top electrode 134 is provided on the free magnetic region 110, and 1330844 P51950188TW 23746twf.doc/n provides a dielectric layer i36 between the top electrode 134 and the write bit line 1〇4. The antiferromagnetic pinned layer 126 fixes the magnetic moment of the fixed magnetic domain 1〇8 so that the magnetic moment of the fixed magnetic domain 108 does not rotate when a moderate magnetic field is applied. On the contrary, the magnetic moment of the free magnetic domain 110 is free to rotate under an external magnetic field. ".The magnetizing 108 has an easy axis (easy) along the direction of the writing word line, and the free magnetic field U〇 has two easy axes that are anti-parallel to each other and also in the direction of the writing word line 106. . As is well known in the art, the axis refers to the magnetic dipole moment of the anisotropic material in the absence of an external magnetic field or bias field (the essential orientation of the dislocation plus dip〇ie. The electron tunneling barrier of the tunneling barrier 112 and the resistance of the memory cell 1〇2 vary with the magnetic field. For example, when the ferromagnetic layers 116 and 12 are each magnetic momentvect〇r parallel to each other The tunneling barrier 112 has a low electron tunneling barrier, and the memory cell 1〇2 has a low resistance. When the respective magnetic moment vectors of the ferromagnetic layers 116 and 120 are antiparallel to each other, the tunneling barrier 112 has a high The electron tunneling barrier, and the memory cell 1〇2 has a high resistance. Therefore, the memory cell 1〇2 can store the value of its resistance by the “1” or “0” of the one-dimensional element of the boundary. For example, the high resistance of memory cell 102 can represent a one-bit "1", and the low resistance of memory cell 1〇2 can represent a one-bit "〇", or vice versa. Adjusting the magnetic moment vectors of the ferromagnetic layers 120 and 122 (so-called "spin rotation,") to rotate the ferromagnetic layer 120 And a magnetic moment vector of 122 to write the data of the one-bit element into the memory cell 1〇2 such that the magnetic moment vector of the ferromagnetic layer 120 is parallel to the magnetic moment vector of the ferromagnetic layer 116 or inverse 1330844 P51950188TW 23746twf. Doc/n ^ ^ Appropriate for writing to the bit line to tear to = Μ line hall to induce external rhyme 'external magnetic field to change the magnetic moment of ferromagnetic layers 120 and 122. Read bit current Id by writing bit line ι〇4 The circular digital magnetic field Hd is induced, and the circular character magnetic field Hw is induced by the word current Iw written to the word line 1 。 6. The strengths of the magnetic fields Hd and Hw are proportional to the digit current ID and the word current Iw, respectively. The in-line line is above the memory cell H)2, and the write word line 1% is below the memory cell 1〇2. Therefore, as shown in Figure 1, when the digital current 1〇 flows from left to right Day τ hd is only in the direction from the outside of the paper to the paper in the plane of the memory cell. Conversely, when the digital current Id flows from right to left, % is essentially left inside the paper in the memory cell. In the direction of the paper in the plane of 102. Similarly, the word current ^ as indicated in Figure 流 flows from the outside of the paper to In the paper, Hw is substantially in the direction of the memory cell 102. In order to write the data of one bit to the memory = to: first provide the word current w by writing the word line 1G6 to memorize The character magnetic field Hw in the plane perpendicular to the easy axis of the free magnetic domain 11 is generated in the plane of the body cell 102. Therefore, the magnetic moment vector of the ferromagnetic layer 120 is in a direction substantially perpendicular to the easy axis of the free magnetic region 110. Alignment. Next, a digital current ID written by the bit line 104 is supplied to generate a digital magnetic field Hd in the direction of one of the easy axes of the free magnetic region 11A. Therefore, the magnetic moment of the ferromagnetic layer 12 is aligned with the easy axis of the free magnetic domain 110. If the digital magnetic field ^^ is in a direction parallel to the easy axis of the fixed magnetic region 1〇8, a one-dimensional 〇 is written into the five-body cell 102. The right digit magnetic field hd is written in the direction parallel to the easy axis of the fixed magnetic field 108, and the one-bit "1" is written into the 1330844 Ρ51950188TW 23746twf.doc/n memory cell 102. The memory cell 102 can be read by sensing its resistance. The MRAM device 100 includes a plurality of read word lines (not shown) and a plurality of read bit lines. Each memory cell corresponds to a read word line and a read bit line and includes a transistor coupled to the corresponding read word line. The MRAM device 100 also includes a sense amplifier, each of which is consuming one of the read bit lines to sense the current passing therethrough. As shown in FIG. 1, the transistor 138 is connected to the bottom electrode 130 of the δ memory cell 102, and the sense amplifier 140 is coupled to the top electrode 134 of the memory cell 1〇2. The corresponding read word line is coupled to the gate of the transistor 138. The corresponding read bit line is coupled to the top electrode 134. In order to retrieve the data stored in the memory cell 1〇2, the corresponding read word line is read and the bit line is read to select the memory cell 1()2. Therefore, the transistor 38 is turned on, and a current C is applied between the top electrode 134 and the bottom electrode 13A and the current through the memory cell 1〇2 is sensed by the sense amplifier 140. As shown in FIG. 1, the sense amplifier 140 is also coupled to sense a reference current through a reference cell (not shown). The sense amplifier (10) compares the current through the clamped cell 1〇2 with the reference current to determine the state of the memory cell 102. In the second sample, the top electrode 134 of the cell 1 〇 2 can be passed through the dielectric layer 136 to form a house 4 · human j · η -, j - Ύ metal 4 king base (not shown And electrically connected to the corresponding bit line 2 ι〇4. Thus, U.S. Patent No. 6,757,189, which is incorporated herein by reference, discloses a high-density &", wherein each memory cell of the high-density MRAM device is 1330844 P51950188TW 23746twf. Doc/n contains multiple magnetic memory units for storing multiple data bits. Figure 2 depicts a high density MRAM device as disclosed in Hung et al. As shown in FIG. 2, the MRAM device 200 includes a plurality of memory cells 202, wherein 202, 202, 3, and 2 are shown. Each memory cell 202 corresponds to a bit line 61^, a read word line RWL, and two write characters, WWL. Each memory cell 2〇2 contains two memory cells 102] and 1〇22 connected in parallel. For example, the memory cell 2〇2ι contains two #S memory units 1021 and 1022 and a transistor 138. Each of the memory units 102l and 1022 has the same structure as the memory cell 1〇2 in the figure. Each bit line BL serves as a write bit line and a read bit line. The memory unit 102 and 1〇22 are connected in parallel between the drain of the transistor 138 and the corresponding bit line BL. The source of transistor 138 is grounded. The gate of transistor 138 is coupled to the corresponding read word line RWL. In FIG. 2, the memory unit 1021 of the memory cells 202 and 2022 corresponds to the first write word line WWL1; the memory units 1102 of the memory cells 2021 and 2〇22 correspond to the second write. Word line WWL2; memory cells 2023 and 2〇24 memory unit lG2l correspond to first-write character line wu; (10) body cell. 203⁄4 and move 4 memory list % corresponding to second write Word line WWL4. In addition, the memory cells 2021 and 2〇22 correspond to the first read word • the element line RWL1; the memory cells 2〇23 and 2024 correspond to the second read word line RWL2; the memory cell and the fiber 3 correspond to The first bit line BL1, and the memory cells 2022 and 2024 correspond to the second bit line]5]12. Each of the bit lines BL1 and BL2 is also lightly connected to the sense amplifier 140 via the transistor 2〇4. Since each memory cell 2〇2 contains two memories 1330844 P51950188TW 23746twf.doc/n body unit 102] and 1022, the MRAM 200 has a high data storage density. MRAM200 is manufactured so that R]max//R2max, Rimax//R2rain,

Rlmin//R2max, R丨min//R2min all have different values, wherein the Ri leg is the high resistance of the memory unit 102, Rlmin is the low resistance of the memory unit 1〇2丨, and R2max is the memory unit 1022. The resistance, R2min is the low resistance of the memory unit χ 〇22, and R//R2 represents the two resistors & First, one of the memory cells 202 to be read is selected by activating the corresponding read word line RWL, and the sense amplifier 14 detects the current through the corresponding bit line BL. The sense amplifier 14 比较 compares the detected current with three intermediate reference currents Refl, Ref2, and Ref3, where Refi and the tool correspond to Rlmax//R2max, Rlmax//R2min, the heart, and R]mm/ Two reference resistor values between /R2min, R2, R3. Assume (for example) ruler position / / ruler 2 dirty > Rl > Rlmax / / R2min > R2 > Rlmin / / R2max > R3 > heart 眺胤 ^. Therefore, if the detected current is between Refl and Ref2, the resistance of the selected memory cell 202 is Rlmax//R2mi. Therefore, the memory unit 102ι of the selected memory cell 202 will be a bit. The memory unit 1〇22 of the selected memory cell 2〇2 stores the one-bit “〇” therein. Figure 3Α shows the clock signal CLK and the first read word. A series of signals on the first bit line BL1 for reading the memory cells 2 〇 2 ι on the first bit line BL1. On the rising edge of the clock signal CLK, a start signal is provided on the first read word line RWL1 ( For example, a positive voltage), and an enable signal is provided to turn on the transistor 204 coupled to the first bit line BL1. Therefore, the transistor 138 of 12 1330844 P51950188TW 23746twf.doc/n memory cell 202 is turned on and A voltage bias is applied to the transistor 204' coupled to the first bit line BL1 and across the memory cells 102! and 1022 of the memory cell 202. The sense amplifier 140 detects the current through the first bit line BL1 ( That is, the memory unit through the memory cell 2〇2ι 1〇2丨 and 1〇22 Current) and compares the detected current with three reference values Refl, Ref2, Ref3. Based on the result of the comparison, the sense amplifier simultaneously outputs two bits of data D0 and D1. In Figure 3A, D0 and D1 The shaded area is the period during which the data is transmitted, and the clear areas of D and D1 are periods in which no data is transferred or the previous data is latched. Therefore, each memory cell 202 can output two during a cl〇ck cycle. One bit of data, and is used to read the bandwidth of the MRAM device 2 or the read bandwidth of the MRAM device 200. However, according to Hung et al., only the data of the bit can be used in one clock cycle. Into each memory cell 2. 2, and writing two bits of data into each memory cell 202 requires two clock cycles. In the example - Figure 3B shows the write character Lines wwu and WWL2 and a series of signals on the first bit line BL1 for writing data into the memory cell 2, in particular, by first providing a first write word line WWL1 Current and then provide power in the appropriate direction through the first bit line BU Flowing to write the data of one bit to the memory unit 1〇2ι of the memory cell 202 in the first clock cycle. In the second clock cycle, the second character is provided by the money The current of line WWL2 and then provide the current in the appropriate direction through the -7L line BL1 to write the data of the - bit to the memory cell! Memory unit 1〇22 13 1330844 P51950188TW 23 746twf. In doc/n, in order to define the state of the memory unit ship and the memory I bit 2 by the current of the first bit line BL1, the 8 1 of the material element is written to the memory fresh bit 1G2l sigh towel. Similarly, the shaded area of 'BL1 in =3B is the time period of the transfer data, and the ambiguous area is the time period during which no data is transmitted. Therefore, although the read bandwidth of the MRAM device is doubled by including two memory cells connected in parallel in the memory cell 202, the bandwidth for writing to the MRAM device 200 (ie, MRam 2〇〇) The write bandwidth is limited because two clock cycles are required for each person to remember the cell 202. [Invention] Embodiments of the invention provide a magnetoresistive near-machine memory (MRAM) device that is formed on a substrate, comprising: a read bit line = two or more write bit lines; Read the word line; write the word line, 'and: the quality i i i in the bit line; and the memory cell, which corresponds to the reading of:, take the word line, write the character line And two or more write lines 'where the memory cells include the first-memory memory unit, each--------------------------------------------------------------------------------------------------- ; fixed solid two ^ has a second easy axis; and wear-resistant barrier, in the free magnetic region and between the 'the first memory unit has two resistance - You Ya 1 - § memory unit free magnetic The magnetic moment of the zone and the magnetic 2 of the fixed magnetic zone = the first resistance; and the free magnetic zone magnetic moment when the first memory is established. The second resistance when the magnetic moment of the fixed magnetic domain is anti-parallel, the second 1330844 P51950188TW 23 746twf.doc/n in the basin § The early position has two resistances - the magnetic moment of the magnetic zone and the fixed magnetic zone The magnetic four early resistance from the thousand (four) brother four resistors, wherein the first - resistance, the inverse and the fourth resistance are different resistance values, and wherein the first - cross-sectional area and the second memory unit::

And the plane of the second read current is called the second product, which is twice the cross-sectional area of the 々. Said, will be 7 can be literated. The present invention has been developed by the present invention, and the features and advantages of the invention will be derived from the specific scope and combination of the appended claims. , to understand the general description of the text and the detailed description below as exemplary. Interpretive and intended to provide a further solution to the invention as recorded

[Embodiment] A detailed reference will be made to this embodiment of the present invention, and an example will be added to the accompanying drawings. The same reference numbers are used throughout the drawings to refer to the same or similar elements. The present invention, as an embodiment, provides a high-frequency wide MRAM device having not only high reading efficiency but also writing efficiency, and a method for the MRAM device. Door Collar Figure 4A illustrates a MRam device P51950188TW 23746twf.doc/n 400 consistent with the first embodiment of the present invention. The MRAM device 400 includes an array of memory cells 4〇2, depicting four of the memory cells 402, 4022, 4023, 4024. Each memory cell 4〇2 corresponds to a read bit line RBL, a read word line RWL, a write word line WWL, and a plurality of (specifically two in FIG. 4A) write bit lines WBL. . The mother-memory cell 402 includes two memory units 404 as memory units 4〇4ι and 4〇\ connected in parallel between the transistor 4〇6 and the corresponding read bit line RBL, wherein the transistor 4〇 The gate of 6 is connected to the pair 2 and the word line RWL should be read. Each memory unit 4〇4 corresponds to one of the write bit lines WBL. As shown in FIG. 4A, the memory cells 4〇2ι and 4〇22 correspond to the first read bit line RBL0; the memory cells 4〇2ι and 4〇22 of the memory unit 4G (corresponding to the first-writer) The bit line WBL(); and the memory unit 4〇42 of the memory cells 4〇1 and 4022 correspond to the second write bit line WBU. The memory cell transfer 3 and the move* correspond to the second read bit The memory unit 4(10)1 of the line ''remembering cells 4〇23 and 4〇24 corresponds to the t-th write bit line WBL2; and the memory unit side 2 of the memory cells 4023 and 4024 corresponds to the fourth write bit a line WBU. The memory cells 'and 403⁄4 correspond to the first read word line ^^ and the first write word line WWL0; and the memory cell 2 and the 4 correspond to the second read word j RWLl And f writes the human character line wwu. The sense amplifier ·, = select transistor 410 (four) is connected to each of the read bit line salt ^ to measure the current through the selected memory cell 402. Figure 4B depicts A cross-sectional view of the memory unit 4〇4. The memory unit is formed between the corresponding write word line WWL and the corresponding write bit line wbl. The dummy write bit line WBL is in the memory unit 4〇4 Square write 1330844 P51950188TW 23746twf.doc/n The entry word line WWL is below the memory unit 404, and the write bit line WBL and the write word line WWL are substantially perpendicular to each other. However, it should be understood that the terms "above" and " The lower portion is a relative term that depends on the angle at which the memory unit 404 is observed. The memory unit 404 includes a fixed magnetic region 420, a free magnetic region 422, and a tunneling resistance sandwiched between the fixed magnetic region 420 and the free magnetic region 422. Barrier 424. Tunneling barrier 424 can include, for example, aluminum oxide (A10x) or magnesium oxide (MgO). Fixed magnetic region 420 can include a fixed ferromagnetic or synthetic antiferromagnetic (SAF) structure. Figure 4B depicts no fixed magnetic The region 420 includes a three-layer SAF structure comprising two ferromagnetic layers 426 and 428 with an antiferromagnetic coupling spacer layer 430 interposed therebetween. The ferromagnetic layers 426 and 428 may include, for example, iron (CoFe), Recording iron (NiFe) or Ming iron butterfly (c〇FeB). The antiferromagnetic coupling separation layer 430 may include, for example, ruthenium (Ru) or copper (Cu). The thickness of the antiferromagnetic coupling separation layer 430 is selected. So that the ferromagnetic layers 426 and 428 are antiferromagnetically opposite each other. The free magnetic region 422 may include a SAF, the SAF includes two ferromagnetic layers 432 and 434, and an antiferromagnetic coupling separation layer 436 sandwiched therebetween. The ferromagnetic layers 432 and 434 may include, for example, cobalt iron (c〇Fe) ), cobalt iron boron (CoFeB) or nickel iron (NiFe). The antiferromagnetic coupling separation layer 436 may include, for example, ruthenium (RU) or copper (Cu). The thickness of the antiferromagnetic coupling spacer layer 436 is selected such that the ferromagnetic layers 432 and 434 are antiferromagnetically coupled to each other. Although FIG. 4B only shows that the free magnetic region 422 includes three layers, a single free magnetic layer or a multilayer SAF structure having three or more layers may be used. For example, the free magnetic region 422 can include three or more ferromagnetic layers separated by a cake separation layer 17 < S:) 1330844 P51950188TW 23746twf.doc/n. An antiferromagnetic pinned layer 438, a buffer layer 440, a bottom electrode 442, and a dielectric layer 444 are sequentially provided between the fixed magnetic domain 420 and the write word line WWL. The antiferromagnetic pinned layer 438 may include, for example, platinum manganese (ρΜη) or manganese germanium (Mnli·). The buffer layer 440 may include, for example, nickel iron (NiFe) 'nickel iron chromium (NiFeCr) or nickel iron cobalt (NiFeCo). A top electrode 446' is provided over the free magnetic region 422 and a dielectric layer 448 is provided between the top electrode 446 and the corresponding write bit line WBL. The antiferromagnetic pinned layer 438 is fixed to the magnetic moment of the fixed magnetic region 42〇 so that the magnetic moment of the fixed magnetic region 42〇 does not rotate when a moderate magnetic field is applied. Conversely, the magnetic moment of the free magnetic domain 422 is free to rotate under an external magnetic field. As in the first embodiment of the present invention, the fixed magnetic region 42A has an easy axis Ep, and the free magnetic region 422 has a positive easy axis E+ and a negative easy axis E, wherein all of the fp, E+, and E· are corresponding to the written word. The meta-line and the write bit line are at an angle of about 45 2, and E+ and E_ are anti-parallel to each other. Fig. 4C is a plan view showing the magnetic moment in the memory unit 4〇4 with respect to the direction corresponding to the write bit line WBL and the write word line WWL when the memory unit 404 is viewed from the top. In Fig. 4C, the x-axis is in the direction corresponding to the write bit line WBL, and the y-axis is in the direction corresponding to the write word line WWL. The positive X-axis is in the direction from the left to the right along the write bit line WBL shown in FIG. 4B, and the positive y-axis is from the outside of the paper to the plane of the paper along the write word line WWL shown in FIG. 4B. Inside the direction. In the absence of an external magnetic field, the magnetic moment vectors of the ferromagnetic layers 426, 428, 432, and 434 are aligned with one of the easy axes. In FIG. 4C, the magnetic moment vector A of the ferromagnetic layer 428 is aligned with the easy axis Ep, and the ferromagnetic layer 426 18 1330844 P51950188TW 23746twf.doc/n, the moment vector B is anti-parallel to the magnetic moment vector A, and the ferromagnetic layer 432 The magnetic moment vector C is aligned with the negative easy axis E- and the magnetic moment vector 1 of the ferromagnetic layer 434 is aligned with the positive easy axis E+. In Figures 4B and 4C and in other figures herein. The arrows labeled with the magnetic moment vectors A-D indicate only the general direction of the magnetic moment vectors and do not indicate their relative strength. The electron tunneling barrier of the tunneling barrier 424 and the resistance of the memory unit 4〇4 vary with the magnetic field. For example, when the magnetic moment φ amount A of the ferromagnetic layer 428 and the magnetic moment vector c of the ferromagnetic layer 432 are parallel to each other, the tunneling barrier 424 has a low electron tunneling barrier, and the memory unit 4 〇 4 Has a low resistance. When the magnetic moment vector A of the ferromagnetic layer 428 and the magnetic moment vector C of the ferromagnetic layer 432 are antiparallel to each other, the tunneling barrier 424 has a high electron tunneling barrier, and the suffix unit 404 has a high resistance. Therefore, the memory unit 4〇4 can store a one-dimensional “丨,, or “〇”, which is defined by the value of its resistance. For example, the high resistance of the memory unit 404 can represent a single element. Γ,, and the low resistance of the memory unit 404 can represent a one-dimensional "〇,,, or vice versa. As in the first embodiment of the present invention, the resistance of each of the devices 记忆 记忆 memory cells 402 has a corresponding Different values for different states of the memory cell 402. The memory unit 4〇4〗 and 4〇42 are not the same resistance value, for example, by forming each memory unit to have different physical sizes. The physical size can be achieved by adjusting the cross-sectional area of the memory unit in a plane that is substantially perpendicular to the flow of current when the memory cell 402 is read. In one aspect, the memory unit is 4〇4ι The cross-sectional area can be fabricated to be about 2 times the cross-sectional area of the memory unit 4042. In this bear sample, therefore, the magnetoresistance of the έ 忆 体 unit 40 VII will be lower than the memory unit 19 1330844 P51950188TW 23746twf.doc /n in it; 2) stored in it 3) The magnetoresistance stored in 4042, because the memory unit 404l has a larger physical size due to its larger transverse wear product. Then, the memory cell 402 has four OK states: 1) "00" When the memory unit 404 〗 has stored a % of one yuan, stored in it 'and the memory unit 4 〇 42 has transferred a single yuan to 01 ' when s remembrance early 404 ι has a one yuan "q,, and the memory unit 4042 has transferred the one-bit "Γ" to 10" 'When the memory unit 404' has already been one-bit and the § already remembered the early position 4042 has one bit "0" ''m ^ in it; and 4) "11", when the memory unit 4〇4丨 has stored a "1" of a drink, and the memory unit 4〇42 has a one yuan疋1 "Stored in it." Next, memory cell 402i also has four possible resistance values corresponding to their four possible states, respectively. In other words, % Rimax"R2max, Rlmax//R2min, Rlmin//R2max, different values' where Rlmax is the high resistance of each memory unit and the low resistance is 4G+ per unit, and the ruler is 2 memory per memory^ The resistance of the bit 4〇42, R2min is the low power limit of each memory unit. Therefore, it can be read from the selected memory cell 402 in the ~眭 pulse period by determining the resistance of the selected memory cell 402. Take two bits of capital' will read, physically move! Consider as an example. Figure 5 depicts the co-signal of the pulse signal c and the read-and-receive leg ^. The rising signal L of the clock signal CLK provides a start signal (for example, positive j) on the 5|receiving line (3), and the transistor 4〇6, & The enable signal (not ') is connected to the read bit line RBLO by #_ to the select transistor 410 of the read bit line ship 20 1330844 P51950188TW 23746twf.doc/n. Therefore, the memory voltage between the read bit line RBL0 and the transistor 406 is applied across the memory cells 404] and 4042 of the memory cell 402, and the sense amplifier 408 measures the current through the bit line RBL0 (also That is, the memory unit 404] and the current of 4042 are stored by the memory cell. The sense amplifier 408 compares the detected current with three intermediate reference current values Refl, Ref2, and Ref3 Ref Ref2, Ref3 corresponds to Rlraax//R2max, R]max//R2min,

Reference resistance value Rl, R2, R3 0 between Rlmin//R2max, R]min//R2min false 疋 (for example) Rlmax//R2max > Rl > Rlmax//R2mh > R2 > Rlxnin//R2max > R3 > Rlmin//R2min. Therefore, if the detected current is between Refl and Ref2, the resistance of the memory cell 4〇2 is Rima//R2_. Therefore, the memory unit 454丨 of the memory cell of the memory cell 402 stores a one-digit "1" therein, and the memory unit of the memory cell 402! 4〇42 stores a zero of the 兀0 among them. Thus, during one clock cycle, two bits of data can be read from each memory cell 402. In Fig. 5 and subsequent figures showing the sequence of signals, the shaded area indicates the period in which the data is transmitted, the clear area refers to the period in which the transmission is transferred or the previous (10), and the different types of shading indicate separations that may or may not be identical to each other. Bit information. If the first entry is not poor - the display 400 also has a high write, during the one-clock cycle, the memory of the two cells can be selected by the field. The second embodiment of the present invention (4) triggers the writer method to write the data of two bits into the selected memory cell 402 of device 400. According to 21 1330844

P51950188TW 23746twf.doc/n Double-sentence method “Firstly, the person to be written is recorded, and the data of the _ position in the It unit is compared with the data stored in the memory unit. If the feed to be written is the same as the data stored in the memory unit, then ^== does not execute. = Then, change or "toggle trigger", the state of the memory unit. If necessary, it can simultaneously trigger the selected memory cell 4(10) of the memory cell 4(4) 4〇4! and 4042. Figure 6 and Figures 7(a) through 7(e) depict a second embodiment. It is assumed that the memory cell 4〇 is selected for the write operation. 'For one of the two-state trigger write memory unit 404, The write current is supplied to the corresponding write word line WWL and the write bit line Wbl to induce an external magnetic field, thereby changing the magnetic moment of the ferromagnetic layer 432. FIG. 4b and FIG. 4C illustrate the supply to the write bit line. The relationship between the WBL and the current written to the word line WWL and the external magnetic field induced thereby. The circular word magnetic field Hw is induced by the word current Iw written to the word line WWL, and is written by the bit line WBL. The digital current ID induces a circular digital magnetic field Hd. The intensities of the magnetic fields Hw and Hd are proportional to the word current Iw and the digital current 1〇, respectively, and, as illustrated in FIG. 4B, when the word current iw is positive (ie, at In the positive y-axis direction, Hw is substantially in the positive X-axis direction in the plane of the memory unit 4〇4 Upper; when the digital current ID is positive (ie, in the positive X-axis direction), HD is substantially in the positive y-axis direction in the plane of the memory unit 404. Figure 6 is used to write data to The write word line WWL0 and the write bit line WBL0 provided by a peripheral circuit (not shown) (hereinafter referred to as a write circuit) in the memory cell 4以2 are 22 1330844 P51950188TW 23746twf.doc/n and write a series of signals on the bit line WBLl. As shown in Figure 6, the clock 1 CLK rises at time t 。. Between time t 〇 and time, between the logic circuit ( (not shown) read the memory cell 4〇2ι, compare the material in the memory cell 4〇2i with the data to be written into the memory cell 4〇2], and determine whether the memory should be triggered by the two states. One or both of 404 ι and 4 〇 42. 疋 疋 己 单位 单位 404! The stored bit data is the same as the bit data to be written to it, and the memory unit 4 〇 42 stored bit data Different from the bit data to be written to it, therefore, the memory unit 4042 should be triggered in a dual state, and should not be triggered by a double state. The memory unit is 4〇4. Next, the write circuit sequentially supplies the digit current and the word current to the binary state memory unit 4042. Specifically, at time t2, the positive bit current is supplied via the write bit line WBL1. At time t], the positive word current Iw is supplied via the write word line WWL0; at time ^, iD is turned off; and at time, iw is turned off. The clock signal CLK falls at time, after t During the period from 〇k to k, no current is supplied via the write bit line WBL〇. Since the word current and the bit current are supplied as shown in Fig. 6, the binary state triggers the memory unit 4042, and the state of the memory unit 404 is kept unchanged. Fig. 7 (a) to Fig. 7 (e) illustrate the process of writing the memory unit 4 〇 42 by the iD shown in Fig. 6 and the ? The magnetic moment vectors C and D in the following description of Figs. 7(a) to 7(e) refer to the magnetic moment vectors C and D of the memory unit 4〇42. Figure 7 (a) shows the magnetic moment vector C of the ferromagnetic layer 432 at time t 〇 and t! and the ferromagnetic layer 434 23 1330844 P51950188TW 23746twf. doc/n when word current or digital current is not supplied.

The magnetic moment vector D. The magnetic moment vector C is in the direction of the negative easy axis E of the free magnetic region 422 and the magnetic moment vector D is in the direction of the positive easy axis of the free magnetic region 422. Fig. 7(b) shows the magnetic moment vectors c and ^ at the time t2 when the digital magnetic field HD is substantially induced on the positive y, and the magnetic field HDT, the Wei vector c, and the ! turn. The magnetic moment vector c is in the direction between the negative X-axis and the positive x-axis. The direction between the magnetic moment vector d X-axis and the positive easy axis of the free magnetic region 422. Fig. 7(4) shows the magnetic moment vectors c and d at time t3 when the magnetic field is substantially induced in the forward direction. Therefore, the magnetic moment vectors c and D_ are rotated again. The magnetic moment vector c is close to the positive y-axis and the magnetic moment vector D can cross the positive X-axis. Figure 7(4)1 shows the magnetic moment vectors c and D at time U when 1d is cut. Therefore, the magnetic moment vectors c and D continue to rotate the needle. The magnetic moment vector ^ can cross positive # and approach the positive easy axis E+ of the free magnetic H 422. The magnetic moment vector D is close to the negative X axis. Fig. 7 (〇 shows that the magnetic moment vector c at time 5 is also fD when Iw is also cut off. Since the magnetic moment vector C is closer to the negative easy axis E. of the free magnetic region 422, the near positive axis E+, Therefore, the magnetic moment vector [continuously rotates clockwise and is aligned with the positive easy axis E+ of the free magnetic region 422. Since the magnetic moment vector d is closer to the negative easy axis e than the positive easy axis E+ near the free magnetic region 422, the magnetic moment The vector 〇 continues to rotate clockwise and is aligned with the negative easy axis E- of the free magnetic region 422. Thus, after the sequence shown in Figure 6, the magnetic moment vector C of the ferromagnetic layer 432 and the ferromagnetic layer Magnetic moment vector D of 434 has been 24 1330844 P51950188TW 23746twf.doc/n

Exchange location. Specifically, the magnetic moment vector c of the ferromagnetic layer 432 has been rotated by 18 〇. Therefore, if the memory unit 4042 has previously "one," stored, and t, then the sequence shown in Figure 6 and the sequence have written a bit ί 1 into the memory unit 4042. If the memory unit 4042 has previously stored a single bit "wide", the sequence of 1〇 and IW shown in Figure 6 has written a one-bit "〇" to the memory unit. 42 in. Similarly, when the two-state trigger memory unit 4〇7 and 4042 are required, the digital current is simultaneously supplied via the memory unit 404l and the write bit line WBL of the class 2 to simultaneously write the memory unit 404〗 and 2. Figure 8 edge 1 write ^ word secret WWLG, write people bit line 0 and write the person on the two for the two-state trigger write memory unit 404〗 and the record body - a series of money. - Generally familiar with this technology, the county resolves the double I, and writes the process of the human memory unit 4G4i and marriage 2, which is not described in detail in this article. + , as in the embodiment of the present invention, in a clock cycle, can be self-contained? Select the memory cell 4 〇 2 to read the data of the two bits 5 to write to the MRAM device 400 for selection, memory, and intraoperative. In other words, the young device ^^ South takes the bandwidth and has a high write bandwidth. , Yes: Medium: The digital current Id is only supplied to the memory unit to be toggled. • Figure 9 wL〇, write bit line WBL0, and write bit 25 1330844 P51950188TW 23746twf.doc/n line WBL1 The two-state trigger writes a series of signals that are only one of the memory units 4042. Specifically, at time h, the positive bit current ID 〇 and the positive bit current ID1 are respectively supplied via the write bit lines WBL0 and WBL1; at time, the positive word current Iw is supplied via the write word line WWL0; At time U, ID1 is cut off; at time I; 5, cut off; [w; and at time t6' also cuts ID〇. The clock signal CLK falls at time t7. In comparison with a series of signals shown in Fig. 6, when a series of signals shown in Fig. 9 is applied, the memory unit 4042 is subjected to the same signal and will be triggered by double sorrow. However, the unit number 4041 is subject to different signal sequences and will not be toggled. Fig. 10 (a) to Fig. 1 (e) illustrate the state of the memory unit 404! through the signal sequence shown in Fig. 9. The magnetic moment vectors c and D in the following description of Figs. 1a to 10(e) refer to the magnetic moment vectors C and D of the memory unit 404!. Figure 10 (a) shows the magnetic moment vector c of the ferromagnetic layer 432 and the magnetic moment vector D of the ferromagnetic layer 434 at times t 〇 and h when no word current or digital current is supplied. The magnetic moment vector c is in the direction of the negative easy axis E_ of the free magnetic region 422, and the magnetic moment vector d is in the direction of the positive easy axis E+ of the free magnetic region 422. Fig. 10(b) shows magnetic moment vectors c and D at time t2 when Id〇 is supplied to induce a digital magnetic field HD〇 substantially in the positive y-axis direction. Under the digital magnetic field HD, the magnetic moment vectors c and D rotate clockwise. The magnetic moment vector C is in the direction between the negative X-axis and the positive y-axis. The magnetic moment vector D is in the direction between the positive X-axis and the positive easy axis E+ of the free magnetic region 422. Figure 10 (C) shows when Iw is provided to induce substantially positive X-axis 26 1330844

P51950188TW 23746twf.doc/n The magnetic moment vectors c and D at time h for the upward magnetic field. Therefore, the magnetic moment vectors C and D continue to rotate clockwise. The magnetic moment vector c is close to the positive y-axis and the magnetic moment vector d can cross the positive X-axis. Fig. 10(d) shows the magnetic moment vectors c and D at time, when Iw is cut. Therefore, the magnetic moment vectors c and D rotate counterclockwise and return to the same position as shown in Fig. 10(b). /, Fig. 10(e) shows the magnetic moment vectors C and D at time 丨5 when the IDG is also cut. The magnetic moment vectors C and D are successively rotated counterclockwise and returned to the same position as shown in Fig. 10(a). Therefore, after the sequence of ID0 and Iw shown in FIG. 9, the magnetic moment vector c of the ferromagnetic layer 432 of the memory unit 401 and the magnetic moment vector D of the ferromagnetic layer 434 are maintained at the same position, and the memory The ceremony of the unit has not changed. As with the embodiment of the present invention, the magnetic moment vector A of the ferromagnetic layer 428 and the magnetic moment vector b of the ferromagnetic layer 426 can be adjusted to produce an edge (or spur) of the magnetic field bias Hbias in the free magnetic domain. The magnetic field is such that only the weak magnetic fields Hw and Hd are required to be binary-triggered to the memory unit side. 11 illustrates the necessary magnetic field Hw and % for the two-state trigger write to the memory early bit 404 when there is no magnetic field bias, and the magnetic field bias H_ when the free magnetic region is in the direction of the positive axis E+. It is used for the two-state triggering of the necessary magnetic fields H, w and % of the fresh memory 4G4. When the write bit 404 requires a weaker magnetic field ~ and %, a lower word can be applied: a Can IW and a lower digit current of 1 〇. Therefore, the magnetic field bias Is results in a reduced power cleanup. / ^3· 27 1330844 P51950188TW 23746twf.doc/n Consistent with the third embodiment of the present invention, it is provided to operate the MRAM device when the 5 memory unit 404 of the MRAM device 400 is subjected to a magnetic field bias. Kind of method. The same sequence ' of signals as illustrated in Figure 5 can be applied to read the MRAM device 400. However, in order to write to the MRAM device 400, -/ when the memory cell 402 is under a magnetic field bias, a series of write currents having two bidirectional current-pulses (i.e., current pulses having a negative portion and a positive portion) are applied. Write to the memory cell 4〇2 in a two-state trigger. For example, FIG. 12 shows that the memory unit 4〇4丨 and 4〇42 of the memory cell 402 are in a magnetic field bias in the direction of the positive easy axis E+ of the free magnetic region 422, and the character is written. The line WWL0, the write bit line WBL〇, and the write bit line WBL1 are used to write data to a series of signals in the memory cell. As shown in FIG. 12, the clock signal CLK rises at time t〇. Between the time t 〇 and the time t1, the logic circuit (not shown) reads the data of the memory cell celestial 丨 'will remember the data in the cell 402! and the data to be written into the memory cell 4 〇 2 ι Compare and determine if one or both of the memory units 4〇4ι and 4042 should be toggled. It is assumed that the data of the ► bit to be written to the memory unit 4〇7 is the same as the data of the bit stored in the memory unit 4〇4], and is to be written to the bit in the memory unit 4042. The data is different from the data stored in the memory unit 4042. Therefore, the two-state trigger memory unit 4042, while the two-state trigger memory unit 404!. Then 'at time t2' provides a negative sub-current Iwi via write word line WWL0; at time h 'provides positive digital current iD1 via write bit line WBL1; at time u, Iwi is turned off, and The positive word power %Iw2 is supplied via the write word line WWL0; at time ", the cut is made, and 28 1330844 P51950188TW 23746twf.doc/n provides the negative bit current Id2 via the write bit line WBL1; At t6, 'IW2 is cut off; and at time tv, 1〇2 is also cut off. The clock number clk falls at time ts. After t〇 to ts, the current is not supplied via the write bit line WBL0. Figure 13 (a) to Figure 13 (g) illustrate the process of writing the memory unit 4402 of ^, Idi, Iw2 and Id2 shown in Figure 12. Figure π (a) to Figure 13 (g) The magnetic moment vectors c and D in the following description refer to the magnetic moment vectors C and D of the memory unit 4042. Figure 13 (a) shows that when the word current or digital current is not supplied, at times t0 and & The magnetic moment vector c of the ferromagnetic layer 432 and the magnetic moment vector d of the ferromagnetic layer 434. Due to the HBIAS, the magnetic moment vectors c and D are reversible and respectively rotated Or cross the negative y-axis and the axis. = Figure 13 (b) shows that at time t; 2, the negative word current Iwi is supplied, resulting in a real f-axis in the negative X-axis direction (ie, and also ... 135S) The pre-magnetic field HW1. In other words, HW1 is partially offset by Hbias. Therefore, the magnetic moment vectors C and D are respectively close to the easy axes E and E+. Figure 13 (c) shows that when Im is provided to induce substantially the positive y-axis The magnetic moment vector c and ρ at time h in the direction of the digital magnetic field Hdi. Therefore, the magnetic moment vectors C and D rotate clockwise. The magnetic moment vector c can cross the negative X axis, and the magnetic moment vector D approaches the positive Figure 13 (d) shows the magnetic moment vector at time t4 when Iw2 is turned off and Iw2 is turned on to induce a magnetic field 幵 from 2 in the substantially axial direction, and therefore, the magnetic moment vectors c and D continue Rotate clockwise. The moment C is close to the positive y axis, and the magnetic moment vector D can cross the positive axis. 29 1330844 P51950188TW 23746twf.doc/n Figure 13 (e) shows when I cut off and picks up The digital magnetic field HD2k induced on the negative y-axis and the magnetic moment vector c and the magnetic moment vector C at time t5 are obtained by the 士士士士士+ + ^丄m« D continues to rotate clockwise. The magnetic is over the positive y-axis, and the magnetic moment vector D is close to the negative 7 axis. The more and the moment, the magnetic moment vector C = D at time t6 continues to rotate clockwise. The current magnetic moment vector ί can be crossed over the negative y-axis and close to Fig. 13 (g) shows the magnetic moment vector c = D at time t? when lD2 is cut. Because before time t7, the magnetic moment vector c is closer to the positive easy axis H to "„ vector D is closer to the negative easy axis, so the magnetic moment is in the position close to the positive easy pumping E+ direction, and the magnetic moment vector D is stabilized in the position close to the E_ direction of the negative easy axis. Therefore, after the sequence of the word electric current and the current current shown in Fig. 12, the magnetic moment vector C of the ferromagnetic | 432 and the magnetic moment of the ferromagnetic layer 4M The vector \ has changed position. In particular, the magnetic moment vector C of the ferromagnetic layer has been rotated from a position close to the negative axis to a position close to the positive axis. Therefore, if the memory unit 4042 has previously been a bit The element "〇, stored in it" then the sequence of word current and digital current shown in Figure 12 has written a "1" of a ^ to the memory unit 4〇42; if the memory unit is 4〇 42 A bit "丨" has been previously stored therein, and the sequence of word currents and digit currents shown in FIG. 12 has written a one-bit "〇" into the memory unit 4042. ° Similarly, when a two-state trigger memory unit of 4〇41 and 4〇42 is required,

30 1330844 P51950188TW 23746twf.doc/n The same % is provided via the write bit line WBL of the memory unit 4〇4i and 4〇42 - for the digital current to be simultaneously written to the memory unit 404 and 4042. Figure 14: Drawing a word line WWL0, writing a bit line WBL0, and writing a bit ', a pair of signals for writing a memory unit unit 1 and a memory unit 4042 on the WBL1 . It is now well known to those skilled in the art to understand the process of writing a memory unit 4 〇 41 and 4 〇 42 in a binary state, and therefore this process is not described in detail herein. • In Figure 12, the digital current Im and ID2 are only provided to the έ 忆 体 unit 4 〇 42 to be toggled. However, consistent with the third embodiment of the present invention, the digital current can also be supplied to the memory unit 404 which is not to be toggled. Fig. 15 depicts a series of signals for writing a memory-only unit 4042 for a two-state trigger write on the write bit line WWL, the write bit line WBL, and the write bit line WBL1. Specifically, at time t2, the negative word current ^ is supplied via the write word line WWLG; at time ^, the positive bit current 1DQ is supplied via the =in 兀 line WBL0 and the write bit line WBL 分别, respectively. ^ and positive digit current ID1; at time u, IW1 is turned off, and the positive word current ^2 is supplied via the write word line WWL0; at time t5, _cut = Idi' and via the write bit line WBL1 Negative digit current ID2 is provided; W2 is cut off between day and day; and at time 7 is also cut off 1〇0 and 1〇2. The clock signal CLK falls at time t8. A series of signal comparisons shown in Fig. 15, when a series of signals in Fig. 15 is applied, the memory unit 4〇42 is subjected to the same signal and will be double-triggered. However, the memory unit 4〇4ι is subject to different signal sequences and will not (three) toggle. Fig. 16 (a) to Fig. 16 (4) illustrate the state of the memory unit 40\ which passes through the signal sequence of 1330844 P51950188TW 23746twf.doc/n in Fig. 15. The magnetic moment vectors c and D in the following description of Figs. 16(a) to 16(e) refer to the magnetic moment vectors C and D of the memory unit 404]. Fig. 16(a) depicts the magnetic moment vector c of the ferromagnetic layer 432 at the time t〇 and the magnetic moment 畺D of the ferromagnetic layer 434 when the word current or the digital current is not provided. Due to hbias, the magnetic moment vectors c and D can be rotated counterclockwise and approach or cross the negative x-axis and the positive x-axis, respectively. As shown in Fig. 16(b), at time t2, the negative word current IW1 is supplied, resulting in a word magnetic field HWi substantially in the negative X-axis direction (i.e., at an angle of n5Q from the H function). In other words, Hwi is partially offset by Hbias. Therefore, the magnetic moment vectors C and D rotate clockwise and approach or pass the easy axis and E+, respectively. Fig. 16(c) shows magnetic moment vectors C and D at time t3 when Id〇 is supplied to induce a digital magnetic field HD〇 substantially in the positive y-axis direction. Therefore, the magnetic moment rotates clockwise to ic and D. The magnetic moment vector 匚 can cross the negative X axis, and the magnetic moment vector D is close to the positive 乂 axis. Figure 6 (d) shows the magnetic moment vector c at time U and thus the magnetic moment vectors C and D when the Iwi is turned off and Iw2 is turned on to induce the word magnetic field Hwz in the positive X-axis direction. clockwise rotation. The magnetic moment vector c is close to the positive y-axis and the magnetic moment vector D can cross the positive 乂 axis. Fig. 16(e) shows the magnetic moment vector c and the D moment vector c and D counterclockwise rotation at time k when Iw2 is cut. The magnetic moment vector c is rotated back toward the negative X-axis, and the magnetic moment vector D is rotated back toward the positive X-axis and can cross the positive X-axis. Therefore, the magnetic moment vector c is closer to the negative easy axis, and the magnetic moment vector 32 Hr 1330844

P51950188TW 23746twf.doc/n D is closer to the positive axis E+. At time ty, the ID 切断 is cut off. Since the moment vector C is closer to the negative easy axis E_ direction before the time h, and the magnetic moment vector D is closer to the positive easy axis direction, the magnetic moment vectors C and D are returned to The respective original positions of + as shown in Figure 16 (a). Therefore, after the sequence of 2Iwi, Id〇, and Iwz as shown in FIG. 15, the magnetic moment vector c of the ferromagnetic layer 432 of the memory unit 404, and the magnetic moment vector D of the ferromagnetic layer 434 are maintained at the same position, And the memory unit 404! has not changed state. & As an embodiment of the present invention, one or more of the memory cells 4 〇 2 can be simultaneously selected. For example, one or more of the memory cells 4 〇 2 can be read by starting a read word line rw1 and a read bit line RBL; the start-write character line WWL and the plurality of writers can be read. The field job ^ is written to more than one memory cell 402. $ Reads the selected signal, such as the signal shown in Figure 5, at the same time = all selected memory cells. In order to write to the somatic technique, such as Fig. 6, Fig. 8, Fig. 9, Fig. 12, Fig. 14 will be interpreted as follows: "Because it is suitable: the number is simultaneously applied to all selected G cells 402. Because in the -clock cycle;: two bits of data or the data of two bits - cell: 02 towel? In the case of the self-device in each clock cycle, the number of shell-shaped ridges read or written by the L-body 402 into the MRAM ' is twice the number of ah. Therefore, 'the actual invention _-乍 33 1330844 P51950188TW 23746twf.doc/n The method of the MRAM device 400 not only provides a high read frequency 'I of MRAM 4' but also provides a high write bandwidth of the MRAM 400. 5 MRAM 400, as in the embodiment of the present invention, also includes an appropriate interface for enabling high read and write bandwidths to be used to access external devices of MRAM 400. The memory device communicates with the external device via a data sink comprising a plurality of data lines and control signal lines. The number of data lines in the data bus is equal to the number of bits of data that the memory device can simultaneously provide or receive. This number is also referred to as the word size. Because of each of the conventional memory devices. It has been recalled that the somatic cell stores only one bit of data, so the size of the conventional memory device is equal to the number of memory cells that can be selected at the same time. For example, if the = memory is set so that the 8 memory cells are simultaneously selected, the memory device is connected to the data bus containing 8 data lines for parallel transmission and receiving 8 bits of data. 7, . . . , and as discussed above, MRam as in embodiments of the present invention has a high read bandwidth and a high write bandwidth. In the -state, when i is = MRAM 400, the MRAM device 400 can be connected to a number of data lines that are twice the number of memory banks selected when:: Busbars: for example, if simultaneously selected Eight memory cells 402, xu ^ 3 16 lean line data bus is connected to the MRAM device 400 and send 16 bits of data. As a result, the MRAM device 400 has doubled the size of the 8 memory cells through the simultaneous selection of the conventional MRAM. In another sad case, when accessing the MRAM 400, the MRAM is loaded with 34 1330844 P51950188TW 23746twf.doc/n. See Figure 17, when the shift register 452iCL signal rises from "〇" to ", it will shift. The output q〇 of the register 452 is set to D〇; when the CL signal of the shift register 454 rises from “〇, to ^, the output Q1 of the shift register 45^ is set to D1. The clock signal CLK is supplied to the shift register = 52 as its CL signal. A clock register 454 for the limb phase of the clock signal CLK which is inverted by the inverter 458 is supplied as its CL signal. The multiplexer 456 receives Q〇 and (1) acts as 'in' and outputs one of Q0 and Q1 in accordance with the selection (SL) signal. :3;!S "L is "1,", when the output of the multiplexer 456 is CLK^ is supplied to the Xixiji Temple output (2) as D〇UT. The 0 pulse signal CLK is supplied to the multiplexer 456 as its SL signal. In the case of = two fields, the output portion 450 of the 7^1/0 circuit of Fig. 17 and the two demonstrations of the two rows of the poor material row are considered as examples. When the suspicion domain CLK is loaded at the beginning of the first week, the shifting field moves the DO out as the output Q〇-=week shift out as the wheel. Therefore, the ... number is in phase 1 and the copper period is τ after the first job. = period is the period of the previous half cycle output Q0 as D〇UT, =:: period during the second half cycle of the cycle output Qi as D0UT * period of the cycle is raining / / therefore, increase in one clock cycle Two squatting assets and D1. The same process is repeated in the second cycle = 36 1330844 P51950188TW 23746twf.doc/a and subsequent clock cycles. As will be appreciated by those skilled in the art, the MRAM 400 (the input portion of the ^0 circuit can be similarly constructed to enable - parallelization of the two bits of the serial transmission in the clock cycle (4). Therefore, this transformation tree Shown in the text or described herein by rearranging the data of two bits into a queue to rearrange the transmissions in one clock cycle and rearrange the data of the two bits received in one clock cycle so that Parallel transmission, the I/O circuit of the MRAM device 4 (8) according to the embodiment of the present invention can achieve a data transfer rate per line which is twice the data rate per line of the device. ~ By increasing the size of the word or increasing the data transmission per line The rate can be fully utilized for the high read and write bandwidth of the MRAM device 4 according to an embodiment of the present invention. FIG. 4A illustrates that each memory cell 4〇2 of the MRAM device 400 includes two delta-resonants. Unit 404. However, consistent with embodiments of the present invention, each memory cell of an MRAM device can include more than two memory units. Figure 19 illustrates an MRAM device 500 consistent with a fourth embodiment of the present invention. 500 includes an array of memory cells 502, painted The memory cells are 502 丨, 5022, 5023, 5024. Each memory cell 502 corresponds to a read bit line RBL, a read word line RWL, a write word line WWL, and three write bits. Line wbL. Figure 19 illustrates that each memory cell 502 includes three memory units 504 connected in parallel between the transistor 506 and the corresponding read bit line rbl (i.e., memory units 504^5042- and 5043). Wherein the gate of the transistor 506 is connected to the corresponding read character 37 1330844 P51950188TW 23746twf.doc/n line RWL. Each memory unit 504 corresponds to one of the three write bit lines WBL. It is shown that the memory cells 502 and 5022 correspond to the first read bit line RBL0, the first write bit line WBL0, the second write bit line WBL1, and the third write bit line WBL2; The cells 5023 and 5024 correspond to the second read bit line RBL1, the fourth write bit line WBL3, the fifth write bit line WBL4, and the sixth write bit line WBL5; the memory cells 502 and 5023 correspond to The first read word line RWL0 and the first write word line WWL0; and the memory cells 5〇22 and 5024 correspond to the second read The line RWL1 and the second write word line WWL1. The sense amplifier 508 is lightly connected to each of the read bit lines RBL via the selection transistor 510 to detect the one selected by one of the memory cells 5〇2. Current. As in the fourth embodiment of the present invention, the memory units 504^5042 and 5043 in each memory cell 502 of the MRAM device 500 are fabricated such that the resistance of each of the memory cells 502 has a corresponding memory. Different values for different states of the body cell 502. In other words, 8 parallel resistors Rlmax//R2max//R3max, Rimax//R2max//R3min, Rimax//R2min//R3max, Rlmax"R2min"R3min, Rimin//R2max"R3max, Rimin//R2max"R3min, Rlmin//R2inin//R3max, R]min//R2min//R3min all have different values, where Rlmax is the high resistance of the memory unit 504!, Rlmin is the memory unit 5〇4! The low resistance 'R2max is the memory The high resistance of the body unit 5042, R2min is the low resistance of the memory unit 5042, R3max is the high resistance of the memory unit 5〇43 and R3min is the low resistance of the memory unit 5〇43. Therefore, three bits of data can be stored in each memory cell 502 and can be read simultaneously. Special 38 1330844 1330844

P51950188TW 23746twf.doc/n In other words, the sense amplifier 508 compares the detected current through the selected memory cell 502 with seven intermediate reference current values Ref 1 Ref7 (Refi Ref7 corresponds to eight parallel resistors). The reference resistance value between) is found, and one of the eight parallel resistances closest to the selected memory cell 502 is found. Once the corresponding parallel resistance is found, that is, the state of the memory unit 504 of the selected memory cell 5〇2 is determined, and the data of the three bits simultaneously outputting DO, D1, and D2 is the same as the fourth embodiment of the present invention. The different resistance values of the memory units 5〇4ι, 5〇42, and 5043 can be achieved by, for example, shaping each memory unit to have different physical sizes. The size of the entity can be achieved by adjusting the cross-sectional area of the 6 memory units in the plane that is substantially perpendicular to the flow of current when the memory cell 502 is read. For example, the memory unit can be manufactured to have a larger solid area than the memory fresh position 5G42, and the memory unit 5042 can be made to have a larger physical cross-section than the unit. The larger the real gambling cross-sectional area, the lower the magnetic power. More specific ί ΐ 实 实 实 实 实 实 实 实 实 实 记 记 记 记 记 记 记 记 记

The sufficiency unit 5042 will have an age-old female Cheng Xue Q 2 liver eight with #乂 large magnetoresistance, and the memory unit 5〇43 will have the maximum magnetoresistance. In order to write the selected memory cell 5〇2, first read the memory unit 504 and the bedding stored in the selected memorandum (10) (four) way (not shown), and write it to be written. Entering the record I# set your mountain ^ 骽 骽 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 504 Or "remaining trigger,," "Secondary" does not perform the write operation. Otherwise, change d to trigger the state of the miscellaneous unit. If a two-state trigger is required, 39 1330844 P51950188TW 23746twf.doc/n, if more than one memory unit so# of the memory cell 502 is selected, the write current can be simultaneously supplied to the corresponding write word line and correspondingly The write bit line of the memory unit to be toggled. Those skilled in the art will be aware of procedures for reading and writing selected memory cells 502' and such procedures are not described in detail herein. When the MRAM 500 is accessed, the MRAM device 5 can be connected to the = bus, which contains a plurality of data lines having three times the number of simultaneously selected memory cells 5 〇 2 . For example, if 8 memory cells 5 〇 2 are selected at the same time, the data bus containing 24 data lines can be connected to the mram device 5 〇 G read and send 24 bits of data. Therefore, the size of the device 5GG is three times the size of a conventional MRAM device that selects eight memory cells when it is off. Alternatively, when accessing the MRAM 5, the Mram device 5 (9) may be j to include a number equal to the number of simultaneously selected memory cells 5 () 2 = line. For example, if _ ring 8 memory cells, i shell material bus bar contains only 8 data lines. However, three bits should be installed by: each of the lines and every clock cycle transmitted to the way. For example, the 1/0 circuit may have a data output portion of three bits read by the memory cell 502 of the array so that the first bit is adjusted in the first one of the clock cycles. The second bit is sent in the second quarter of the clock cycle, and the third bit is transmitted in the third quarter of the clock cycle. The I/G circuit contains the material (4) to be written into the battery, selects the memory cell 502 $ three bits of data 1330844 P51950188TW 23746twf.doc/n 兀 is paralleled to the write circuit for simultaneous writing to the selected record Indignation

* The input portion of the memory unit 504 of 5〇2. Therefore, although the MRAM • 500 word size has not changed, the data transfer rate per line has tripled. - As in the fourth embodiment of the invention, the I/C) circuit may comprise any suitable logic circuit for this dual purpose. For example, FIG. 20 illustrates an example of the output portion 550 of the I/O circuit of the MRAM device 500 in accordance with the fourth embodiment of the present invention. As shown in FIG. 20, the output portion 55A includes three shift registers 552, 554, and 556, and a multiplexer 558. The shift registers 552, 554, and 556 respectively receive the data outputs d〇, di from the sense amplifier 508 at f D2, and output the same data on the rising edges of the clock signal (CL) as Q0, Q1, and Q2, respectively. . Two external clock signals clk 1 and CLK2 are provided to generate a clock signal for shifting registers 552, 554, and 556, where CLK2 is twice as fast as CLK1. Specifically, the clock signal of the shift register 552 is AND (CLK1, CLK2), the clock signal of the shift register 554 is AND (CLK1, sinking), and the time of the temporary storage is 556. The pulse signal is aND (clki, CLK2), wherein the river stone is followed by > and 0^2 by CLK1 and CLK2 which are inverted by inverters 56 and 562, respectively. Therefore, when AND(CLK1, CLK2) rises, shift register 552 shifts 00 out as Q0; when AND(CLK1, MN) rises, shift register 554 shifts D1 out as Q1; and when AND(( When CLK, CLK2) rises, shift register 556 shifts D2 out as Q2. The multiplexer 558 receives Q〇, Q1, and Q2 as inputs, and outputs one of Q0, Q1, and Q2 based on the two selection signals SL1 and SL2. In particular, when both SL1 and SL2 are 丫, the output Q〇 is 1330844. P51950188TW 23746twf.doc/n is DOUT 'slave SL1 is “i” and su is “〇, when output qi is DOUT, and when SL1 It is “〇,” and su is “Γ as DOUT. When both SL1 and SL2 are “〇,, the output DOUT is set to float. °° Figure 21 shows the two clock cycles of the process of dividing D〇, 、, m into the train by the output section 55〇, for example, the first cycle and the second cycle. Those skilled in the art should be able to understand the three-digit data.

The process is therefore not described in detail in this article. The input portion of the MRAM 500 I/O Snow <? Female && X, % Road can be similarly constructed, and is not shown in the figures or described herein. Therefore, according to the fourth embodiment of the present invention, the memory can be simultaneously selected when the number of sub-sequences can be increased by a sub-segmental _ MRAM device can be increased to j or doubled. Multiple bit data of three times the number of body cells. ,

Similarly, as in the embodiment of the present invention, the MRAM device can have four or more memory units in a memory cell in the basin;; increase and increase the size of the word or increase each The line data transfer rate is communicated to the external device by the > material bus. One of the above descriptions of the embodiments of the present invention assumes, for convenience, that sub-u or digital currents are provided in a manner such that the magnetic moment vectors C and D rotate in a certain direction. However, it should be understood that the magnetic moment vectors C and D can be rotated in the cis = counterclockwise direction. For example, in contrast to FIG. 6 and FIG. 5, and in accordance with the second embodiment of the present invention, the memory unit 4〇42 of the memory cell 402 is written for the 42 1330844 binary state trigger. The positive word current can be supplied via the write word line WWL0 between time, t2 and time %

Iw ' and may be provided between the time h and the time h via the write bit line wbli - for the positive bit current Id. Therefore, as shown in Figs. 7(a) to 7(e): In the clockwise rotation, the magnetic moment vectors C and D will rotate counterclockwise. For another example, compared with a series of signals shown in FIG. 12, and also in accordance with the third embodiment of the present invention, in order to write the memory cell 4〇2ι, / hidden body unit 4042, Negative bit current is provided between time t2 and time U: a positive bit current can be provided between time t4 and time t6' can provide a positive word current between time ^ and 1 and can be in time & Negative word current is provided between. Therefore, in contrast to the clockwise rotation of Figs. 13(a) to 13(g); the magnetic moment vectors C and D will rotate counterclockwise. In the above description, it is assumed that the easy axis E+ and E are at an angle of about 45^ with the χ axis and f. However, it should be understood that the easy axis does not have to be at a particular angle to the axis of the x-axis but may be at any angle to the x or y axis. Correspondingly, according to the second embodiment of the present invention, | and the digit line are at an arbitrary angle, the memory unit 404 is used, wherein the method of writing the •• 也L is used to write the έ 忆 体 unit 4 〇 4 or 5 〇 4 . For example, the 'easy axis and the read word line of the free magnetic area

43 13 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The embodiments of the present invention are described in the accompanying drawings, and are in the ,

FIG. 1 illustrates a memory cell of a conventional MRAM device. 2 depicts a conventional high density MRAM device. Figure 3A illustrates a series of signals for reading the memory cells of the high density MRAM device of Figure 2. Figure 3B illustrates a series of signals for writing the memory cells of the high density MRAM device of Figure 2. 4A illustrates an MRAM device in accordance with a first embodiment of the present invention.

Fig. 4B is a cross-sectional view showing the memory unit of the MRAM device shown in Fig. 4A. Fig. 4C is a plan view showing the magnetic moment in the memory unit of the PCT apparatus shown in Fig. 4A. Figure 5 illustrates a series of signals for reading the memory cells of the MRAM device shown in Figure 4A. Figure 6 1 shows a series of signals for writing memory cells of the MRAM device not shown in Figure 4A in accordance with a second embodiment of the present invention. Figures 7(a) through 7(e) illustrate the process of one of the series of signal writes shown in Figure 6 1330844 P51950188TW 23746twf.doc/n into the memory unit of the MRAM device shown in Figure 4A. Figure 8 illustrates a series of signals for writing a plurality of memory cells of a memory cell of the iMRAM device shown in Figure 4A. Figure 9 illustrates a series of signals used to write the memory units of the iMRAM device shown in Figure 48. Fig. 10 (a) to Fig. 10 (e) illustrate the state of the memory unit subjected to the series of signals shown in Fig. 9. Figure 11 illustrates the effect of magnetic field bias on the magnetic field used to write the memory unit of the MRAM device shown in Figure 4A. Figure 12 is a diagram showing a series of signals for writing a memory cell of the MRAM device shown in Figure 4A when the MRAM device is under a magnetic field bias in accordance with a third embodiment of the present invention. Figures 13(a) through 13(g) illustrate the process of writing a series of signals shown in Figure 12 to the memory unit of the MRAM device shown in Figure 4A. The figure shows a series of signals for writing the plurality of s replies of the mram device shown in Fig. 4A. Figure 15 is a diagram showing a series of signals for writing the memory unit of the MRAM device shown in Figure 4A in accordance with a third embodiment of the present invention. 16(a) to 16(e) illustrate the state of the memory unit subjected to the series of signals shown in Fig. 15. The figure depicts a portion of an exemplary 1/〇 circuit of the MRAM device shown in Figure 4A. Figure 18 illustrates an example of two clock cycles of the process performed by the portion of the I/O circuit shown in Figure 17. D: {: Λ 45 1330844 P51950188 TW 23746 tw doc / n Figure 19 depicts an MRAM device not according to the fourth embodiment of the present invention. Figure 20 is a diagram showing the I/O circuit of the MRAM device of the garment-sharing example shown in Figure 19. Figure 21 illustrates two exemplary clock cycles by the process of 1/〇 shown in Figure 20. [Parts of the main component symbol description] 100: MRAM device 102: memory cell 102], 1〇22: memory unit 104: write bit line 106: write word line 108: fixed magnetic area 110: Free magnetic region 112: tunneling barriers 114, 116. Ferromagnetic layer 118: antiferromagnetic coupling spacer layer 120, 122: ferromagnetic layer 124: antiferromagnetic coupling spacer layer 126: antiferromagnetic pinned layer 128: Buffer layer 130: bottom electrode 132, 136: dielectric layer 134: top electrode 138 = transistor 46 1330844 P51950188TW 23746twf.doc / n 140: sense amplifier 200: MRAM device / MRAM 202, 202 wide 2024: memory cell 204 :Crystal

400: MRAM device/MRAM 402, 402 wide 4024: memory cell 4〇4, 404!, 4042: memory unit 406: transistor 408: sense amplifier 410: select transistor 420. fixed magnetic region 422: free magnetic Region 424: tunneling barriers 426, 428: ferromagnetic layer 430: antiferromagnetic coupling spacer layers 432, 434: ferromagnetic layer 436: antiferromagnetic coupling spacer layer 438: antiferromagnetic pinned layer 440: buffer layer 442: bottom electrode 444, 448: dielectric layer 446: top electrode 450: output portion 452, 454: shift register 47 1330844 P51950188TW 23746twf.doc/n 456: multiplexer 458: inverter

500 : MRAM device / MRAM 502, 502!, 5022, 5023, 5024: memory cells 504, 50^, 5042, 5043: memory unit 506 transistor 508 sense amplifier 510 select transistor 550 output portion 552, 554, 556: Shift register 558: multiplexer 560, 562: inverter

48

Claims (1)

1330844 P51950188TW 23746twf.doc/n The third memory unit has a third cross-sectional area; wherein each of the first cross-sectional area and the second cross-sectional area is greater than the third cross-sectional area, And wherein the third cross-sectional area corresponds to a plane substantially perpendicular to a third read current.