1330812 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種操控系統，特別是有關於一種快速操控系統，其 有效提升操控系統之工作效率，並提升操控系統之穩定性。 【先前技術】 習知之快速操控系統(Rea卜time System)，如通訊協定處理器、數位 訊號處理器等應用，普遍呈現軟硬體系統設計複雜、系統對於外界緊急事 件之反應時間過長、執行穩定度不符合使用者需求與強韌度不佳以及系 統整合困難等缺點。當反應速度為操控系統必要之關鍵性考量項目時如 何保證操控系統具備快速反應的能力，已成為工程師首先面臨需要解決之 課題。 、 傳統快速操控系統之主程式與插斷服務程式之運作方式，在主程式完 成初始設雜，即等待_各插斷需求（Internjpt Request，_的插斷 服務程式（Interrupt Service Routine, ISR)執行，整個中央處理器的主 要負載為最高優先權的出現頻率最高的定時插斷，譬如WI_WSi|5對應卿 之TIMER1 ;較低優先權的出現頻率較底的定時插斷，譬如WIN])〇ws中對應 IRQ8之TIMER2，以及其他相關介面插斷需求的ISR，其中當中央處理器開 始執行ISR時’中央處理器會強制在ISR之内部參數設定允許插斷位元為 1，以允許優先權較高之插斷需求搶先執行其ISR。 插斷需求的例行處理之效能是藉由插斷服務程式ISR來處理各種不同 之插斷事件，其改善措施如以軟體方式處理時，有三種方式，即：串接式 IS歸列法、具優先次序表之ISR指示表以及無優先次序表之ISR指示表。 若採用硬體方式處理呼叫ISR時，則有⑴用於傳統之插斷控制器之簡便 法；（2)具兩條插斷需求輸人控制線設計法：—般插斷需求（inter邮 Request，IRQ)輸入端與優先插斷需求(_盼咖坑_如，^①輸 入端的中央處理器’其中FIQ用於關繼之優先插斷需求，❼IRQ則用於 5 =性插«求。錢⑶料賊理時社快速迦斷控繼，當有插斷 ^求發生時’快速型插斷控彻將FIQ之職與相對應_之初始位址同 時傳送至中央處理器，而提升操控系統之作業時效。 快速操控系統的反應時間受到四種因素影響，即：硬體架構之效能、 ^性作Μ統核α作難之處觀能、靖處理效誠及資源管理效 =其中㈣⑽«統已是各鶴控純可重複使狀碰元件，但操 控系統為了使用即時性作業系統，卻會導致操控系統之設計複雜度增加， =而降低處理魏。尤其，_性即時f料之輸人處理方式與處理時間會 直接影響難祕對事件反應之贿。辅合使用者之需求，如何提升快 速操控系統之决速反應㉟力，是快速操控系統設計工程師亟待解決之課題。 因此’本發明針對上述之問勒提供—種快速操齡統，其讓即時作 業系統得赠速而準確贼成健料，達絲度狱性、餘性 性之故果。 【發明内容】1330812 IX. Description of the Invention: [Technical Field] The present invention relates to a control system, and more particularly to a quick control system, which effectively improves the working efficiency of the control system and improves the stability of the control system. [Prior Art] Conventional fast control system (Rea time system), such as communication protocol processor, digital signal processor and other applications, generally presents complex software and hardware system design, system response to external emergency events is too long, execution Stability does not meet the shortcomings of user needs and poor toughness and system integration difficulties. When the reaction speed is the key consideration for manipulating the system, how to ensure that the control system has the ability to respond quickly has become the first problem that engineers need to solve. The main program of the traditional fast control system and the operation mode of the interrupt service program are completed in the main program, that is, waiting for each interrupt request (Internjpt Request, _ Interrupt Service Routine (ISR) execution The main load of the entire central processing unit is the highest priority frequency insertion interrupt, such as WI_WSi|5 corresponding to TIMER1; lower priority frequency is lower than the timing interrupt, such as WIN]) 〇ws The ISR corresponding to IRQ8 of IRQ8, and other relevant interface interruption requirements, when the central processor starts to perform ISR, the central processor will force the internal parameter setting of the ISR to allow the interrupt bit to be 1 to allow priority. High interrupt demand is the first to implement its ISR. The performance of routine processing of interrupting requirements is to handle various interrupt events by interpolating the service program ISR. When the improvement measures are handled in software, there are three ways, namely: serial IS issuance, An ISR indicator with a prioritization table and an ISR indicator with no prioritization table. If the call ISR is handled in a hardware manner, there are (1) a simple method for the traditional interrupt controller; (2) a two-interruption input control line design method: the general interrupt request (inter-mail Request) , IRQ) input and priority interrupt requirements (_ 盼 坑 _ _, ^1 input terminal of the central processor ' where FIQ is used to close the priority of the interrupt demand, ❼ IRQ is used for 5 = sexual interpolation «Q. (3) The thief is in a state of rapid control, and when there is an interruption, the quick-breaking control will transmit the FIQ job and the corresponding initial address to the central processor at the same time, and improve the operation of the control system. The response time of the fast-control system is affected by four factors, namely: the performance of the hardware architecture, the performance of the Μ 核 核 α α 、 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 靖 = = = = = = = = = = = = = = = Each crane control can repeat the component, but the control system will increase the design complexity of the control system in order to use the immediacy operation system, and reduce the processing of Wei. In particular, the _ sexual instant f material input processing method And processing time will directly affect the difficult thing In response to the needs of users, how to improve the speed response of the fast control system 35 is a problem that the design of the rapid control system needs to be solved. Therefore, the present invention provides a fast working age for the above-mentioned problem. System, which allows the real-time operating system to receive the speed and accuracy of the thief into a healthy material, Darcy's prisoner, the nature of the remaining nature. [Summary]
本發明之主要目的在於提供—觀絲㈣統，具触速反應處理插 斷事件之能力，並迅速掌_舰_事件之纽_，纽縮短插斷事 件之反應時間，提升系統之運作效能。 本發明之-人-目的，在提供—種快速操控系統，其設置快速準樓而有 效的核心线晶片轉，㈣擇配置各式快速操齡統可加速快速操控 系統的反應時效。 本發明之另-目的’在提供一種快速操控系統採用模組化的設計， 簡化系u之複雜度，藉以縮短系關發時程、降低開發成本、提高產 品可靠度以賴化健祕作餘序。離麵雜，達雜速反應，巨 幅提升系統性能。 …本發明為-種快逮操控祕，其提供接收插斷事倾對狀插斷需求訊 號後’快速掌錄斷事狀處理賴，並雜_事狀優先順序決定對 6 應之減贿程狀齡敎，以财處裡财贿料， 控系統-旦接㈣對麵雛靖事件之優先_絲訊贿即2 關鍵性插斷事件，糾，本發批料魅錢更可迅賴關外處I 件’以提升快速域核之反應效^本㈣之電路藉由採賴組 計’以簡化系統設計的複雜度’運用高逮中央處理器提升運算處理迷度， 以及運用資源雜技術達成處理複_統之能力，而提昇整統性能， 巨幅縮關行(Overhead)軟體處理作料聰體處理作業時間。 【實施方式】 茲為使貴審查委員對本發明之結構特徵及所達成之功效有更進一步 之瞭解與賴，讀佳之㈣例及配合詳細之制，如後： 快速操控系統的廣泛應用，尤其是嵌入式操控系統，為推動近代科技 自動化控餘祕紐展之肋力，具魏進__速率，提升電腦中 央處理II的齡棘速度，賊道存特面之可料化，降低 等功能》 快速操控系統之即時作業系統的處理項目包含：工作排程、工作控制 權交換、插斷處理、通訊通道處理與例外處理。其中工作排程之處理效能 與其採用之運算法則有關，工作排程之常用運算法則，如：出現頻率高低 排程(Rate Monotonic，RT)法則、最早到達時限優先(EarUest DeadUne ?1时，£0?)法則、最少出現優先_1_11^作1；<卜此明法則等動 態排程(Dy_ic Scheduling)法則等，各有其優缺點。至於較先進之排序 法則’如最緊急優先(Maxi_ Urgency First，》)法則，則融合上述各 法則優點之集大成，但處理複雜度與成本相對較高。 基本上’工作控制權交換之效能與中央處理器之硬體架财關，不同 的介面與中央處理器結構與處理軟體之效能息息相關即：推出機制(?她 mechanism)、登錄器窗口（Register wind〇w)、快速記憶機制（^油1呢 mechanisnO與多管道執行架構(pipelines啦阶奶㈣等技術。插斷處 1330812 理之效能是藉由插斷服務程式ISR來處理各種不同之插斷事件，一般插斷 事件之處理程序為：步驟㈠由插斷控㈣決定事件聽次序；步驟(二) 插斷中央處理器執行服務；步驟(三)作業系統決定呼叫相對應之ISR :步驟 (四)執行被呼叫之ISR ;步驟(五)事件完成插斷服務。其中步驟㈠與㈡ 僅能由硬觀善，步驟⑻與(五)觀由性能較佳之ISR運算法則改善。 步觀二)之改善措施如以軟體方式處理時有三種方式即：串接式脱 排列法、具優先次序表之ISR指示表(p〇inter)以及無優先次序表之ISR指 示表。The main object of the present invention is to provide a bird's-eye (four) system with the ability to handle the insertion event with a touch-speed response, and to quickly shorten the reaction time of the insertion event and improve the operational efficiency of the system. The human-purpose object of the present invention is to provide a rapid control system that sets a fast quasi-floor and effective core line wafer turn, and (4) selects various fast-moving age systems to accelerate the response time of the fast control system. The other object of the present invention is to provide a rapid control system with a modular design, which simplifies the complexity of the system, thereby shortening the timing of the system, reducing the development cost, and improving the reliability of the product. sequence. Off-surface miscellaneous, up to complex reaction, greatly improving system performance. ...the invention is a kind of fast catching control secret, which provides a fast palm recording and interrupting demand signal after receiving the insertion and insertion, and the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Age-old, wealthy bribes, control system - Dan (4) Opposite the incident of the Qijing incident _ silk bribery 2 key interruption events, correct, this batch of enchanting money can be more quickly I piece 'to improve the response of the fast domain core ^ (4) the circuit by the mining group to 'simplify the complexity of the system design' using high-crank central processing unit to improve the processing processing, and the use of resource hybrid technology to achieve processing The ability to re-organize the system, and improve the performance of the overall system, the huge reduction of the line (Overhead) software processing material processing time. [Embodiment] In order to make the reviewer have a better understanding of the structural features and the effects achieved by the reviewer, read the (4) case and the detailed system, such as: the wide application of the fast control system, especially The embedded control system is to promote the rib strength of the modern technology automation control secrets exhibition, with Wei Jin __ rate, improve the speed of the computer central processing II, the thief road saves the special material, lowers and other functions. The processing items of the real-time operating system of the quick-control system include: work scheduling, work control exchange, interrupt processing, communication channel processing, and exception processing. The processing efficiency of the work schedule is related to the algorithm used. The common algorithms for work scheduling, such as the Rate Monotonic (RT) rule and the earliest arrival time priority (EarUest DeadUne?1, £0) ?) The law, the least occurrence of priority _1_11 ^ for 1; < This law and other dynamic scheduling (Dy_ic Scheduling) rules, etc., each have its advantages and disadvantages. As for the more advanced sorting rule 'Maxi_ Urgency First', the advantages of the above rules are combined, but the processing complexity and cost are relatively high. Basically, the performance of the work control exchange and the hardware of the central processor, the different interface and the structure of the central processor and the processing software are closely related: the launch mechanism (? her mechanism), the register window (Register wind 〇 w), fast memory mechanism (^ oil 1 mechanisnO and multi-pipe execution architecture (pipelines milk (four) and other technologies. Interrupt 1330812 performance is to intervene the service program ISR to handle a variety of different interrupt events The general interrupting event processing procedure is: step (1) determining the event listening order by inserting and disconnecting control (4); step (2) interrupting the central processor to execute the service; and step (3) operating system determining the corresponding ISR of the call: step (four Perform the called ISR; step (5) event completion interrupt service. Steps (1) and (2) can only be improved by hard view, steps (8) and (5) are improved by better performance ISR algorithm. Step 2) There are three ways to improve the software, such as the serial de-arrangement method, the ISR indicator table with the priority list, and the ISR indicator table without the priority list.
接上述’右採用硬體方式處理呼叫脱時則有⑴簡便法用於傳統之 插斷f制s，⑵具兩脑斷需求輸讀鱗設計法 >般饋需求(卿 輸入知與&速優先插斷需求(⑽)輸人端的巾央處理器，其中HQ用於關鍵 陡决速優先插斷㈤求，巾⑽則用於—般性插斷需求^以及⑶零例行處理 時間，快速優先插斷控制H ’該快紐先_控綱具綱時提供插斷需 求編號與相對應之賊插斷服務程式（驗时町邮Service R〇utine， _)之初始位址至中央處理器之功能。當有__插斷事件發生，而觸發該 快速優先插，控制器之一對應之插斷控制單元發送一對應之插㈣求訊號 中央處理H時’將讓巾央處理器得以即時依據執行目前優先權最高之優 先插斷服雜式卿’職㈣提昇作業反應時效。 發明採用「零例行處理時間之快速型插斷控制器」，提供快速反應之 控錢及其紐’ _是錢__胁快賴齡狀作業程序 ^裝置，有效縮短快速操控系統反應時間，快速而料的達成即時反應任 二因而提升系統之卫作效益。讓快速準確的程序，或至高度穩定性 韌性與可靠性之系統性能。 明參閱第-圖’其為本發明之一實施例之快速操控系統之方塊圖。如 本發明之即時作業系統核心1〇，其包含—工作排程⑽⑹ .、一工作控制權交換(Context Switching)模組12、-資源配置管 rce Allocation Management)模組 13、一插斷處理模組 μ、一通 8 訊通道處理模組15與-例外處理模組16。卫作排程(】Qbseheduling)模組 U依據插斷需求訊號之接收順序指派對應插斷服務程式之作業排程後，立 即由工作控制權交換(c〇ntext Switching)模組12依據插斷服務程式之優 先順序修改該作業排程，用以即時處理最高優先權之工作任務。工作控制 2交換模組12麟峨服務程紅肢權純順序修改齡籍程為最適 當之作業排程之後’插斷處理驗14依據更新狀作㈣程執行插斷服務 程式，通訊通道處理模組15利用快速資訊傳輸匯流道處理Ap間（多重通訊 管道、信箱、事件排序等）。資源配置管理(Res〇urce A11〇cati〇nManagement) 模組13偵荒資源配置資訊。 承上述，例外處理(Exception Handling)模組16偵測插斷處理模組14 之作業狀態，當插斷處理模組14發生一例外處理事件時，例外處理模組16 立即發送-最高優先㈣需求域至卫作㈣歡賴組12，而驅使插斷 處理模組14立即執行對應之插斷服務程式，以排除例外處理事件，其中例 外處理事件’如插斷處理模組14之運算溢位（GverflQW)<)另外，本發明 之快速操控系統更包含一快速型插斷控制器2〇與一主程式單元31。快速型 插斷控制器20設置-第-優先插斷單元2卜一第二優先插斷單元烈、一 第一一般插斷單元23、一第N個一般插斷單元24、一感測器25、一控制器 26，其中第一優先插斷單元21與第二優先插斷單元四為分別發送一第一 優先插斷需求訊號FIQ1與一第二優先插斷需求訊號FIq2,第一一般插斷需 求23與第N個-般插斷需求24為分別發送-第一一般插斷需求訊號賺 與一第N個-般插斷需求訊號主程式單元31具有一系統呼叫模組 311與一驅動單元312，其中即時作業系統核心10為執行主程式單元31所 包含之一主程式。 另外，第一優先插斷需求FIQ1訊號所對應之即時性插斷需求為驅使即 時作業系統核心10之工作控制權交換模組12修改目前工作排程模組n所 排定之作業排程’讓即時作業系統核心10插斷目前優先權低於對應之即時 第一優先插斷服務程式之執行程式，而接續優先執行第一優先插斷服務程 1330812 式（FISRl) 32 ;第二優先插斷需求FIq2所對應之即時性插斷需求為驅使 即時作業系統核心10之工作控制權交換模組12修改目前之作業排程，讓 即時作業系統核心10插斷目前優先權低於第二優先插斷需求FIq2之執行 程式，而接續優先執行第二優先插斷服務程式（FISR2) 33。 又，當工作排程模組11依據插斷控制器2〇所發送之插斷需求訊號， 而排定之作諸程包含對應_即贼先插斷需求織之即時優先插斷服務 程式時’工作控制權交換模組12即比較該即時優先插斷服務程式與插斷處 理模組14目前執行之插斷服務程式的優先權，並依據比較結果修改該作業 鲁排程，而讓插斷處理模組Η執行優先權高之插斷服務程式，若該即時優先 插斷服務喊之優細冑，職輯理模組14猜該即時優^^服務程 式’若插斷處理模組14目前執行之插斷服務程式的優先權高，則插斷處理 模組14繼續執行目前之插斷服務程式。且，當工作排程模組u依據插斷 控制器20所發送之插斷需求訊號所排定之作業排程中，而該作業排程包含 對應至少一即時優先插斷需求訊號之至少一即時優先插斷服務程式與對應 至少 般插斷需求訊號之至少--般插斷服務程式時，工作控制權交換 模組12即先依據該即時優先插斷需求訊號修改該作業排程，再依據該一般 插斷需求訊號修改該作業排程，而讓插斷處理模組14先執行該優先插斷服 φ 務程式（FISR1，FISR2)，再執行該一般插斷服務程式（ISRMSRN) 34, 35。 請參閱第二圖’其為本發明之-實施例之即時作業系統核心之各種狀 態遷移的示意圖。如圖所示，正常即時作業系統核心1〇的工作狀態可區分 為睡眠狀態（Dormant state)54、等候狀態（Waiting state)50、備便狀態 (Ready state)51、執行狀態(Running state)52與執行插斷服務狀態53。 當有插斷事件發生時，即時作業系統核心1〇隨即插斷現行執行中之程式， 改執行相對應之插斷服務程式ISR，一直到ISR執行結束後，再回復到原程 式之執行狀態52。新加入之工作(Task)或插斷需求納入備便列隊(Ready queue)而處於備便狀態51中等候，被插斷的程式則納入等候列隊(Waiting queue)50中等候，當即時作業系統核心1〇完成執行中之作業排程時，將該 10 1330812 作業排程排入睡眠狀態54，或稱為停止狀態’隨即由工作控制權交換模組 12 ’根據敎權由備便舰中選擇最適當下__個卫作繼續執行，以提升等 整體操控系統之反應效能。 _如第三圖所示’其為本發明之一實施例之一般插斷需求之處理時間的 不意圖’其顯示即時作業系統核心、1Q於處理—般插斷需求時之等候 (Latency)時間IRQTla1、職⑽、反應(Resp〇nse)時間聰卿、师赃與回 復(Recovery)時間IRQTreh、IRQIW，其中第二一般插斷需求雌訊號之優 先權低於第--般插斷需求_訊號。如第_所示，其為本發明之一實 施例之優先插斷需求之處理時間的示意圖，其顯示即時作業系統核心1〇於 處理快速型巢缝斷需求之等候_ FIQTui、FIQV、反應_輝卿、 FIQ1W與回復時間FiQ1Wl m，其中第二優先插斷需求訊號_之優 先權低於第-優先满需求峨FIQ卜如第四_第三騎示，即時作業 系統核心10處理第四圖之優先插斷需求FIQ比處理第三圖之一般插斷需求 IRQ反應更快速，其中即時作業系統核心、1〇處理優先插斷需求⑽所需之 等候時間FIQTlm、FIQTu2趨近於零，因此中央處理器處理優先插斷需求FIQ 所需之反應時間FIQTres,、FIQTW與回復時間而啦,、fiq1W2也相對縮短。 «月參閱第五A圖與第五B圖，其為本發明之一實施例之處理一般插斷 •需求之流程圖。如第五A圖所示，按步驟S100所示，即時作業系統核心10 初始化-主程式’亦即讀取該主程式之系統初始值然後按步驟疆所示， 執行等待插斷事件之迴圈。如第五8圖所示，當即時作業系統核心1〇於執 行等待迴圈之過程中，發生一插斷事件，而該插斷事件觸發一一般插斷需 求訊號’並發送至即時作業系統核心]〇時，即時作業系統核心、1〇按步驟 S102所tf，儲存目前之相關資料如令央處理器之程式計數器伽卿 Counter’ PC)資料、狀態登錄器、資料登錄器等資料群組而暫存至一插 斷堆疊（Interrupt stack)單元，其如圖七所示。然後按步驟遞所示設 定允許插斷位元為1，再按步驟S104所示，至對應之插斷服務程式脱的 初始位址6賣取該對應之插斷服務程式ISR，接著於步驟遍中執行該對應 1330812 之插斷服務程式ISR，接續步驟S1G6於插斷服務程式ISR執行完成後，再 由插斷堆疊單元回復原資料群組至對應之驗置，以供即時作業系統核心 10繼續執行回復之執行程式β 、 如第六圖所示，其為本發明之一實施例之處理優先插斷需求之流程 圖，其表示優先靖f求之處理機制。由於本發明之處理鋪讓即時作業 系統核心10可分離出最具時效需求的優先插斷需求_，_，而讓即時 作業系統核心1G具有分辨優先插斷需求FIQ1，FIQ2編號之能力，以及快 速處理相對應插斷服務程式F蘭，FISR2之能力。按步驟咖所示即 時作業系驗w 1G執行主程式時發生—輯事件，_發龍之一插斷需 求訊號發送至即時作靠統核心、1G;接續按步驟S2G2所示，即時作業系統 核心ίο先行賴插斷需求訊狀織，如果是優先_需求(fiqi)訊號， 則按步驟測所示’導向至對狀—即雜饋服務程式FISR1的初始位 址，而讀取優先插斷服務程式FISR1，即時執行步驟S205，即為即時執行 優先插斷贿程式F聰，然後按麵S2G6所示，完缝先輯服務程式 FISR1後回復先前被插斷之執行程式。如此優先插斷 行處理時間，達到快速反應之除 有效驗例 接續上述，再按步驟S202所示，若非優先插斷需求，則按步驟S2〇3 所示，尋找對應插斷需求之位址，以執行步驟S2〇4之依據該插斷需求導向 至對應之插斷服務程式ISRMSRN的初始位址，而讀取對應之一般插斷服 務程式ISR1〜ISRN。然後按步驟S205所示，執行對應之插斷服務程式，於 執行完成插斷服務程式ISRpISRN後，按步驟S2〇6所示，回復先前插斷之 執行程式。 請參閱第七圖，其為本發明之另一實施例之快速操控系統之多執行緒 的方塊圖。如圖所示，本發明執行快速操控系統的計算機結構包含一中央 處理器60與一記憶體70，中央處理器60連接一記憶體70，且中央處理器 60包含一程式計數器（cpu pr〇gram c〇unter) 6〇2與複數暫存器，記 憶體70包含一第一優先控制區塊Ή、-帛二優先控制區塊72、-第一一 12 1330812 般控制區塊73至一第N個一般控制區塊74、一第一優先插斷堆叠單元75、 一第二優先插斷堆疊單元76與一第一一般插斷堆疊單元77至一第N個一 般插斷堆疊單元78。第一優先控制區塊71包含一第一優先指標暫存單元 712、一第一優先插斷狀態單元714與一第一優先插斷優先權單元716，第 二優先控制區塊72包含一第二優先指標暫存單元722、一第二優先插斷狀 態單元724與一第二優先插斷優先權單元726，第一一般控制區塊73包含 一第一一般指標暫存單元732、一第一一般優先插斷狀態單元734與一第一 一般插斷優先權單元736 ’第N個一般控制區塊74包含一第N個一般指標 暫存單元74卜一第N個一般優先插斷狀態單元734與一第N個一般插斷優 先權單元736。 承上述，第一指標暫存單元712、第二指標暫存單元722與第一一般指 標暫存單元732至第N個一般指標暫存單元742分別儲存一指標位址，其 分別導向第一優先插斷堆疊單元75、第二優先插斷堆疊單元76與第一一般 插斷堆疊單元77至第N個一般插斷堆疊單元78之儲存位址。且第一優先 插斷堆疊單元75、第二優先插斷堆疊單元76與第一一般插斷堆疊單元77In addition to the above-mentioned right-handed handling of call disconnection, there are (1) a simple method for the traditional interrupted f system, (2) with a two-brain break demand scale design method > general feed demand (Qi input and & Speed priority interrupt demand ((10)) The end of the towel processor, where HQ is used for critical steep speed priority interrupt (5), towel (10) is used for general interrupt demand ^ and (3) zero routine processing time, Quick priority interrupt control H 'The fast start first _ control program provides the interrupt request number and the corresponding thief interrupt service program (inspection service R〇utine, _) initial address to the central processing The function of the device. When a __interruption event occurs, and the fast priority insertion is triggered, one of the controllers corresponding to the interrupt control unit sends a corresponding plug (4) when the signal is processed centrally H, 'will enable the towel processor to Immediately based on the implementation of the current highest priority, the priority of the interrupted service, the clerk's job (four) to improve the response time of the operation. The invention uses the "zero-line processing time fast-type interrupt controller" to provide rapid response control and its new _ is the money _ _ 快 fast 赖 age-like operating procedures ^ device, Efficiently shortens the response time of the quick-control system, and quickly achieves the immediate response, thus improving the system's effectiveness. Allows fast and accurate procedures, or system performance with high stability, toughness and reliability. See Figure-Figure' It is a block diagram of a fast control system according to an embodiment of the present invention. The real-time operating system core of the present invention includes a work schedule (10) (6), a Context Switching module 12, The resource allocation tube rce Allocation Management module 13 , an interrupt processing module μ , a pass 8 channel processing module 15 and an exception processing module 16 . The maintenance scheduling (Qbseheduling) module U assigns the operation schedule of the corresponding interrupt service program according to the receiving order of the interrupt demand signal, and immediately the service control exchange (c〇ntext switching) module 12 is based on the interrupt service. The program prioritizes the job schedule to handle the highest priority work tasks in real time. Work control 2 exchange module 12 Linyi service process red limb rights pure order modification age program is the most appropriate work schedule after the 'interruption processing test 14 according to the update status (four) process execution interrupt service program, communication channel processing mode Group 15 uses the fast information transmission busway to handle Ap (multiple communication pipes, mailboxes, event sequencing, etc.). Resource configuration management (Res〇urce A11〇cati〇nManagement) Module 13 detects resource allocation information. In the above, the Exception Handling module 16 detects the operation status of the interrupt processing module 14. When an exception processing event occurs in the interrupt processing module 14, the exception processing module 16 immediately transmits - the highest priority (four) requirement. The domain-to-guard (4) joyful group 12 drives the interrupt processing module 14 to immediately execute the corresponding interrupt service routine to exclude exception processing events, such as the exception processing event 'such as the operation overflow of the interrupt processing module 14 ( GverflQW) <) In addition, the rapid control system of the present invention further includes a fast type interrupt controller 2 and a main program unit 31. The fast type interrupt controller 20 is provided with a first priority interrupting unit 2, a second priority interrupting unit, a first general interrupting unit 23, an Nth general interrupting unit 24, and a sensor 25. a controller 26, wherein the first priority interrupting unit 21 and the second priority interrupting unit 4 respectively transmit a first priority interrupt demand signal FIQ1 and a second priority interrupt demand signal FIq2, the first general interrupt The demand 23 and the Nth general interrupt demand 24 are respectively sent - the first general interrupt demand signal earned and the Nth general interrupt demand signal main program unit 31 has a system call module 311 and a drive unit 312, wherein the real-time operating system core 10 is a main program included in the execution main program unit 31. In addition, the immediate insertion request corresponding to the first priority insertion demand FIQ1 signal is to drive the work control right exchange module 12 of the real operation system core 10 to modify the current work schedule scheduled by the work scheduling module n. The real-time operating system core 10 interrupts the execution program whose priority is lower than the corresponding immediate first priority interrupt service program, and the priority first executes the first priority interrupt service routine 1330812 (FISR1) 32; the second priority interpolating requirement The real-time plug-in requirement corresponding to FIq2 is to drive the work control right exchange module 12 of the real-time operating system core 10 to modify the current work schedule, so that the current operating system core 10 is interrupted, and the current priority is lower than the second priority interrupting requirement. The execution program of FIq2, and the priority execution of the second priority interrupt service program (FISR2) 33. In addition, when the work scheduling module 11 is based on the interrupt demand signal sent by the interrupt controller 2, and the scheduled process includes the corresponding _ the thief first interrupts the demand for the instant priority interrupt service program' The work control right exchange module 12 compares the priority of the plug-in service program currently executed by the immediate priority interrupt service program and the interrupt processing module 14, and modifies the job schedule according to the comparison result, and allows the interrupt processing The module executes the high priority interrupt service program. If the instant priority interrupt service is called, the job management module 14 guesses that the instant service program 'if the interrupt processing module 14 is currently executed. The interrupt service module has a high priority, and the interrupt processing module 14 continues to execute the current interrupt service program. Moreover, when the work scheduling module u is in accordance with the work schedule scheduled by the interrupt demand signal sent by the interrupt controller 20, the work schedule includes at least one instant corresponding to at least one immediate priority interrupt demand signal. When the service program is interrupted and the at least one plug-in service program corresponding to at least the interrupt signal is interrupted, the work control right exchange module 12 first modifies the work schedule according to the immediate priority interrupt request signal, and then according to the The general interrupt request signal modifies the job schedule, and the interrupt processing module 14 executes the priority interrupt service program (FISR1, FISR2) first, and then executes the general interrupt service program (ISRMSRN) 34, 35. Please refer to the second figure, which is a schematic diagram of various state transitions of the core of the real-time operating system of the embodiment of the present invention. As shown in the figure, the working state of the normal real-time operating system core can be divided into a Dormant state 54, a Waiting state 50, a Ready state 51, and a Running state 52. Interrupt the service state 53 with the execution. When an interrupt event occurs, the real-time operating system core 1 插 interrupts the currently executing program, and executes the corresponding interrupt service program ISR until the ISR execution ends, and then returns to the execution state of the original program 52 . The newly added Task or Interruption requirement is included in the Ready queue and is waiting in the standby state 51. The interrupted program is included in the Waiting queue 50, when the core of the real-time operating system 1〇 When the execution of the scheduled work schedule, the 10 1330812 work schedule is discharged into the sleep state 54, or called the stop state, and then the work control right exchange module 12 is selected according to the right of the reserve. The current __ Guardian continues to perform to improve the response performance of the overall control system. As shown in the third figure, 'which is a non-intentional processing time for the general insertion demand of one embodiment of the present invention', which shows the Latency time of the real-time operating system core and 1Q in processing the interrupt demand. IRQTla1, job (10), reaction (Resp〇nse) time Congqing, teacher and reply (Recovery) time IRQTreh, IRQIW, wherein the second general interrupt demand female signal has lower priority than the first-interest interrupt demand_signal . As shown in the figure _, which is a schematic diagram of the processing time of the priority insertion requirement according to an embodiment of the present invention, which shows that the core of the real-time operating system is waiting for the processing of the rapid nesting gap requirement_FIQTui, FIQV, reaction_ Huiqing, FIQ1W and reply time FiQ1Wl m, wherein the priority of the second priority interrupt demand signal _ is lower than the first-priority full demand 峨FIQ Bu such as the fourth_third riding, the immediate operating system core 10 processes the fourth picture The priority insertion requirement FIQ is faster than the general interrupt requirement IRQ of the third figure. The waiting time FIQTlm and FIQTu2 required by the immediate operating system core and the processing priority insertion requirement (10) approach zero, so the central The processor handles the response time FIQTres, FIQTW and response time required to interpolate the demand FIQ, and the fiq1W2 is also relatively shortened. «Monthly refer to the fifth A diagram and the fifth B diagram, which are flowcharts of the processing of general interleaving and demand according to an embodiment of the present invention. As shown in FIG. 5A, as shown in step S100, the real-time operating system core 10 initializes the main program, that is, reads the initial value of the main program, and then executes the loop waiting for the interrupt event as shown in the step. . As shown in FIG. 8 , when the real-time operating system core 1 is in the process of executing the waiting loop, an interrupt event occurs, and the interrupt event triggers a general interrupt demand signal and is sent to the core of the real-time operating system. ] 〇, the real-time operating system core, 1 step according to step t102 tf, store the current relevant information such as the central processor program counter Ginger Counter' PC) data, status register, data logger and other data groups and Temporarily stored in an Interrupt Stack unit, as shown in Figure 7. Then, according to the step, the setting allows the interrupt bit to be 1, and then, according to step S104, the corresponding interrupt service program ISR is sold to the corresponding initial address of the interrupt service program, and then the step is repeated. The interrupt service program ISR corresponding to 1330812 is executed, and after the execution of the interrupt service program ISR is completed in step S1G6, the original data group is returned to the corresponding verification device by the interrupting stacking unit, so that the real-time operating system core 10 continues. The execution program β for executing the reply, as shown in the sixth figure, is a flowchart of the processing priority insertion request according to an embodiment of the present invention, which indicates a priority processing mechanism. Since the processing of the present invention allows the real-time operating system core 10 to separate the most interrupted demand for the most demanding requirements, the real-time operating system core 1G has the ability to resolve the priority insertion requirements FIQ1, FIQ2 numbering, and fast. The ability to handle the corresponding interrupt service program Flan, FISR2. According to the step coffee, the real-time operation system check w 1G occurs when the main program is executed - the event, _ one of the tyrants interrupts the demand signal and sends it to the instant core, 1G; the subsequent step S2G2 shows the core of the real-time operating system. Ίο first breaks the demand signal, if it is the priority _ demand (fiqi) signal, then according to the step test, the 'directed to the right---the initial address of the miscellaneous service program FISR1, and the read priority interrupt service The program FISR1, immediately executing step S205, is to execute the priority interrupting program F Cong immediately, and then, according to the surface S2G6, completes the previously interrupted execution program after completing the service program FISR1. In this way, the row processing time is preferentially inserted, and the fast response is completed. In addition to the valid test example, the above step is performed. If the demand is not preferentially inserted, the address corresponding to the interrupt request is searched for as shown in step S2〇3. The corresponding general interrupt service programs ISR1 ISISRN are read by executing the step S2〇4 according to the interrupt request and leading to the initial address of the corresponding interrupt service program ISRMSRN. Then, as shown in step S205, the corresponding interrupt service program is executed. After the completion of the interrupt service program ISRpISRN, the execution program of the previous interrupt is returned as shown in step S2〇6. Please refer to the seventh figure, which is a block diagram of a multi-thread of the quick control system according to another embodiment of the present invention. As shown, the computer structure of the present invention for executing a rapid control system includes a central processing unit 60 and a memory 70. The central processing unit 60 is coupled to a memory 70, and the central processing unit 60 includes a program counter (cpu pr〇gram). C〇unter) 6〇2 and a plurality of registers, the memory 70 includes a first priority control block Ή, a second priority control block 72, a first one 12 1330812, a control block 73 to a Nth A general control block 74, a first priority interleaving stacking unit 75, a second priority interleaving stacking unit 76 and a first general interleaving stacking unit 77 to an Nth general interleaving stacking unit 78. The first priority control block 71 includes a first priority indicator temporary storage unit 712, a first priority insertion state unit 714 and a first priority interrupt priority unit 716, and the second priority control block 72 includes a second The priority indicator temporary storage unit 722, a second priority interrupted state unit 724 and a second priority interrupted priority unit 726, the first general control block 73 includes a first general indicator temporary storage unit 732, a first general The priority interrupt status unit 734 and a first general interrupt priority unit 736 'the Nth general control block 74 include an Nth general indicator temporary storage unit 74 and an Nth general priority interrupt status unit 734 and An Nth general interrupt priority unit 736. In the above, the first indicator temporary storage unit 712, the second indicator temporary storage unit 722, and the first general indicator temporary storage unit 732 to the Nth general indicator temporary storage unit 742 respectively store an indicator address, which respectively leads to the first priority. The storage address of the stacking unit 75, the second priority interleaving stacking unit 76, and the first general interleaving stacking unit 77 to the Nth general interleaving stacking unit 78 are interrupted. And the first priority interleaving stacking unit 75, the second priority interleaving stacking unit 76 and the first general interleaving stacking unit 77
至第N個一般插斷堆疊單元78分別儲存對應第一優先插斷服務程式、第二 優先插斷服務財鮮一餘嶋務奴至帛N個-般贿服務程式之 資料參數；第-優先插斷狀態單元714、第二優先插斷狀態單元724與第一 般插斷狀態單元734至第N個-般插斷狀態單元744更分別儲存第一優先 插斷需求FIQ卜第二優先插斷需求_與第一一般插斷需求職至第n 個一般插斷需求_之狀態資訊；第一優先插斷優先權單元716 '第二優 ，插斷優先權單元726與第-般插斷優先權單元736至第N個一般插斷優 ，單兀746更刀別儲存第一優先_需求卿、第二優先插斷需求卿 '、 叙插斷需求1RQ1至第N個一般插斷需求卿之優先權。 即時作㈣統1G之工作触模組n會齡健排程至該些暫存器 體70 Ϊ即乍排程模組ί1依據所有插斷需求之優先權順序儲存對應記憶 初口立址至暫存器604 ’因而設定程式計數器602讀取插斷需求參 13 1330812 數之讀取順序’以讓程式計數器602依據該讀取順序讀取已設定之插斷需 求參數’讓中央處理器6〇執行對應之ISR;當即時作業系統10接收一更高 優先權之FIQ時’即時作業系統1〇即發送一插斷訊號至中央處理器6〇，而 驅使中央處理器60插斷正在執行之isr，以及驅使程式計數器602讀取該 些暫存器604所儲存之對應位址，以讓中央處理器6〇執行對應之FISR。當 FISR或ISR執行完畢時，將回填返回位址至程式計數器6〇2，以讓中央處 理器60接續執行原本被插斷之程式。The Nth general interrupt stacking unit 78 stores data parameters corresponding to the first priority interrupt service program, the second priority interrupt service, and the N-general bribe service program; The interpolating state unit 714, the second priority interpolating state unit 724 and the first interpolating state unit 734 to the Nth general interpolating state unit 744 respectively store the first priority interpolating requirement FIQ and the second priority interpolating requirement _ with the first general interrupt demand to the nth general interrupt demand _ status information; first priority interrupt priority unit 716 'second best, interrupt priority unit 726 and the first general interrupt priority Unit 736 to the Nth general interpolation, the single 兀 746 is not the first priority to store the first priority _ demand qing, the second priority interrupt demand clerk ', the insertion of the demand 1RQ1 to the N general insertion demand priority right. Instant (4) system 1G work touch module n ageing health scheduling to the temporary register body 70 Ϊ instant scheduling module ί1 according to the priority order of all interrupt requirements to store the corresponding memory initial address to the temporary The memory 604' thus sets the program counter 602 to read the read order of the interrupt request parameter 13 1330812 'to allow the program counter 602 to read the set interrupt demand parameter according to the read order' for the central processor 6 to execute Corresponding ISR; when the real-time operating system 10 receives a higher priority FIQ, the real-time operating system 1 transmits an interrupt signal to the central processing unit 6〇, and drives the central processing unit 60 to interrupt the isrium being executed. And driving the program counter 602 to read the corresponding addresses stored by the registers 604 to cause the central processor 6 to execute the corresponding FISR. When the FISR or ISR is executed, the return address is returned to the program counter 6〇2, so that the central processor 60 can continue to execute the program that was originally interrupted.
一開始，即時作業系統核心10驅使中央處理器60先讀取並執行主程 式單元31之絲式，而等待插斷需求參㈣設定，續執行其對應的插斷 服務程式，若有多個插斷需求參數同時設定，職照已設定插斷需求參數 的優先權比較’中央處理器6〇會依工作排程模組u已設定於中央處理單 元暫存器602之作業排程執行對應之ISR，當令央處理器6〇執行該作業排 程所包含之其中-ISR，且-更高優先權的插斷需求_訊號發送至中央處 理器60時，將使中央處理器6〇會插斷目前執行的脱，轉而執行對應呗 的FISR。等新的FISR執行完畢後，脱的結束指令便會重新回填原本被插 斷程式的返回紐職辆數^咖，餅被贿的主程式得關續執行， 可讓中央處理^ 6Q執行主程式時—再被插斷，以形成高效率的 τςι?沾理方式運用優先插斷處理方式的即時操控軟體程式，將原本 立轉移至主程式執行，如此可精簡脱的負擔，讓中央處理器6〇 立即反應插斷需求輸人，達成高難的㈣反應作業需求。 :，中央處理單元6G於執行第—般插斷堆疊單元？7 一一般插斷服務程式哪時接收到第一優先插斷需求 中央處理單元60先讀取第-優先控·Μ β说而使 離眘句、優先控術塊，以取得第一優先控制區塊的狀 ^務程弋的優先楢古於f務程式的初始位址與優先權。由於第一優先插斷 U程摘優先“於第——編__式咖因此巾 先插斷目前執行的第--般插斷服務程式咖 於 斷服務程式ISR1的資料，再依攄第一“储存對應於第一一般插 據第優先域暫存單元711所儲存之指標 14 1330812 位址讀取並執行第一優先插斷服務程式FISR1，其中第一優先指標暫存單元 711所儲存之指標位址即對應於第一優先插斷堆疊單元的儲存位址亦即對 應第一優先插斷服務程式的資料參數。 此外，本發明之快速操控系統，可再進一步將具時效需求之第二優先 優先插斷需求FIQ2分離出來，讓即時作業系統核心1〇具有分辨第二優先 優先插斷需求FIQ2編號之能力，以及快速處理相對射哪軟體之能力， 包含：當事件插斷需求發生時，即時作業系統核心、10先行辨識FIQ2之編 號；如果是第二優先優綠斷需求⑽2)，肚即跳至姆應的簡2初 始位址，即時執行第二優先插斷服務程式FISR2。但須適當之硬體設備相配 合，以達整體反應效率之提升。 又’本發明更可整合即時作業系統核心、1〇，亦即工作排程模组u、工 作控制權交換模組12、該資源配置管理模組13、插斷處理模組14、通訊通 道處理模組15與例外處理模組16為-系統晶片（System on Chip s〇c) (Application Specific Integrated Circuit, ASIC) (Field Programing Gate Array, FPGA) 路且快速型插斷控制器2〇亦可與上述之工作排程模組i卜工作控制權 換模組12該資源配置管理模組13、插斷處理模組14、通訊通道處理模 、:、"外處理模組16整合為―系統晶片W或—特_途積體電路Μι。 二可編輯邏輯閉陣列脱電路，另外，快速型插斷控制器20亦可 鼓胡睡°為一系統晶片S〇C或—特殊用途積體電路跳或一場效可編輯邏 ;FPGA電路。如此簡化本發明之電路架構以及藉由硬體實現插斷 需求’而讓本㈣之快速操㈣統反應更加迅速。 明眘η所述者，僅林發明之—雛實_而已，並非絲限定本發 神舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精 -=等變化與修飾，均應包括於本發明之中請專利範圍内。 國專具有新紐、進步性及可業彻者，應符合我 所規疋之專利申請要件無疑，爰依法提出發明專利申請，祈鈞 15 1330812 局早日賜准專利，至感為禱。 【圖式簡單說明】 第一圖為本發明之一實施例之快速操控系統之方塊圖； 第二圖為本發明之一實施例之中央處理器之各種狀態遷移示意圖； 第三圖為本發明之一實施例之一般插斷需求之處理時間示意圖； 第四圖為本發明之一實施例之優先插斷需求之處理時間示意圖； 第五圖為本發明之一實施例之處理一般插斷需求之流程圖； 第六圖為本發明之一實施例之處理優先插斷需求之流程圖；以及 第七圖為本發明之另一實施例之快速操控系統之多執行緒的示意圖。 【主要元件符號說明】 10 即時作業系統核心 11 工作排程模組 12 工作控制權交換模組 13 資源配置管理模組 14 插斷處理模組 15 通訊通道處理模組 16 例外處理模組 20 快速型插斷控制器 21 第一優先插斷需求 22 第二優先插斷需求 23 第--般插斷需求 24 第N個一般插斷需求 25 感測器 26 控制器 31 主程式單元 1330812 311 驅動單元 312 系統呼叫模組 32 第一優先插斷服務程式 33 第二優先插斷服務程式 34 第一一般插斷服務程式 35 第N個一般插斷服務程式 50 等候狀態 51 備便狀態 52 執行狀態 53 執行插斷服務狀態 54 睡眠狀態 60 中央處理器 602 程式計數器 604 暫存器 70 記憶體 71 第一優先控制區塊 711 第一優先指標暫存單元 72 第二優先控制區塊 721 第二優先指標暫存單元 73 第一一般控制區塊 731 第一一般指標暫存單元 74 第N個一般控制區塊 741 第N個一般指標暫存單元 75 第一優先插斷堆疊單元 76 第二優先插斷堆疊單元 77 第一一般插斷堆疊單元 78 第N個一般插斷堆疊單元 17Initially, the real-time operating system core 10 drives the central processing unit 60 to read and execute the silk of the main program unit 31, and waits for the interrupt request parameter (4) to be set, and continues to execute its corresponding interrupt service program. The break demand parameter is set at the same time, and the job photo has set the priority comparison of the plug-in demand parameter. 'The central processor 6 执行 will execute the corresponding ISR according to the work schedule set by the work scheduling module u that has been set in the central processing unit register 602. When the central processor 6 executes the -ISR included in the job schedule, and the -high priority interrupt demand_signal is sent to the central processing unit 60, the central processing unit 6 will be interrupted. The execution is off, and the corresponding FISR is executed instead. After the execution of the new FISR, the end of the instruction will be re-filled back to the number of returning jobs that were originally interrupted. The main program of the bribe will be executed continuously, allowing the central processing unit to execute the main program. Time--interruption, in order to form a high-efficiency τςι? smuggling method using the priority interrupt processing method of the instant control software program, the original transfer to the main program execution, so that the burden can be streamlined, let the central processor 6 〇 Immediately respond to the demand for insertion and input, and achieve high-difficult (four) reaction operation needs. : The central processing unit 6G performs the first interleaving of the stacking unit? 7 When a general interrupt service program receives the first priority interrupt request, the central processing unit 60 first reads the first-priority control Μβ and then leaves the cautionary sentence and the priority control block to obtain the first priority control area. The priority of the block is prior to the initial address and priority of the program. Because the first priority is interrupted, the U-process is preferentially "in the first - edited __-style coffee, so the towel is first inserted into the currently-executed first-interrupt service program to break the service program ISR1 data, and then rely on the first "Storing the index 14 1330812 stored in the first general-purpose priority domain temporary storage unit 711 to store and execute the first priority interrupt service program FISR1, wherein the first priority indicator temporary storage unit 711 stores the indicator. The address corresponds to the storage address of the first priority interrupt stacking unit, that is, the data parameter corresponding to the first priority interrupt service program. In addition, the fast control system of the present invention can further separate the second priority prioritized insertion requirement FIQ2 with the aging requirement, so that the real-time operating system core has the ability to distinguish the second priority prioritized insertion requirement FIQ2 number, and The ability to quickly process which software is relatively involved, including: when the event interrupting demand occurs, the real-time operating system core, 10 first identifies the FIQ2 number; if it is the second priority excellent green breaking demand (10) 2), the belly jumps to the M. Jane 2 initial address, instant execution of the second priority interrupt service program FISR2. However, appropriate hardware equipment must be used to achieve an overall improvement in reaction efficiency. In addition, the present invention can integrate the core of the real-time operating system, that is, the work scheduling module u, the work control right exchange module 12, the resource configuration management module 13, the interrupt processing module 14, and the communication channel processing. The module 15 and the exception processing module 16 are System on Chips (ASIC) (Field Programing Gate Array (FPGA)) and the fast-type interrupt controller 2 The resource scheduling module 12, the interrupt processing module 14, the communication channel processing module, and the external processing module 16 are integrated into a system chip. W or - special _ way integrated circuit Μι. The second editable logic closed-array off-circuit, in addition, the fast-type interrupt controller 20 can also be used as a system chip S〇C or a special-purpose integrated circuit jump or an effect editable logic; FPGA circuit. This simplifies the circuit architecture of the present invention and enables the fast-moving (four) system to react more quickly by implementing the interrupting requirements by hardware. The above mentioned, only the invention of the Lin _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Within the scope of the patent in the present invention. The national specialties have new, progressive and practical, and should meet the requirements of patent applications that I have stipulated. Undoubtedly, the application for invention patents is filed according to law, and the 15 1330812 Bureau will grant patents as soon as possible. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a block diagram of a fast control system according to an embodiment of the present invention; the second figure is a schematic diagram of various state transitions of a central processing unit according to an embodiment of the present invention; Schematic diagram of the processing time of the general interrupting requirement of one embodiment; the fourth drawing is a schematic diagram of the processing time of the priority interrupting requirement according to an embodiment of the present invention; and the fifth figure is a processing of the general interrupting requirement according to an embodiment of the present invention. FIG. 6 is a flow chart of processing a priority insertion requirement according to an embodiment of the present invention; and FIG. 7 is a schematic diagram of a multi-thread of a quick control system according to another embodiment of the present invention. [Main component symbol description] 10 Real-time operating system core 11 Work scheduling module 12 Work control right switching module 13 Resource configuration management module 14 Interrupt processing module 15 Communication channel processing module 16 Exception processing module 20 Fast type Interrupt Controller 21 First Priority Interrupt Demand 22 Second Priority Interrupt Demand 23 First-Plug Interrupt Demand 24 Nth General Interrupt Demand 25 Sensor 26 Controller 31 Main Program Unit 1330812 311 Drive Unit 312 System call module 32 first priority interrupt service program 33 second priority interrupt service program 34 first general interrupt service program 35 Nth general interrupt service program 50 wait state 51 standby state 52 execution state 53 execution plug Shutdown service state 54 sleep state 60 central processor 602 program counter 604 register 70 memory 71 first priority control block 711 first priority indicator temporary storage unit 72 second priority control block 721 second priority indicator temporary storage unit 73 First general control block 731 First general indicator temporary storage unit 74 Nth general control block 741 Nth general indicator temporary storage Element 75 first priority interrupt stack unit 76 of the second priority interrupt stack unit 77 of the first stacking means 78 interrupt the general N-th general interrupt stacking unit 17