200837633 九、發明說明： 【發明所屬之技術領域】 本發明係有關於'~種择和系續，辟别s女Μ 有效提升择㈣心ιΓ 有關於一種快逮操控系統，其 有版物υ敎I作效率，錄義控_之穩定性。 【先前技術】 曹==n(ReaMime System)，如通訊協定處理器、數位 减處理is#顧’ ¥遍呈現軟硬織統設計複雜、_200837633 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to '~ selection and continuation, and s s Μ Μ Μ Μ Μ Μ Μ 四 四 Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ Γ敎I for efficiency, recording control _ stability. [Prior technology] Cao ==n (ReaMime System), such as communication protocol processor, digital subtraction processing is #顾' ¥over rendering soft and rigid weaving design complex, _
件之反鱗_長、執行敎鮮縣使时絲與錄衫佳， 統整合困難等缺點。當反應速度為操鮮勒要之關舰考量項目時，如 何保證操控祕具舰速反應力，已成心程師首先祕需要解決之 課題。 傳統快速操控系統之主程式與插斷服務程式之運作方式，在主程式完 成初始設定後，即料對應各_需求（Interrupt Request，_的插斷 服務程式(J—r_ Service Routine，ISR)執行，整 要負載為最兩優先權的出現頻率最高的定時插斷，譬如麵雨8中對應卿 之TIMER1，較低優先權的出現頻率較底的定時插斷，譬如誦廳s中對應 # IRQ82TIMER2 ’以及其他相關介面插斷需求的ISR，其中當中央處理器開 始執行ISR時’中央處理器會強制在ISR之内部參數設定允許插斷位元為 1，以允許優先權較高之插斷需求搶先執行其ISR。 插斷需求的例行處理之效能是藉由插斷服務程式ISR來處理各種不同 之插斷事件，其改善措施如以軟體方式處理時，有三種方式，即··串接式 ISR排列法、具優先次序表之ISR #示表以及無優先次序表之ISR指示表。 若採用硬體方式處理呼叫ISR時，則有（1)用於傳統之插斷控制器之簡便 法；（2)具兩條插斷需求輸入控制線設計法··一般插斷需求（Interrupt Request，IRQ)輸入端與優先插斷需求(Fast Interrupt Re(juest，fiq)輸 入端的中央處理器，其中FIQ用於關鍵性之優先插斷需求，而IRq則用於 200837633 一般性插斷需求。以及(3)零例行處理時間之快速型插斷控制器，當有插斷 需求發生時，快速型插斷控制器將FIQ之編號與相對應FISR之初始位址同 時傳送至中央處理器，而提升操控系統之作業時效。 快速操控系統的反應時間受到四種因素影響，即：硬體架構之效能、 即時性作㈣統核^卫作排程之處理效能、插斷處理效能以及資源管理效 能:其中叫統已是各型操控祕可重複使狀軟體元件，但操 控系統為了使用即雜作靠統，卻會導致操㈣統之設計複雜度增加， 因而降低處理效能。尤其，關鍵性即時資料之輸入處理方式與處理時間會 直接影響操㈣騎事件反應之快慢。為符合朗者之需求，如何提升快 速插控I狀快歧應能力，㈣速胁魏設牡_爾鑛之課題。 2 ’本發明針對上述之問題而提供—種㉟速操控纽，其讓即時作 =2⑽速而準確的完成健程序，達成高度狱性、_性與可靠 【發明内容】 t發明之主要目的在於提供—雜絲 指 斷事件之能力，並财掌M_ 〜㈣献應處理指 件之反應時間’提升系統之運作效能。&日’機’有效縮短插斷事 本發明之次-目的，在提供 效的核心m崎，供轉配置各2設置快速準確而有 系統的反應時效。 直合环跌迷耜控系統，可加速快速操控 本發明之另一目的，力担乂林 簡化系統設計之複雜度，逮操«統，_模組化的設計， 品可靠度錢簡倾發雜、降低财成本、提高產 幅提升系統性能 。、作業程序。減輕電源消耗，達到快速反應，巨 號 本發縣-種快速操控錢，其提 :後，快速掌握插斷事件卢…、接收插斷事件所對應之插斷需求訊 处日、機’並依據插斷事件之優先順序決定對 200837633 ! 應之插斷服務程式之執行優先順序，以迅速處裡所有插斷事件，且快速操 控系統一旦接收到對應關鍵性插斷事件之優先插斷需求訊號時，隨即處理 關鍵性插斷事件，另外，本發明之快速操控系統更可迅速排除例外處理事 件，以提升快速操控系統之反應效率。本發明之電路藉由採用模組化的設 計，以簡化系統設計的複雜度，運用高速中央處理器提升運算處理速度， 以及運用資源管理技術達成處理複雜系統之能力，而提昇整體系統性能， 巨幅縮短例行(Overhead)軟體處理作業時間軟體處理作業時間。 赢 【實施方式】 馨 茲為使貴審查委員對本發明之結構特徵及所達成之功效有更進一步 之瞭解與認識，謹佐以較佳之實施例及配合詳細之說明，說明如後： 快速操控系統的廣泛應用，尤其是彼入式操控系統，為推動近代科技 自動化控制系統迅速發展之原動力，具有促進資訊數據速率，提升電腦中 央處理器的指令存取速度，匯流道存取介面之可程式化，降低電源消耗量 等功能。 快速操控系統之即時作業系統的處理項目包含··工作排程、工作控制 權父換、插斷處理、通訊通道處理與例外處理。其中工作排程之處理效能 鲁與其採用之運算法則有關，工作排程之常用運算法則，如：出現頻率高低 排程(Rate Monotonic，RT)法則、最早到達時限優先(EarHest DeadUne First，EDF)法則、最少出現優先(Minimum Laxity First，MLF)法則等動 悲排程(Dynamic Scheduling)法則等，各有其優缺點。至於較先進之排序 法則’如最緊急優先(Maximum Urgency First，MUF)法則，則融合上述各 法則優點之集九成’但處理複雜度與成本相對較高。 基本上’工作控制權交換之效能與中央處理器之硬體架構有關，不同 的介面與中央處理器結構與處理軟體之效能息息相關，即··推出機制仇由 mechanism)、登錄器窗口（Register win(j〇w)、快速記憶機制（casMng mechanism)與夕管道執行架構等技術。插斷處 200837633 斷服務程式1SR來處理各種不同之插斷事件，一般插斷 处耘序為.步驟㈠由插斷控制器決定事件優先次序.牛驟卜） 僅能由硬體&盖之步驟(五)事件完成插斷服務。其中步驟㈠與(二） )與㈤僅能由性能較佳之脱運算法則改善。 =法、具優先次序表之ISR指示表⑽敝)以及無優先次序表之^指 不衣。The anti-scale of the pieces _ long, the implementation of the Xianxian County, the time and silk recording, the integration difficulties and other shortcomings. When the reaction speed is the key consideration for the handling of the ship, how to ensure the speed response of the handling of the secret ship has become the subject of the first secret problem. The main program of the traditional rapid control system and the operation mode of the interrupt service program are executed after the main program completes the initial setting, which is corresponding to each _requirement (Interrupt Request, _'s interrupt service program (J-r_ Service Routine, ISR) The whole load is the highest frequency of the most two priority insertions, such as the corresponding TIMER1 in the rain 8 and the lower priority frequency of the lower timing, such as the corresponding # IRQ82TIMER2 in the hall s 'and other related interfaces interrupted demand ISR, when the central processor starts to perform ISR' the central processor will force the internal parameter setting of the ISR to allow the interrupt bit to be 1 to allow higher priority interrupt demand Preemptive execution of its ISR. The performance of routine processing of interrupting requirements is to handle various interrupt events by interpolating the service program ISR. There are three ways to improve the software, such as serial connection. ISR permutation method, ISR #表表 with priority table, and ISR indicator table without priority table. If the call ISR is handled in hardware, there are (1) for traditional interrupts. Simple method of controller; (2) Design method of input control line with two interrupts required · Interrupt Request (IRQ) input and priority interrupt request (Fast Interrupt Re (juest, fiq) input Central processor, where FIQ is used for critical priority interrupt requirements, while IRq is used for 200837633 general interrupt requirements, and (3) zero-line processing time for fast interrupt controllers when there is an interrupt requirement When it occurs, the fast-interrupt controller transfers the FIQ number to the central processor at the same time as the initial address of the corresponding FISR, and improves the operating time of the control system. The response time of the fast-control system is affected by four factors, namely: The performance and real-time performance of the hardware architecture (4) The processing efficiency of the management, the processing efficiency of the interrupt processing, and the efficiency of resource management: Among them, the system is a repetitive messenger software component, but the control system is The use of miscellaneous work will result in increased design complexity of the operation (4), thus reducing processing efficiency. In particular, the input processing method and processing time of critical real-time data will directly affect (4) The speed of response to the riding event. In order to meet the needs of the Langers, how to improve the ability of rapid insertion and control of I-shaped fast-disambiguation, (4) the subject of the rapid-warning Weishen-Yer mine. 2 'The present invention provides for the above problems - A 35-speed control button, which allows instant 2 = (10) speed and accurate completion of the health program, achieving a high degree of prison, _ sex and reliability [invention] The main purpose of the invention is to provide - the ability of the wire to break the event, And the financial palm M_ ~ (4) should deal with the reaction time of the finger 'improving the operational efficiency of the system. & day 'machine' effectively shortens the insertion of the present invention - the purpose of providing efficient core m, supply and configuration Each 2 sets a fast, accurate and systematic response time. The direct-loop loop-down control system can accelerate the quick manipulation of another object of the present invention, and the complexity of the system design is simplified, and the system design is simplified, and the reliability of the product is simplified. Miscellaneous, reduce financial costs, increase production capacity and improve system performance. , operating procedures. Reducing power consumption and achieving rapid response, the giant number of this county - kind of fast control money, which: after, quickly grasp the interrupt event Lu..., receive the interrupted event corresponding to the interrupt demand, the machine, and The priority of the interrupt event determines the execution priority of the 200837633! interrupt service routine to quickly intervene all interrupt events, and the fast control system receives the priority interrupt request signal corresponding to the critical interrupt event. The critical interrupt event is processed immediately. In addition, the rapid control system of the present invention can quickly eliminate the exception handling event to improve the reaction efficiency of the fast control system. The circuit of the invention improves the complexity of the system design by adopting a modular design, using a high-speed central processing unit to improve the processing speed, and using resource management technology to achieve the ability to process complex systems, thereby improving overall system performance, Overhead software processing time software processing time. Win [Embodiment] Xinzin has a better understanding and understanding of the structural features and the effects achieved by the review committee. Please refer to the preferred embodiment and the detailed description to explain the following: Quick control system Widely used, especially the in-line control system, to promote the rapid development of modern technology automation control system, to promote the information data rate, improve the command access speed of the computer central processing unit, and the programmable channel access interface , to reduce power consumption and other functions. The processing items of the real-time operating system of the quick-control system include · work scheduling, work control, parental exchange, interrupt processing, communication channel processing, and exception processing. The processing efficiency of the work schedule is related to the algorithm used by it. The common algorithms for work scheduling, such as the Rate Monotonic (RT) rule and the EarHest DeadUne First (EDF) rule. The minimum priority (Minimum Laxity First, MLF) rules, such as the Dynamic Scheduling rule, have their own advantages and disadvantages. As for the more advanced sorting rules, such as the Maximum Urgency First (MUF) rule, the advantages of the above-mentioned rules are combined into 90%, but the processing complexity and cost are relatively high. Basically, the performance of the work control exchange is related to the hardware architecture of the central processing unit. The different interfaces are closely related to the performance of the central processor structure and the processing software, that is, the launch mechanism mechanism, the register window (Register win) (j〇w), fast memory mechanism (casMng mechanism) and eve pipeline execution architecture. Interruption 200837633 break service program 1SR to handle a variety of different interrupt events, the general interrupts are ordered. Step (a) by plugging The controller determines the priority of the event. The cattle can only be interrupted by the hardware & step (5) event. Steps (1) and (2)) and (5) can only be improved by the better off-performance algorithm. = method, ISR indicator table with priority list (10) 敝), and no priority list.
插斷ΪίΪ，雜用硬體方式處理呼叫谓時，則有（1)簡便法鎌傳統之 〈插斷需求⑽)輸人端財央處職，其中FI㈣於關鍵 β#Ρ^Ιλφ ^ ^ ,jc〇 £<^(3)^Wf4i$ 电狼㈣、優先插斷控㈣，該快速優先鑛控制11具翻時提供插斷需 "(FaSt Service Routine, 之初始位址至中央處理器之功能。當有一插斷事件發生，而觸發該 =優先插斷控制H之—對應之插斷控鮮元發送—對應之插斷需求訊號 中央處理_，將讓中央處理將以即時依據執行目前優純最高之優 先插斷服務程式_，所以關㈣作業反應時效。 t 膝用「零例行處理時間之快速型插斷控制器」，提供快速反應之 鱼速操控系、献其方法’制是錢—種翻於快速操控纽之作業程序 ”裝置#效縮短快速操控系統反應時間，快速而準確的達成即時反絲 ^ ’因而提升系統之卫作效益。讓快速準柄程序，或至高度穩定性、強 早々性與可靠性之系統性能。 ^明參閱第一圖，其為本發明之一實施例之快速操控系統之方塊圖。如 =斤不’本發日狀即時作業纽核心，其包含—工作排程⑽sehedul㈣ 代且11工作控制權交換①加仏义士 Switching)模組12、一資源配置管 里(Resource All〇catlon Management)模組 13、一插斷處理模組 14、一通 8 200837633 理模組15與-例外處理模組16。碎排程⑽遍u i依據插斷需求訊號之接收順序指派對應插斷服務程式之作㈣程後，立Interruption Ϊ Ϊ Ϊ 杂 Ϊ Ϊ Ϊ 杂 Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂 杂Jc〇£<^(3)^Wf4i$ electric wolf (four), priority plug-in control (four), the fast priority mine control 11 time-providing insertion needs " (FaSt Service Routine, the initial address to the central processor The function: when an interrupt event occurs, and triggers the = priority interrupt control H - the corresponding interrupt control fresh element transmission - the corresponding interrupt demand signal central processing _, will allow the central processing to execute the current basis Excellent pure highest priority interrupt service program _, so off (four) operation response aging. t Knee uses "zero routine processing time fast type interrupt controller" to provide fast response fish speed control system, offer its method It is money - a kind of operation program that turns over the fast control button. The device # shortens the response time of the quick control system, and quickly and accurately achieves the instant anti-wire ^' thus enhances the effectiveness of the system. Let the quick-handle program, or to the height Stability, strong earlyness and reliability System performance. Referring to the first figure, it is a block diagram of a fast control system according to an embodiment of the present invention. For example, if the size of the current operation is the core of the current operation, it includes a work schedule (10) sehedul (four) generation and 11 Work Control Rights Exchange 1 Plus Switching Module 12, Resource All〇catlon Management Module 13, Interrupt Processing Module 14, One Pass 8 200837633 Management Module 15 and - Exception Processing Module Group 16. Fragmentation schedule (10) passes ui according to the order of reception of the interrupt demand signal, and assigns the corresponding interrupt service program (4)
Switehing)模組12依據插斷服務程式之優 =紐麵齡，細⑶觸。工作控制 組陳據插斷服務程式之優先權高低順序修改該作業排程為最適 ^作業齡讀,_理· 14_麟狀作籍程執行插斷服務 ^式’通訊通道處理模組15利用快速資訊傳輸匯流道處理Ap間（多重通訊Switehing) module 12 is based on the superiority of the plug-in service program = new face age, fine (3) touch. The work control group uses the priority level of the interrupt service program to modify the job schedule to be the optimum ^ working age reading, _ _ 14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Fast information transmission channel processing between Ap (multiple communication)
官道、W事件排料）。魏㈣Res。嶋Μ丨咖⑻Μ琴肥⑹ 杈組13偵蒐資源配置資訊。 承上述，例外處理(ExceptionHandling)模組16偵測插斷處理模組14 之作業狀態，當插斷處理模組14發生—例外處理事件時，例外處理模_ 立即發送-最高優先插斷需求訊號至工作_權交換模組12，而驅使插斷 处理模、、且14立即執行對應之彳崎服務程式，以排除例外處理事件，其中例 外處理事件，如插斷處理模組14之運算溢位（加出⑽）。另外，本發明 之快速操㈣、賊包含-快速赌斷控織2G與—主減單元31。快速型 插斷控制H 20設置-第-優先插斷單元m先插斷單元22、一 第--般插斷單元23、-第N個-般插斷單元24、一感測器25、一控制器 26其中第-優先插斷單元21與第二優先插斷單元22為分別發送一第一 優先插斷需求訊號FIQ1與一第二優先插斷需求訊號FIQ2,第一一般插斷需 求23與第IH固-般插斷需求24齡別發送一第一一般插斷需求訊號賺 與一第N個一般插斷需求訊號_。主程式單元31具有一系統呼叫模組 311與一驅動單元312，其中即時作業系統核心10為執行主程式單元31所 包含之一主程式。 另外，第一優先插斷需求FIQ1訊號所對應之即時性插斷需求為驅使即 時作業系統核心10之工作控制權交換模組12修改目前工作排程模組u所 排疋之作業排程’讓即時作業系統核心1〇插斷目前優先權低於對應之即時 第一優先插斷服務程式之執行程式，而接續優先執行第一優先插斷服務程 200837633 式（FISRl) 32 ;第二優先插斷需求_所對應之 即時作業系統核心1〇之工作控制權交換模組12修改目前之=== 即時作業系統核心、10插斷时優先權低於第二優先插斷需求_之 程式’而接續優紐行第二優先插斷服務程式（FiSR2)犯。 又’當工作排程模組U依據插斷控制器2〇所發送 而=之健齡包含賊-㈣錢核叙㈣優務 私式時，工作控制權父換模、组12即比較該即時優先插斷服務程式與插斷處 理核組14目前執行之插_務程式的優先權，並依據比較結果修改該 排程，而義斷處理模組14執行優先權高之插斷服務程式，若該即時優先 插斷服務程紅優先權高，_斷細驗14執機即時優先插斷服務程 式，若插斷處理模組14目前執行之插斷服務程式的優先權高，則插斷處理 模組Η繼續執行目前之插_務程式。且，當工作排程模組u依據插斷 控制器20所發送之插斷需求訊號所排定之作業排程中，而該作業排程包含 對應至少-即時優先插斷需求訊號之至少一_優先插斷服務程式與對應 至少--般插斷需求喊之至少—般插斷服務程式時，工作控制權交換 模組12即先依據該即時優先插斷需求訊號修改該作業排程，再依據該一般 插斷需求訊f綠改該作飾程，祕插斷處理模組14先執行該優先插斷服 務耘式（FISR1，FISR2)，再執行該一般插斷服務程式（iSRi〜ISRN) 35。 請參閱第二圖，其為本發明之一實施例之即時作業系統核心之各種狀 •癌遷移的示意圖。如圖所示，正常即時作業系統核心1〇的工作狀態可區分 為睡眠狀態（Dormant state)54、等候狀態(Waiting state)50、備便狀態 (Ready state)51、執行狀態(Running state)52與執行插斷服務狀態53。 當有插斷事件發生時，即時作業系統核心1〇隨即插斷現行執行中之程式， 改執行相對應之插斷服務程式ISR，一直到ISR執行結束後，再回復到原程 式之執行狀態52。新加入之工作(Task)或插斷需求納入備便列隊(Ready queue)而處於備便狀態51中等候，被插斷的程式則納入等候列隊(Waiting queue)50中等候’當即時作業系統核心10完成執行中之作業排程時，將該 10 200837633 作業排程排入睡眠狀態54，或稱為停止狀態，隨即由工作控制權交換模組 12，根據優先權由備便列隊中選擇最適當下一個工作繼續執行，以提升等 整體操控系統之反應效能。 如第三圖所示，其為本發明之一實施例之一般插斷需求之處理時間的 示意圖’其顯示即時作業系統核心1Q於處理—般插斷需求時之等候 (Latency)時間 IRQTLA1、IRQTLA2、反應(Resp〇nse)時間 _卿、__與回 復(Recovery)時間IRQL、IRQTrk2，其中第二一般插斷需求_訊號^優 先權低於第一般插斷需求聰贿。如細圖所示，其為本發明:一實 施例之優偷斷需求之處理時間的示意圖，其顯示即時作業系統核心㈣ 處理快速型巢狀插斷需求之等候時間F肌,、F肌A2、反應時間卿、、 FIQTW與回復時間FL、FIQW，其中第二優先插斷需求峨綱2之優 先權低於第-優先插斷需求訊號_。如第四圖與第三圖所示，即時作^ 系統核心10處理第四圖之優先插斷需求FIQ比處理第三圖之一般插斷•求 加反應更快速，其中即時作業系統核心1〇處理優先插斷需求⑽所^之 等候時間FIQTW1、FIQTu2趨近於零’因此中央處理器處理優先插斷需求 所需之反應時間FIQfe、FIQT_與回復時間FIQ1Wi、FIQTrk2也相對縮短。 請參閱第五A圖與第五B圖，其為本發明之一實施例之處理一般 需求之流程圖。如第五A圖所示，按步驟_所示，即時作業系統核心1〇 初始化-主程式，亦即讀取触程式之祕初始值，織按步驟簡所示， 執打等待插斷事件之迴圈。如第五B _示，當即時作業系統核心1〇於執 :等待_之過程中’發生-插斷事件，而該插斷事件觸發一一般 ^訊號，並發送至即時作業系統核心1G時，即時作業系統核心iQ按步驟 厂02所不’儲存目前之相關資料如中央處理器之程式計數器(加細 ounter’ PC)胃料、狀態登錄H、資料登錄轉資料群組，而暫存至—插 ，堆疊anter_ stack)單元，其如圖七所示。然後按步驟遞所示咬 2許插斷位元為！，再按步驟腿所示，至對應之瓣服務程式跦的 仞始位_取該對應之插斷服務程式ISR，接著於步驟懸中執行該對應 200837633 獅6於嫌雜細執行嫌，再 ㈣續執行回復之群組至對應之原位置，以供即時働統核心 圖，’其為本發明之—實施例之處理優先插斷需求之流程 【㈣二 需求之處理機制。由料發明之處理機制讓即時作業 作業^访可=離出最具時效需求的優先插斷需求FIQ1，_，而讓即時 速處理相具有分辨縣插斷f求FIQ1，FIQ2編號之能力，以及快 時ΐ鞏= 式麵’簡2之能力。按步驟_所示，即 業系捕心10執行主程斜發生一插斷 # 10; ^ ^ 'tmTm ‘步插斷f求訊號之編號，如果是優—斷需求(_)訊號’ 址，二敌得^不’導向至對應之一即時性插斷服務程式FISR1的初始位 而_4先_服務財F腿，㈣執行步驟麵 ，紐按刪206所示，完紐_服務程式 行處理執 如輸鱗議理可有侧 接，上述’再按步驟所示，若非優先插斷絲，職步驟咖 對應插斷需求之紐，以執行步驟s之依據該插斷需求導向 2之插斷服務程式脱卜的初始位址’輯取對應之—般插斷服 力私式ISR1〜ISRN 〇然後按步驟S205所示，執行對廡之插 ^=3斷騎喊聰.N後，按轉S2G6;示，喊^插= =閱m其為本發明之另—實施例之快速操控系統之多執行绪 卢田。如圖所不’本發明執行快速操控系統的計算機結構包含 ^器6G與-記憶體7〇，中央處理器6()連接—記麵7()，且卷 二T二式？器⑽一。uM 叫體70包3-第一優先控制區塊7卜一第二優先控制區塊了2、—第〜 12 200837633 般控制區塊73至-第_-般控制區塊74、—第―狄觸堆疊單元？5、 -第二優先插斷堆疊單元76與-第―—般插斷堆疊單元77至—第n個一 般插斷堆疊單元78。第-優脸魏塊71包含—第—縣指標暫存單元 712、-第-優先插斷狀態單元714與一第一優先插斷優先權單元716，第 二優先控制區塊72包含-第二優先指標暫存單元？22、一第二優先插斷狀 態單元724與-第二優先插斷優先權單元汹，第一一般控制區塊73包含 -第一般練暫存單元732、崎——般優紐斷轉料I與一第一 =插斷優先權單元736，第N個一般控制區塊74包含一第n個一般指標 ΓΪΓ Γ 一第N個一般優先插斷狀態單元734與一第N個一般插斷優 先權早元736。 *承士述，第-指標暫存單元瓜、第二指標暫存單元π2與第一一般指 732至第N個一般指標暫存單元742分別儲存一指標位址，其 ==:，7先插斷堆疊單元75、第二優先插斷堆疊單元76與第二一般 至第N個—般插斷堆疊單元78之儲存位址。且第一優先 二優先插斷堆疊私76與第—般插斷堆疊單元77 =:ΪΓΓ疊單元78分別儲存對應第一優先插斷服務程式、第二 爐斷職程歧第Ν個―_斷服務程式之 貝枓參數H先插斷麟單元714、第二縣 態單元734至第Ν個—般插單元744 :斷而求_、第二優先插斷需求FIQ2與第——般插斷絲_至第N 個-般插斷需求1_之狀態f訊；第一優先 與第—般插斷優先權單·至第^般^ ㈣^〜刀別儲仔弟一優先插斷需求卿、第二優先播斷需电PIQ2 與第--般插斷需求_至第N個—般插斷需求卿之優先權 即時健錢1G之工作排賴組U會儲存作㈣程至 604 ’亦即工作排程握如】彳 占 二暫存器 體70之初雜址絲據所有㈣需权優先_稍存對應記憶 暫存益604，因而設定程式計數器6〇2讀取插斷需求參 13 200837633 灸貝取順序崎程式計數器6〇2依據該讀取順序讀取已設定之插斷需 蜃1數讓中央處理器60執行對應之1SR;當即時作業系統10接收一更高 ^權之FIQ時’即時作業系統1〇即發送一插斷訊號至中央處理器⑼，而 =中央處理器6〇插斷正在執行之脱，以及驅使程式計數器機讀取該 :二暫存器604所儲存之對應位址，以讓中央處理器60執行對應之FISR。當 或ISR執行完畢時，將回填返回位址至程式計數器·，以讓中央處 理器6G接續執俩本·崎之程式。 、〜開始’即時作業系統核心1〇驅使中央處理器⑽先讀取並執行主程 藝式單=31之絲式’崎待插斷絲參㈣設定，以便執行麟應的插斷 務知式若有夕個插斷需求參數同時設定，則依照已設定插斷需求參數 的優先巾央處理$⑼會依卫作排程模組a已設定於巾央處理單 =暫存器602之作業排錄行對應之脱，當中央處理器6〇執行該作業排 私所包3之其中-ISRi-更高優先權的插斷需求⑽訊號發送至中央處 理器60 %將使中央處理器6〇會插斷目前執行的說，轉而執行對應「IQ 的FISR。等新的FISR執行完畢後，ISR的結束指令便會重新回填原本被插 斷程式的返回位址到程式計數器繼，使得被插斷的主程式得以繼續執行， 如此方式便可讓中央處理器6〇執行主程式時一再被插斷，以形成高效率的 # 巢狀插斷處理方式。運用優先插斷處理方式的即時操控軟體程式，將原本 ISR的工作轉移至主程式執行，如此可精簡脱的負擔，讓中央處理器卯 立即反應插斷需求輸入，達成高效能的即時反應作業需求。 例如’中央處理單元6〇魏行帛-一般插斷堆疊單元77所儲存之第 --般插，服務程式騰時接收到第一優先插斷需求卿訊號，而驅使 ^央處理單元60先讀取第-優先控制區塊，以取得第一優先控制區塊的狀 悲資訊、第-優先插斷服務程式的初始位址與優先權。由於第一優先插斷 服務程式的優先權高於第--般插斷服務程式ISR1，因此中央處理器6〇會 錢斷目前執行的第一般插斷服務程式，並儲存對應於[一般^ 斷服務程式ISR1的資料，再依據第一優先指標暫存單元711所儲存之指標 200837633 位址讀取並執行第一優先插斷服務程式FISR1，其中第一優先指標暫存單元 | 711所儲存之指標位址即對應於第一優先插斷堆疊單元的儲存位址，亦即對 應第一優先插斷服務程式的資料參數。 此外，本發明之快速操控系統，可再進一步將具時效需求之第二優先 優先插斷需求FIQ2分離出來，讓即時作業系統核心1〇具有分辨第二優先 ； 優先插斷需求FIQ2、編號之能力，以及快速處理相對應FISR2軟體之能力， 包含：當T件插斷需求發生時，即時作業系統核心1〇先行辨識FIQ2之編 號；如果是第二優先優先插斷需求(F，則立即跳至相對應的FISR2初 ^ φ 始位址即時執行第一優先插斷服務程式FISR2。但須適當之硬體設備相配 合，以達整體反應效率之提升。 又，本發明更可整合即時作業系統核心1〇，亦即工作排程模組n、工 I 作控制權交換模組12、該資源配置管理模組13、插斷處理模組14、通訊通 丨 道處理模組15與例外處理模組16為一系統晶片（System on Chip, SoC) 或一特殊用途積體電路（Applicati〇n Specific Integrated Circuit， ASIC)或一場效可編輯邏輯閘陣列（FieMpr〇grammingGate紅ray，Fp以) ； 且快速型插斷控制器2〇料與上述之工作排賴組n、工作控制權Official road, W event discharge). Wei (four) Res.嶋Μ丨 ( (8) Μ 肥 肥 (6) 杈 group 13 Detective resource allocation information. In the above, the Exception Handling module 16 detects the operation status of the interrupt processing module 14 when the interrupt processing module 14 generates an exception processing event, the exception processing mode _ immediate transmission - the highest priority interrupt request signal Up to the work_right exchange module 12, driving the interrupt processing module, and 14 immediately executing the corresponding Nagasaki service program to exclude exception processing events, wherein the exception processing events, such as the operation overflow of the interrupt processing module 14 (Add (10)). In addition, the fast operation (4) of the present invention, the thief includes a fast betting control 2G and a main subtraction unit 31. Quick type interrupt control H 20 setting - first priority interrupting unit m first interrupting unit 22, a first insertion unit 23, - Nth general interrupting unit 24, a sensor 25, a The controller 26, wherein the first priority interrupting unit 21 and the second priority interrupting unit 22 respectively send a first priority interrupt demand signal FIQ1 and a second priority interrupt demand signal FIQ2, the first general interrupt demand 23 and The first IH solid-like interrupt demand 24 years old does not send a first general interrupt demand signal earned with an Nth general interrupt demand signal _. The main program unit 31 has a system call module 311 and a drive unit 312, wherein the real-time operating system core 10 is a main program included in the execution main program unit 31. In addition, the immediate insertion request corresponding to the first priority insertion demand FIQ1 signal is to drive the work control right exchange module 12 of the real operation system core 10 to modify the current work schedule of the current work scheduling module u. The real-time operating system core 1〇 interrupt current priority is lower than the corresponding immediate first priority interrupt service program execution program, and the connection first executes the first priority interrupt service service 200837633 (FISR1) 32; the second priority interrupt The work control right exchange module 12 of the real-time operating system core corresponding to the demand_modifies the current === the core of the real-time operating system, and the priority of the 10-bit interrupt is lower than the second priority interrupting demand_ You are the second priority interrupt service program (FiSR2). In addition, when the work scheduling module U is sent according to the interrupt controller 2〇, and the health is included in the thief-(4) money verification (four) superior service private, the work control right parent changes the model, the group 12 compares the instant Priority interrupting the service program and interpolating the priority of the plug-in processing core group 14 currently executing, and modifying the schedule according to the comparison result, and the assertion processing module 14 executes the high-priority interrupt service program, if The instant priority interrupt service service has a high priority, and the _ break test 14 performs the immediate priority interrupt service program. If the interrupt service module currently executing the interrupt processing module 14 has a high priority, the interrupt processing mode is interrupted. The group continues to execute the current plug-in program. Moreover, when the work scheduling module u is in accordance with the work schedule scheduled by the interrupt demand signal sent by the interrupt controller 20, the work schedule includes at least one corresponding to at least one-time priority interrupt demand signal. When the priority interrupt service program and the at least the general interrupt service program corresponding to at least the general interrupt demand are invoked, the work control right exchange module 12 first modifies the work schedule according to the immediate priority interrupt demand signal, and then The general interrupt request signal is modified, and the secret interrupt processing module 14 first executes the priority interrupt service (FISR1, FISR2), and then executes the general interrupt service program (iSRi~ISRN). . Please refer to the second figure, which is a schematic diagram of various types of cancer migration in the core of the real-time operating system according to an embodiment of the present invention. As shown in the figure, the working state of the normal real-time operating system core can be divided into a Dormant state 54, a Waiting state 50, a Ready state 51, and a Running state 52. Interrupt the service state 53 with the execution. When an interrupt event occurs, the real-time operating system core 1 插 interrupts the currently executing program, and executes the corresponding interrupt service program ISR until the ISR execution ends, and then returns to the execution state of the original program 52 . The newly added task or interrupt request is included in the Ready queue and is waiting in the standby state 51. The interrupted program is included in the Waiting queue 50 waiting for the current operating system core. 10 When the execution schedule is completed, the 10 200837633 job schedule is discharged into the sleep state 54, or stopped state, and then the work control right exchange module 12 is selected according to the priority. A job continues to be performed to improve the response performance of the overall control system. As shown in the third figure, it is a schematic diagram of the processing time of the general insertion requirement of one embodiment of the present invention. It shows the waiting time (Latency) time IRQTLA1 and IRQTLA2 of the real-time operating system core 1Q in processing the general interrupt demand. Responsive (Resp〇nse) time_qing, __ and recovery time (Recovery) time IRQL, IRQTrk2, where the second general interrupt demand _ signal ^ priority is lower than the general interrupt demand. As shown in the detailed diagram, it is a schematic diagram of the processing time of the preferred stealing requirement of an embodiment of the present invention, which shows the core of the real-time operating system (4) waiting time for the rapid nest insertion requirement F muscle, F muscle A2 The response time is clear, the FIQTW and the reply time FL, FIQW, wherein the second priority interrupt demand criterion 2 has a lower priority than the first priority interrupt demand signal _. As shown in the fourth and third figures, the system core 10 processes the priority insertion requirement FIQ of the fourth picture. The general interpolation and the addition response are faster than the processing of the third picture, wherein the real-time operating system core 1〇 The waiting time for the priority insertion request (10) is FIQTW1 and FIQTu2 is close to zero. Therefore, the reaction time required for the CPU to process the priority insertion requirement FIQfe, FIQT_ and the recovery time FIQ1Wi, FIQTrk2 are also relatively shortened. Please refer to Figures 5A and 5B, which are flow diagrams of the general requirements for processing in accordance with one embodiment of the present invention. As shown in Figure 5A, as shown in step _, the real-time operating system core 1 initialization-main program, that is, the initial value of the touch program is read, and weaving, as shown in the step, is waiting for the interrupt event. Loop. As shown in the fifth B_, when the real-time operating system core 1 is in the process of 'waiting_', the occurrence-interruption event, and the interrupting event triggers a general signal, and is sent to the real-time operating system core 1G. The real-time operating system core iQ does not store the current relevant information such as the central processor's program counter (plus fine ounter' PC), the status log H, the data login to the data group, and the temporary operation to - Insert, stack the unit_stack) unit, as shown in Figure 7. Then, according to the steps, the bite is inserted and the bit is broken! Then, according to the step leg, to the corresponding service address of the corresponding service program _ take the corresponding interrupt service program ISR, and then execute the corresponding 200837633 lion 6 in the step suspension, and then (4) Continue to execute the reply group to the corresponding original location for the instant system core diagram, 'which is the process of processing the priority insertion requirement of the embodiment of the invention [(4) two requirements processing mechanism. According to the processing mechanism of the invention, the instant job operation can be used to exit the priority insertion demand FIQ1, _, which is the most time-sensitive requirement, and let the instant processing phase have the ability to distinguish the county from the FIQ1, FIQ2 number, and Fast time ΐ Gong = style 'simplified 2' ability. According to the step _, the industry department catches the core 10 to perform the main path oblique occurrence of an interrupt # 10; ^ ^ 'tmTm 'step inserts the number of the signal, if it is the excellent-break requirement (_) signal address, The second enemy has not been directed to the initial position of one of the instant interruption service programs FISR1 and _4 first _ service finance F legs, (4) execution step surface, button shown in delete 206, complete _ service program line processing If you are in charge of the scales, you can have a side connection. The above steps are shown in the following steps. If the thread is not preferentially inserted, the job step corresponds to the insertion of the demand, and the step s is performed according to the insertion of the insertion demand. The initial address of the service program is extracted, and the corresponding ISR1~ISRN is inserted. Then, as shown in step S205, the insertion of the ^ ^ = = = = = . . . . S2G6; show, shout ^ plug = = read m is another embodiment of the invention - the quick control system of the multi-threaded Lu Tian. As shown in the figure, the computer structure of the present invention for executing the quick control system includes a device 6G and a memory 7 〇, a central processor 6 () connected - a face 7 (), and a volume two T two? One (10) one. uM is called the body 70 package 3 - the first priority control block 7 - a second priority control block 2 - the first ~ 12 200837633 general control block 73 to - the first general control block 74, - Di Touch stacking unit? 5. The second priority interleaving stacking unit 76 and the -th intervening stacking unit 77 to the nth general interleaving stacking unit 78. The first-superior face block 71 includes a -th county index temporary storage unit 712, a -first priority interrupt status unit 714 and a first priority interrupt priority unit 716, and a second priority control block 72 includes - second Priority indicator temporary storage unit? 22, a second priority interrupt state unit 724 and a second priority interrupt priority unit, the first general control block 73 includes - the first general temporary storage unit 732, the s And a first = interrupt priority unit 736, the Nth general control block 74 includes an nth general indicator Γ Γ an Nth general priority interrupt state unit 734 and an Nth general interrupt priority Early 736. * 承士, the first indicator temporary storage unit melon, the second indicator temporary storage unit π2 and the first general indicator 732 to the Nth general indicator temporary storage unit 742 respectively store an indicator address, which ==:, 7 first The storage address of the stacking unit 75, the second priority interleaving stacking unit 76, and the second to Nth general interleaving stacking unit 78 are interrupted. And the first priority two preferentially inserts the stack private 76 and the first interrupted stacking unit 77 =: the folding unit 78 stores the corresponding first priority interrupt service program, and the second furnace interrupts the first one. The parameter of the service program is first inserted into the lining unit 714, the second county unit 734 to the third unit, the general insertion unit 744: the _, the second priority insertion requirement FIQ2 and the first-like insertion wire _ to the Nth - the general interrupt demand 1_ state f news; the first priority and the first interpolated priority list · to the ^ ^ ^ (four) ^ ~ knife save the younger brother a priority to interrupt demand, The second priority broadcast power demand PIQ2 and the first-interruption demand _ to the Nth-like interruption demand for the priority of the immediate health money 1G work arbitrage group U will be stored as (four) to 604 ' The work schedule is as follows: 彳 occupies the first singularity of the register body 70 according to all (4) power priority _ slightly stored corresponding memory temporary storage benefit 604, thus setting the program counter 6 〇 2 reading the interrupt demand reference 13 200837633 The moxibustion ordering sequence program counter 6〇2 reads the set insertion time according to the reading order, and the CPU 60 executes the corresponding 1SR; When the operating system 10 receives a higher FIQ, the real-time operating system 1 sends an interrupt signal to the central processing unit (9), and the central processing unit 6 interrupts the execution of the disconnection, and drives the program counter to read the machine. The corresponding address stored in the second register 604 is taken to cause the central processor 60 to execute the corresponding FISR. When the ISR or ISR is executed, the return address will be backfilled to the program counter, so that the central processor 6G can continue to execute the program. , ~ Start 'the real-time operating system core 1 〇 drive the central processing unit (10) to read and execute the main program single = 31 silk type 'satisfaction to insert wire (4) settings, in order to implement Lin Ying's interrupted knowledge If there is an interpolated demand parameter set at the same time, the priority processing according to the setting of the interpolated demand parameter is processed ($), and the scheduling module a is set in the processing row of the central processing unit = register 602. Corresponding to the line, when the central processing unit 6 performs the operation of the private package 3 -ISRi - the higher priority interrupt request (10) signal is sent to the central processor 60% will cause the central processor 6 to meet Interrupt the current execution, and then execute the corresponding "IQ's FISR. After the new FISR is executed, the ISR's end instruction will refill the original interrupted program's return address to the program counter, so that it is interrupted. The main program can be executed continuously. In this way, the central processing unit 6 can be interrupted repeatedly when executing the main program to form a highly efficient nested interrupt processing method. The instant control software program using the priority interrupt processing method. Will work on the original ISR Move to the main program execution, so that the burden can be reduced, so that the central processor immediately responds to the interrupt input, achieving high-performance real-time response operations. For example, 'Central Processing Unit 6〇 Wei Wei帛-General Interrupt Stacking Unit The stored first-order plug-in, the service program receives the first priority interrupt request signal, and drives the central processing unit 60 to first read the first-priority control block to obtain the first priority control block. The sorrow information, the initial address and priority of the first-priority interrupt service program. Since the priority of the first priority interrupt service program is higher than the first-interrupt service program ISR1, the central processor 6 will The money breaks the currently executed general interrupt service program, and stores the data corresponding to the [General Service Program ISR1, and then reads and executes the first priority according to the index 200837633 stored in the first priority indicator temporary storage unit 711. Interrupting the service program FISR1, wherein the indicator address stored in the first priority indicator temporary storage unit | 711 corresponds to the storage address of the first priority interrupting stacking unit, that is, corresponding to the first priority interrupting In addition, the fast control system of the present invention can further separate the second priority prioritized insertion requirement FIQ2 with the aging requirement, so that the real-time operating system core has the second priority; The ability to request FIQ2, numbering, and the ability to quickly process the corresponding FISR2 software, including: When the T-interruption demand occurs, the real-time operating system core 1 first identifies the FIQ2 number; if it is the second priority-prioritized insertion requirement ( F, immediately jump to the corresponding FISR2 initial ^ φ starting address to immediately execute the first priority interrupt service program FISR2. However, appropriate hardware equipment should be matched to achieve an overall improvement in reaction efficiency. The real-time operating system core can be integrated, that is, the work scheduling module n, the work I control ring exchange module 12, the resource configuration management module 13, the interrupt processing module 14, and the communication channel processing module The 15 and exception processing module 16 is a System on Chip (SoC) or an Applicati Integrated Integrated Circuit (ASIC) or an effect. Series A logic gate array (FieMpr〇grammingGate red ray, Fp in); and fast interrupt controller 2〇 type material of the above-described discharge depends Working Group n, work control
X換核組12、該資源配置管理模組13、插斷處理模組14、通訊通道處理模 _ 、、且15與例外處理她16整合為-系統晶片SoC或-特殊用途積體電路ASIC 或-場效可編輯邏輯閘陣列FPGA電路，另外，快速型插斷控制器2〇亦可 獨立整合為-系統晶片Soc或―特殊用途積體電路趟c或一場效可編輯邏 =閉陣列FPGA電路。如此簡化本發明之電路架構，以及藉由硬體實現插斷 需求，而讓本發明之快速操控系統反應更加迅速。 惟以上所述者，僅為本發明之一較佳實施例而已，並非用來限定本發 明實施之細，舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精 神所為之均等變化與修飾，均應包括於本發明之申請專利範圍内。 故本發明係實為-具有新継、進步性及可供產業_者，應符合我 國專利法所規定之專利申請要件無疑，爰依法提出發明專利申請，祈鈞 15 200837633 局早曰賜准專利，至感為禱。 【圖式簡單說明】 第-圖為本發明之-實施例之快速操㈣統之方塊圖； 第-圖為本發明之一實施例之中央處理器之各種狀態遷移示意圖； 第二圖為本發明之一實施例之一般插斷需求之處理時間示意圖； 第四圖為本發明之一實施例之優先插斷需求之處理時間示意圖； 第五圖為本發明之一實施例之處理一般插斷需求之流程圖； φ 第六圖為本發明之一實施例之處理優先插斷需求之流程圖；以及 第七圖為本發明之另一實施例之快速操控系統之多執行緒的示意圖。 【主要元件符號說明】 10 即時作業系統核心 11 工作排程模組 12 工作控制權交換模組 13 資源配置管理模組 14 插斷處理模組 15 通訊通道處理模組 16 例外處理模組 20 快速型插斷控制器 21 第一優先插斷需求 22 第二優先插斷需求 23 第---般插斷需求 24 第N個一般插斷需求 25 感測器 26 控制器 31 主程式單元 16 200837633The X-switching core group 12, the resource configuration management module 13, the interrupt processing module 14, the communication channel processing module _, and 15 and the exception processing her 16 are integrated into a system chip SoC or a special purpose integrated circuit ASIC or - Field effect editable logic gate array FPGA circuit. In addition, the fast type interrupt controller 2 can also be independently integrated into - system chip Soc or "special purpose integrated circuit" or an effect editable logic = closed array FPGA circuit . This simplifies the circuit architecture of the present invention and enables the fast control system of the present invention to react more quickly by implementing the interrupting requirements by hardware. However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the shapes, structures, features, and spirits described in the claims are equivalently changed. Modifications are intended to be included in the scope of the patent application of the present invention. Therefore, the present invention is actually - with new, progressive and available industries _, should meet the requirements of patent applications stipulated in China's patent law, no doubt, 提出 legally filed a patent application, praying 15 200837633 To the feeling of prayer. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a fast operation (four) of an embodiment of the present invention; FIG. 1 is a schematic diagram showing various state transitions of a central processing unit according to an embodiment of the present invention; Schematic diagram of the processing time of the general insertion requirement of one embodiment of the invention; FIG. 4 is a schematic diagram of the processing time of the priority insertion requirement according to an embodiment of the present invention; Flowchart of the demand; φ FIG. 6 is a flow chart of processing the priority insertion requirement according to an embodiment of the present invention; and FIG. 7 is a schematic diagram of the multi-thread of the quick control system according to another embodiment of the present invention. [Main component symbol description] 10 Real-time operating system core 11 Work scheduling module 12 Work control right switching module 13 Resource configuration management module 14 Interrupt processing module 15 Communication channel processing module 16 Exception processing module 20 Fast type Interrupt Controller 21 First Priority Interrupt Demand 22 Second Priority Interrupt Demand 23 First-Internal Interrupt Demand 24 Nth General Interrupt Demand 25 Sensor 26 Controller 31 Main Program Unit 16 200837633
311 驅動單元 312 系統呼叫模組 32 第一優先插斷服務程式 33 第二優先插斷服務程式 34 第----般插斷服務程式 35 第N個一般插斷服務程式 50 等候狀態 51 備便狀態 52 執行狀態 53 執行插斷服務狀態 54 睡眠狀悲 60 中央處理器 602 程式計數器 604 暫存器 70 記憶體 71 第一優先控制區塊 711 第一優先指標暫存單元 72 第二優先控制區塊 721 第二優先指標暫存單元 73 第'-一般控制區塊 731 第一一般指標暫存單元 74 第N個一般控制區塊 741 第N個一般指標暫存單元 75 第一優先插斷堆疊單元 76 第二優先插斷堆疊單元 77 第一一般插斷堆疊單元 78 第N個一般插斷堆疊單元 17311 drive unit 312 system call module 32 first priority interrupt service program 33 second priority interrupt service program 34 - general interrupt service program 35 Nth general interrupt service program 50 wait state 51 State 52 Execution State 53 Execution Interrupt Service State 54 Sleep Symptom 60 Central Processing Unit 602 Program Counter 604 Register 70 Memory 71 First Priority Control Block 711 First Priority Indicator Temporary Unit 72 Second Priority Control Block 721 second priority indicator temporary storage unit 73 '-general control block 731 first general indicator temporary storage unit 74 Nth general control block 741 Nth general indicator temporary storage unit 75 first priority interrupting stacking unit 76 Second priority interleaving stacking unit 77 First general interleaving stacking unit 78 Nth general interleaving stacking unit 17