1327778 94095 21550twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體元件及其製造方法， 別是有關於一種非揮發性記憶體及其製造方法。 【先前技術】 隨著積體電路產業的快速魏，在要求電路積集化越 來越尚的情訂，整個電路元件大小的設計也被迫往尺1327778 94095 21550twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element and a method of manufacturing the same, and to a non-volatile memory and a method of manufacturing the same. [Prior Art] With the rapid development of the integrated circuit industry, the design of the entire circuit component size is forced to the ruler in the case of requiring the circuit to accumulate more and more.
不停縮小的方向驗。當記㈣元件的尺寸逐漸縮小時， 疋件之_距離也會相對_小，當其距_短到某 的程度之後’各種因製程積集度提高所衍生的問題便會發 生0 X a習知—種非揮發性記憶體树為堆疊式結構，其主專 j基底上方以摻雜的多轉製作浮置難(floating、gate 娜gate)。而且，控制閘極是直接設置在^Constantly narrowing the direction of inspection. When the size of the (4) component is gradually reduced, the distance of the component will be relatively small. When the distance from the _ is short to some extent, the problem caused by the increase in the process integration will occur. It is known that the non-volatile memory tree is a stacked structure, and it is difficult to float above the main substrate of the j-substrate with a multi-turn doping (floating, gate-gate). Moreover, the control gate is set directly in ^
而：ί Iΐ f極與控制閘極之間以閘間介電層相隔， =閘極與基底間以閘極氧化層相隔 中形成源極與汲極》 元件憶體元件積集度的提高，傳統之應 製程产隹現/許多挑戰。舉例來說，由於記憶體 回，圯憶體元件之源極與汲極之間的距離 1日隨之2小，因此容易造植通道效應（shGft channe】 :ct于、此之外，—般記憶體元件之位元線接觸窗 r ,. \〇ntaCt)疋以自行對準接觸窗製程 _algne e〇ntaet pn)eess)所形成。因此，當元件 5 1327778 94095 21550twf.doc/n 尺寸縮小時，通常會因製程變異而造成偏移， 路或甚至是斷路等問題。再者’元件的積集化二 制閘極與浮置閘極之間的電容面積減少，使得 數（coupling ratio)降低，影響元件操作效能。σ係 因此，如何製造出小尺寸、高觀度，又能 的記憶體元件是產業的努力目標。 .漱頜口口貝 【發明内容】 有鑑於此，本發明的目的就是在提供一種 憶體及其製造方法，能_免短通道效應，使^J己 窗發生誤鮮躲賴料低，並謂提轉合係t接觸 仲ifΓί出—種非揮發性記憶體結構，此非揮發•己 ，體包括基底、第—導體層、第—介電層、第二導體^己 第-介電層與摻雜區。基底中具有溝槽。第―導體曰 於溝槽内侧表面。第—介電層配置於第—導 ^底 =第二導體層配置於第一導體層上，且填心槽基 與第二導體層之間。榜雜‘ 上述之 依照本發明的實施例所述之非揮發性記憶體 一介電層例如是氧化矽/氮化矽/氧化矽層。 上述之 依照本發明的實施例所述之非揮發性記憶體 第一導體層的材質例如是摻雜多晶矽。 上述之 依照本發明的實施例所述之非揮發性記憶體 第二導體層的材質例如是摻雜多晶矽。 上述之 依照本發明的實施例所述之非揮發性記憶體 1327778 94095 21550twf.doc/n • 第一介電層例如是氧化石夕層。 本發明提出一種非揮發性記憶體的製造方法，此方法 包括下列步驟。首先，提供基底，此基底上形成圖案化罩 幕層。然後，以圖案化罩幕層為罩幕，進行蝕刻製程，於 基底中形成溝槽。繼之，於溝槽内侧表面形成第一介電層。 而後，於第一介電層上形成第一導體層。接著，形成第二 ^電層，以順應性覆蓋圖案化之罩幕層、第一介電層與^ • 一導體層。繼之，於第二介電層上形成第二導體層。後， 進行平坦化製程，移除部分第二導體層直至曝露出第二介 電層。然後’移除曝露出的第二介電層以及圖案化罩幕層。 隨後，進行離子植入製程，於溝槽兩側之基底中形成摻雜 區。 '〆’、 依照本發明的實施例所述之非揮發性記憶體的製造 方法，上述之第二介電層例如是氧化矽/氮化矽/氧化矽層。 依照本發明的實施例所述之非揮發性記憶體的製曰造 方法，上述之第二介電層的形成方法例如是進行一 •相沈積製程。 予軋 依照本發明的實施例所述之非揮發性記憶體的製造And: ί Iΐ f pole and the control gate are separated by a dielectric layer between the gates, = the gate and the substrate are separated by a gate oxide layer to form a source and a drain. The traditional process should be produced and many challenges. For example, due to the memory back, the distance between the source and the drain of the memory component is 2 small, so it is easy to plant channel effects (shGft channe): ct at, beyond, The bit line contact window r, . \〇ntaCt) of the memory element is formed by self-aligning the contact window process _algne e〇ntaet pn)eess). Therefore, when the size of the component 5 1327778 94095 21550twf.doc/n is reduced, there is usually a problem of offset, road or even open circuit due to process variation. Furthermore, the capacitance area between the integrated gate of the device and the floating gate is reduced, so that the coupling ratio is lowered, which affects the operational efficiency of the device. σ system Therefore, how to create a small-sized, high-profile, and capable memory component is an industry goal.漱 口 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 The non-volatile memory structure, the non-volatile body, the body includes a substrate, a first conductor layer, a first dielectric layer, a second conductor, a dielectric layer With doped regions. There is a groove in the substrate. The first conductor is on the inner side surface of the groove. The first dielectric layer is disposed on the first conductive layer. The second conductive layer is disposed on the first conductive layer and between the filled trench substrate and the second conductive layer. The non-volatile memory-dielectric layer described above in accordance with an embodiment of the present invention is, for example, a hafnium oxide/tantalum nitride/yttria layer. The material of the non-volatile memory first conductor layer according to the embodiment of the present invention is, for example, doped polysilicon. The material of the non-volatile memory second conductor layer according to the embodiment of the present invention is, for example, doped polysilicon. Non-volatile memory as described above in accordance with an embodiment of the invention 1327778 94095 21550twf.doc/n • The first dielectric layer is, for example, a oxidized layer. The present invention provides a method of manufacturing a non-volatile memory, the method comprising the following steps. First, a substrate is provided on which a patterned mask layer is formed. Then, using a patterned mask layer as a mask, an etching process is performed to form trenches in the substrate. Then, a first dielectric layer is formed on the inner surface of the trench. Then, a first conductor layer is formed on the first dielectric layer. Next, a second electrical layer is formed to compliantly cover the patterned mask layer, the first dielectric layer, and the first conductor layer. Next, a second conductor layer is formed on the second dielectric layer. Thereafter, a planarization process is performed to remove a portion of the second conductor layer until the second dielectric layer is exposed. The exposed second dielectric layer and the patterned mask layer are then removed. Subsequently, an ion implantation process is performed to form doped regions in the substrates on both sides of the trench. In the method of manufacturing a non-volatile memory according to an embodiment of the present invention, the second dielectric layer is, for example, a hafnium oxide/tantalum nitride/yttria layer. According to the method of fabricating a non-volatile memory according to an embodiment of the present invention, the method of forming the second dielectric layer is, for example, performing a phase deposition process. Pre-rolling Non-volatile memory fabrication in accordance with embodiments of the present invention
方法，上述之圖案化罩幕層例如是由墊氧化層與墊氮化芦 所組成。 S 依照本發明的實施例所述之非揮發性記憶體的製造 方法，上述之第一介電層例如是氧化矽層。 依照本發明的實施例所述之非揮發性記憶體的製造 方法’上述之第一介電層的形成方法例如是熱氧化法。 7 94095 21550twf.doc/n 依A?、本發明的實施例所述之非揮發性記憶體的製造 方法，上述之第二導體層的材質例如是摻雜多晶矽。 依照本發明的實施例所述之非揮發性記憶體的製造 ^法，上述於第一介電層上形成第一導體層的方法例如 是，先於基底上方形成導體材料層，順應性覆蓋圖案化之 罩幕層與第一介電層。然後，移除部分導體材料層，直至 曝露出第一介電層表面，以形成之。 依照本發明的實施例所述之非揮發性記憶體的製造 方法，上述之平坦化製程例如是化學機械研磨製程。 依照本發明的實施例所述之非揮發性記憶體的製造 方法，上述之移除所曝露出的第二介電層以及 層的方法例如是進行蝕刻製程。 罩幕 依,，、、本發明的實施例所述之非揮發性記情體的贺^ 方法，上述在摻舰職之前可更進-步於第 侧之基底上形成犧牲氧化層。上述，犧牲氡化層的方 法例如是熱氧化法。 ，本發明之方法是將非揮發性記憶體的部分閘極結構 ，成於基底巾’紐再於閘極結構兩卿成_區作為源 極/汲極區，因此可使源極/汲極區間的通道距離增大，如 此-來可避躲通道效應(sh⑽ehannel他叫二發生。 f方面’與1知相較’本發明之非揮發性記憶體的堆叠 南度相對較低，所以可減少位元線接觸窗誤對準的發生。 =且’本發明可以增加導體層之間的電容面積進^可提 尚耦合係數（coupling ratio)，改善元件操作效能。 1327778 94095 21550twf.doc/n 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉一實施例，並配合所附圖式’作詳細說明 如下。 【實施方式】 圖1A至圖1F為依照本發明一實施例所繪示之非揮發 性記憶體的製造方法的流程剖面示意圖。In the method, the patterned mask layer is composed of, for example, a pad oxide layer and a pad nitride. S In accordance with a method of fabricating a non-volatile memory according to an embodiment of the invention, the first dielectric layer is, for example, a hafnium oxide layer. The method for producing a non-volatile memory according to an embodiment of the present invention is a thermal oxidation method, for example, a method of forming the first dielectric layer. 7 94095 21550 twf.doc/n According to A?, a method of manufacturing a non-volatile memory according to an embodiment of the present invention, the material of the second conductor layer is, for example, doped polysilicon. According to the manufacturing method of the non-volatile memory according to the embodiment of the present invention, the method for forming the first conductor layer on the first dielectric layer is, for example, forming a conductive material layer above the substrate, and conforming the cover pattern. The mask layer and the first dielectric layer. Then, a portion of the conductor material layer is removed until the surface of the first dielectric layer is exposed to form it. According to the method of manufacturing a non-volatile memory according to an embodiment of the present invention, the above planarization process is, for example, a chemical mechanical polishing process. In accordance with a method of fabricating a non-volatile memory according to an embodiment of the present invention, the method of removing the exposed second dielectric layer and layer is performed, for example, by an etching process. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; As described above, the method of sacrificing the deuterated layer is, for example, a thermal oxidation method. The method of the present invention is to form a part of the gate structure of the non-volatile memory in the base towel 'new layer and then the gate structure to the source/drain region, thereby enabling the source/drainage The channel distance of the interval is increased, so that the channel effect can be avoided (sh(10) ehannel, he called the second occurrence. The f aspect is compared with the one. The non-volatile memory of the present invention has a relatively low stack south, so it can be reduced. Bit line contact window misalignment occurs. = and 'The invention can increase the capacitance area between the conductor layers to improve the coupling ratio and improve the component operation efficiency. 1327778 94095 21550twf.doc/n The above and other objects, features, and advantages of the present invention will become more apparent <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A schematic cross-sectional view showing a method of manufacturing a non-volatile memory according to an embodiment.
首先，請參照圖1A，提供基底1〇〇。基底1〇〇例如是 矽基底或其他合適之半導體基底。然後，於基底1〇〇上形 成罩幕層102。罩幕層1〇2例如是由塾氧化層1〇4以及塾 氮化層106所構成。罩幕層1〇2的形成方法例如是，利用 熱氧化法，在基底1〇〇上形成氧化矽層以作為墊氧化層 loy然後，進行化學氣相沈積製程，於墊氧化層1〇4上形 成氮化矽層以作為墊氮化層1〇6。 、—然後，請參照圖1B，在罩幕層1〇2形成之後，接著 進行微影與钱刻製程’以於基底腦上形成圖案化罩幕 層102a。繼之’以圖案化罩幕層1〇2a為蝕刻罩幕，钱刻 部份基底100，於基底100中形成溝槽1〇8。 於溝槽108的内側表面形成第 110例如是氧化矽層，其形成 接著，請參照圖1C， 一介電層110。第一介電層 方法例如是熱氧化法。 德Ϊ繼續參照圖1C，在第—介電層形成之 介電層UG上形成卜導體層112，第一 浮置閑極。承上述，第-導體層112的 Ϊ ίίϊί第一導體層112的形成方法例如 先於基底100上方形成導體材料層（未繪示），此導體 9 1327778 94095 21550twf.doc/n 材料層順應性覆蓋圖案化罢莖远ιλ 然後，利用化學機械研磨^與第一介電層110。 直到暴露出第一介電屛〗 ’移除部份導體材料層， 112。 日 表面，即可形成第一導體層 之後’請參照圖，才其 層114，以順應性覆蓋罩幕層形成第二介電 一導體層112。第二介電岸 弟一 w電層110與第 矽層。第二介電層114的^形歹^^氧化石夕/氮化石夕/氧化 法於基底H)〇上方形成一層氧化::例2 ’先以熱氧化 氧化石夕層。 料化成一層氮化石夕層與另— 繼之，請繼續參照圖1D，於第二 第二導體層116。第二導體層116的材質:二θ 成 梦。第二導艘層116的形成方法例如是化晶 -二!=1Ε’進行-平坦化製二=第 j體層116直至曝露出第二介電層U4，以形 j -曰116a ’此第二導體層U6a可作為控極 平坦化製程例如是化學機械研磨製程。 迖之 值得注;t的是’本發明之方法是將浮置_(第 層产112)形成於基底100中，然後再於其上方形成控搞 (第二導體層116a)，因此可降低元件的堆#高度^以^ 習知之位元線接職誤解縣誠生。另外 ^ 將浮置閘極(第-導體層112)形成於基底刚中之溝 的内側表面，因此可提高浮置閘極(第—導體層】12)盘日 閘極（第二導體層116a)之間的電容面積，進而可提高^人 94095 21550twf.d〇c/n 係數，達到增it元件操作效能的目的。 凊參照圖1F，移除所曝露出的第二介電層114 太沐你|、:、1〇^°移除第二介電層114及罩幕層102&的 於第」導蝕刻製程。之後，進行離子植入製程， 兩側之基底中形成-摻雜區118，此摻 ΐ '伽卩為非揮發性記憶體之齡織極區。在—實施例 1〇〇 前，可於第二導體層⑽兩側的基底 製程掛ir· 化層（未繪示），以避免後續之離子植入 ί 造成損傷。犧牲氧化層的材質例如是 氧化石夕，其形成方法例如是熱氧化法。 知’本發明之源極/没極區(掺雜區118)之間 的„加，因此可避免短通道效應的發生。 ㈣本發明之非揮發性記憶體結構。 參照圖1F，本發明之非揮發性記憶體主要是由 土 - 導體層112、第一介電層110、第二導體層 麻二電層114與摻雜區118戶斤構成。其中，在基 的内捕矣而有，槽.108。第-導體層112配置於溝槽108 笛乂:思第—導體層112的材質例如是摻雜多晶石夕。 m配置於第—導體層112與基底之間， 第-i體；ι!Γ:】如是氧化矽層。第二導體層ii6a配置於 . I 上，且填滿溝槽108，第二導體層116a的 晶[第二介電層114配置於第-導體 二二體層116&之間’第二介電層114例如是氧 兩侧之鼠基底二韻。摻雜區m配置於第二導體層_ 1327778 94095 21550twf.doc/n 综上所述，本發明可使源極/汲極區之間的通道長度增 加，因此可避免短通道練應的發生。另外，與習知相較， 本發明之結構的堆疊高度相對較低，因此可降低位元線接 觸窗誤對準的發生。而且，本發明還可以增加浮置閘極與 控制閘極之間的電容面積，因而可提高耦合係數，以及 元件操作效能。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限J本發明，任何熟習此技藝者，在不脫離本發明之精 =範圍内，當可作些許之更動與潤飾，因此本發明之 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】First, referring to FIG. 1A, a substrate 1 is provided. The substrate 1 is, for example, a germanium substrate or other suitable semiconductor substrate. Then, a mask layer 102 is formed on the substrate 1''. The mask layer 1〇2 is composed of, for example, a tantalum oxide layer 1〇4 and a tantalum nitride layer 106. The mask layer 1〇2 is formed by, for example, forming a ruthenium oxide layer on the substrate 1 by thermal oxidation as a pad oxide layer, and then performing a chemical vapor deposition process on the pad oxide layer 1〇4. A tantalum nitride layer is formed as the pad nitride layer 1〇6. Then, referring to Fig. 1B, after the mask layer 1〇2 is formed, a lithography and engraving process is then performed to form a patterned mask layer 102a on the base brain. Following the patterning of the mask layer 1〇2a as an etching mask, a portion of the substrate 100 is engraved to form trenches 1〇8 in the substrate 100. A 110th layer, for example, a hafnium oxide layer, is formed on the inner surface of the trench 108, which is formed. Referring to FIG. 1C, a dielectric layer 110 is formed. The first dielectric layer method is, for example, a thermal oxidation method. Referring to Fig. 1C, the germanium conductor layer 112 is formed on the dielectric layer UG formed by the first dielectric layer, and the first floating idle electrode. In the above, the first conductor layer 112 is formed by, for example, forming a conductive material layer (not shown) above the substrate 100, and the conductor 9 1327778 94095 21550 twf.doc/n material layer compliance coverage. Patterning the stem away from the λλ, then using a chemical mechanical polishing ^ with the first dielectric layer 110. The portion of the conductor material layer is removed until the first dielectric layer is exposed. On the surface of the day, the first conductor layer can be formed. Referring to the figure, the layer 114 is formed to conform to the mask layer to form the second dielectric-conductor layer 112. The second dielectric bank is a w-layer 110 and a third layer. The second dielectric layer 114 is formed by a layer of oxidation over the substrate H): in the case of the thermal oxidation of the oxidized stone layer. The material is formed into a layer of nitride layer and the other layer, and then continue to refer to FIG. 1D to the second second conductor layer 116. The material of the second conductor layer 116: two θ dreams. The second guiding layer 116 is formed by, for example, a crystal-two!=1Ε'-----the second layer of the j-th layer 116 until the second dielectric layer U4 is exposed to form a shape j - 曰 116a 'this second The conductor layer U6a can be used as a gate flattening process such as a chemical mechanical polishing process. It is worthwhile to note that the method of the present invention is to form a floating _ (first layer 112) in the substrate 100, and then form a control layer (second conductor layer 116a) thereon, thereby reducing the components. The heap #height ^ to the well-known bit line to take over the misunderstanding of the county Chengsheng. Further, the floating gate (the first conductor layer 112) is formed on the inner side surface of the groove in the base, so that the floating gate (first conductor layer) 12) the day gate (the second conductor layer 116a) can be raised. The area of the capacitor between the two can further improve the coefficient of 94095 21550twf.d〇c/n, which achieves the purpose of increasing the operational efficiency of the element. Referring to FIG. 1F, the exposed second dielectric layer 114 is removed, and the second dielectric layer 114 and the mask layer 102& are removed from the first etching process. Thereafter, an ion implantation process is performed, and a doped region 118 is formed in the substrates on both sides, and the doped gamma is a non-volatile memory age region. Before the embodiment, the ir-layer (not shown) may be etched on the substrate on both sides of the second conductor layer (10) to avoid damage caused by subsequent ion implantation. The material of the sacrificial oxide layer is, for example, oxidized stone, and the method of forming it is, for example, a thermal oxidation method. Knowing the addition between the source/no-polar region (doped region 118) of the present invention, the occurrence of short-channel effects can be avoided. (IV) Non-volatile memory structure of the present invention. Referring to FIG. 1F, the present invention The non-volatile memory is mainly composed of a soil-conductor layer 112, a first dielectric layer 110, a second conductor layer, and a doped region 118, wherein the base is trapped therein. The slot 108 is disposed in the trench 108. The material of the conductor layer 112 is, for example, doped polysilicon. The m is disposed between the first conductor layer 112 and the substrate, the -i ι!Γ:] is a ruthenium oxide layer. The second conductor layer ii6a is disposed on the I and fills the trench 108, and the second conductor layer 116a is crystallized [the second dielectric layer 114 is disposed on the first conductor 2 The second dielectric layer 114 is, for example, a rat base on both sides of the oxygen. The doped region m is disposed on the second conductor layer _ 1327778 94095 21550 twf.doc / n In summary, the present invention can Increasing the length of the channel between the source/drain regions, thereby avoiding the occurrence of short-channel training. In addition, the structure of the present invention is compared with the prior art. The stack height is relatively low, so the occurrence of misalignment of the bit line contact window can be reduced. Moreover, the present invention can also increase the capacitance area between the floating gate and the control gate, thereby improving the coupling coefficient and component operation. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
圖1A至圖if為依照本發明一實施例所繪示之 性记憶體的製造方法的流程剖面示意圖。 X 【主要元件符號說明】 100 ·基底 102 :罩幕層 102a :圖案化之罩幕層 104 :墊氧化層 106 :墊氮化層 108 :溝槽 110 :第一介電層 112 :第一導體層 114 :第二介電層 116、116a :第二導體層 118 :摻雜區 121A through 1 are schematic cross-sectional views showing a method of manufacturing a memory according to an embodiment of the invention. X [Main component symbol description] 100 · Substrate 102 : mask layer 102a : patterned mask layer 104 : pad oxide layer 106 : pad nitride layer 108 : trench 110 : first dielectric layer 112 : first conductor Layer 114: second dielectric layer 116, 116a: second conductor layer 118: doped region 12