1327011 玖、發明說明： 【發明所屬之技銜領域】 本發明係大致有關相位-振幅調變（例如qam或QPSK)傳輸 信號產生之領域。更具體而言，本發明提供了一種使用鎖 相迴路（Phase Locked Loop ;簡稱PLL)來驅動功率放大器 (Power Amplifier ;簡稱PA)之相位-振幅調變器，其中係由 正父或極性輸入信號提供相位及振幅，因而為無線通訊提 供了一種低成本且高功率效率的傳輸解決方案。 【先前技術】1327011 发明, INSTRUCTION DESCRIPTION: FIELD OF THE INVENTION The present invention relates generally to the field of phase-amplitude modulation (e.g., qam or QPSK) transmission signal generation. More specifically, the present invention provides a Phase-Amplitude Modulator that uses a Phase Locked Loop (PLL) to drive a Power Amplifier (PA), which is a positive or negative input signal. Providing phase and amplitude provides a low cost, high power efficiency transmission solution for wireless communications. [Prior Art]
早自1950年代，發射機技術中即實施了一種“包線消除及 恢復采構’主要是為了提高射頻功率放大器的效率。 Leenaem等人所著的“Circuit ⑹如 for RFSince the 1950s, the implementation of a "wire-band elimination and restoration" in transmitter technology has been mainly to improve the efficiency of RF power amplifiers. Leenaem et al. "Circuit (6) such as for RF
TranSCeivers’’（ISBN 0-7923-7551-3)中詳細說明了 此種架 構。圖1所不之孩架構提供了一種在功率放大器級中加入振 幅資訊的傳統方法之替代方法。 傳統的正交相移調變（Quadrature Phase SMft Keying ;簡 稱QPSK)及正交振幅調變（Quadrature八—川滅 Modulation ;簡稱qam)包含圖2所示之一正交I/Q調變器、 一向上變頻器、及一線性射頻功率放大器。需要有一高線 性射頻功率放大器，且在天線之前需要一高階且低耗損的 帶通濾波器，用以去除因向上變頻而產生的邊帶信號。這 兩種組件都是高成本的，且都會造成低功率效率。 因此，目前需要提供能作出成本較低且功率效率較高的 QPSK及QAM信號發射機以供無線應用之調變裝置。 85265 1327011 【發明内容】 本發明之調變器使用一鎖相迴路（PLL)的輸出來驅動功率 放大器（PA)。因為該PLL的連續相位，所以該pll輸出的頻 譜包含極低的亂真功率。該P A輸出的調變加入了振幅資訊， 因而合成了相位-振幅。在本發明的結構中，利用輸入信號 的相位來產生輸入到該PLL的相位檢波器（Phase Detector ; 簡稱PD)之中頻信號。該PLL的輸出係連接到該pa。然後利 用輸入信號的振幅來調變該PA的增益，以便合成射頻輸出。 【實施方式】 請參閱各圖式，圖3示出本發明的一第一實施例。在該實 施例中’係使用一採用類比至數位轉換器（A/D)( 1 0)及（1 2) 以及相移架構（1 4)的正交調變器而利用I/Q基頻帶向量來產 生一精確的相位調變載波中頻（IF)。然後將該正交調變器所 產生的中頻饋入一 PLL的相位檢波器（PD)( 16)之基準相位輸 入端。低通濾波器（LP)( 18)調整該PD的輸出信號。在回授 迴路中混合振益器頻率（Oscillator Frequency ;簡稱OF)信 號，且電壓控制振盡器（Voltage Controlled Oscillator;簡稱 VCO)(20)的輸出端產生係為IF + 0F的總和信號之一經向上 變頻的頻率，而且保留了該等I/Q信號的原始相位資訊。該 信號然後驅動一 PA(22) ^係配合一低通諧波濾波器（23)而使 用一非線性的PA，此種方式取代了一成本較高的高階帶通 濾波器，而利用了該PLL的較純淨之輸出頻譜。 輸入信號的振幅資訊在本質上係與向量I+Q的大小成正 比，且係由增益變化或替代實施例中之輸出軌而在該PA中 85265 1327011 汶振幅資訊纟圖3所不之實施例巾，—振幅產生器^ $) 決定該等⑽轉換器的輸出之振巾H為大部分的PA具有 變動的增益及線性特性’所以在圖3所示之實施例中提供了 ㈣的閉迴路㈣m振幅檢波器（adet)(24)(在各 實施例係被實施為一射頻二極體）及—類比轉移函數 (G(s))(26)(在各實施例係被實施為一運算放大器）來執行上 述的閉迴路控制》 對於圖3所示之Ι/Q架構而言’該pLL的調變信號包含振幅 資訊。對於諸如QPSK等的某些調變類型而言，該振幅可暫 時變為接近零。為了避免在相位轉變期間由失落的相位邊 彖所引發的潑/賤（splash) ’ Ι/Q載波轉變路徑應避免“零，，或“接 近零的振幅。例如，自圖7所示的a點轉變為B點時，會暫 時在中頻中產生一個零振幅。在該圖中，rl*pi/4卩”民的 必然不是零之最小載波振幅，且r2是不會交越原點的一 QPSK(在本門技術中被稱為偏移QPSK(〇ffset qPSK))中的一 改變後跡線之最小載波振幅《將該UQ向量修改成在原點附 近’因而至少有一個最小的大小Γ2 ^本發明的最佳採用方 式是使用Offset QPSK或替代的QAM、GMSK、或其他非零 交越的調變技術。 圖4a示出更適於矽晶片實施的本發明之一第二實施例。 在所示實施例中’完全不使用該等Ι/Q向量，因而不需要用 於Ι/Q類比信號之A/D轉換器《係使用極性形式的相位-振幅 資訊，亦即相角及大小。一直接數位合成器（Direct-Digital Synthesizer ;簡稱DDS)(28)接收相位信號，並產生要提供 85265 •8- 1327011 給各PLL元件（PD(16)、LP(18)、及VC〇（20))之中頻信號。 圖4b示出以該第二實施例，其中係以一脈寬調變器（Pulse Width Modulator;簡稱PWM)(28')取代DDS，而提供相位之 數位合成，以便產生用於PLL的中頻信號。在圖4c所示之另 一實施例中，係使用一第二PLL(28”）來取代該DDS。係將 該DDS或替代的一PWM或第二PLL、以及PLL的PD、LP、 及VCO組件置於積體電路（IC)(30)中。 圖5所示之實施例強化了本發明可能達到的成本降低，其 方式為使用1C中之一脈寬調變器（PWM)(32)來整合振幅調變 功能，因而在將數位振幅資訊施加到電路之前無須先將該 數位振幅資訊轉換為類比信號。 圖6示出一替代實施例，其中係在1C中實施用於PA控制的 振幅偵測及轉移函數產生之組件。ADET(34)自PA接收信 號，並經由A/D(3 6)而傳送該ADET(3 4)之輸出。在一數位函 數產生器（T(z))(38)中將該數位化後之信號與振幅混合，然 後將混合後的信號經由數位至類比轉換器（D/A)(40)傳送， 以便提供PA之回授信號。 對於諸如PA增益調變的替代方式等的其他實施例而言， 亦可以下列方式完成振幅調變：改變PA電晶體上的電源供 應電壓；改變輸入匹配參數或使用一射頻衰減器。此外， 使用 圖 4d 所示之公式 Phase = Arctan(Q/I)、 Amplitude = SQRT(I2 + Q2)，而自原始的I/Q信號推導出相位及 振幅以維持頻譜要求，即可實現頻譜整形。此外，亦可在PLL 的低通遽波器中執行對相位的部分滤波。 85265 1327011 對圖3所示本發明的一實施例之SpicE模擬證實了該電路 的功政。在圖8所示之模擬中，如跡線（42)所示，該模型中 之載波頻率是19〇〇 MHz，且具有1 MHz的一 QPSK符號速 率。為了示出採用本發明的調變之傳真度，係將所示圖形（44) 中提供的基頻帶I/Q振幅之輸入信號與圖中示為信號（46)的 孩1900 MHz載波所形成之振幅包線比較。 至此已按照專利法規要求之方式詳細說明了本發明，但 熟習此項技術者當可了解，尚可對本文所揭示的特定實施 例作出各種修改及替換。此類修改仍係在下文的申請專利 範圍所界定的本發明之範圍及意圖内。 【圖式簡單說明】 若參照上文中之詳細說明，並配合各附圖，將可更易於 了解本發明的上述這些及其他的特徵及優點，這些附圖有： 圖1是先前技術的包線消除及恢復技術之一示意圖； 圖2是一傳統的qPSk/QAM發射機之一示意圖； 圖3是採用正交相位及振幅資訊的本發明第一實施例之一 示意圖； 圖4a是採用極性相位及振幅信號資訊且具有用於中頻信 號產生的一直接數位合成器的一第二實施例之一示意圖； 圖4b是採用極性相位及振幅信號資訊且具有用於中頻信 號產生的一脈寬調變器的該第二實施例之一示意圖； 圖4c是採用極性相位及振幅信號資訊且具有用於中頻信 號產生的一鎖相迴路的該第二實施例之一示意圖； 圖4d是展現對極性相位及振幅信號資訊的i/q信號進行基 85265 • 10- 1327011 頻帶濾波以供頻譜整形的該第二實施例之一示意·圖； 圖5是極性向量實施例的一替代實施例之一示意圖； 圖6是採用本發明的一完全整合式極性向量調變器的一第 二替代實施例之一示意圖； 圖7是本發明一實施例的QPSK振幅之一正交圖形；以及 圖8是在使用根據本發明的圖3所示實施例的一多模調變 器的一 SPICE模擬中之載波及包線資料以及所得到的信號輸 出之一資料圖形。 【圖式代表符號說明】 10，12, 36類比至數位轉換器 14 相移架構 16 相位檢波器 18 低通滤波器 20 電壓控制振盪器 22 功率放大器 23 低通諧波濾波器 15 振幅產生器 24, 34 振幅檢波益 26 類比轉移函數 28 直接數位合成器 28’，32 脈寬調變器 2 8” 第二鎖相迴路 30 積體電路 38 數位函數產生器 85265 -11 1327011 40 數位至類比轉換器 42 跡線 44 圖形 46 信號 -12- 85265Such a structure is described in detail in TranSCeivers' (ISBN 0-7923-7551-3). The architecture of Figure 1 provides an alternative to the traditional method of adding amplitude information to the power amplifier stage. The conventional Quadrature Phase SMft Keying (QPSK) and Quadrature Amplitude Modulation (Quadture VIII-Modulation; qam) include one of the orthogonal I/Q modulators shown in Figure 2, Upconverter, and a linear RF power amplifier. A high-line RF power amplifier is required, and a high-order, low-loss bandpass filter is required in front of the antenna to remove sideband signals due to upconversion. Both components are costly and result in low power efficiency. Therefore, there is a need to provide a modulation device that can make QPSK and QAM signal transmitters that are less costly and more power efficient for wireless applications. 85265 1327011 SUMMARY OF THE INVENTION The modulator of the present invention uses a phase-locked loop (PLL) output to drive a power amplifier (PA). Because of the continuous phase of the PLL, the spectrum of the pll output contains very low spurious power. The modulation of the P A output incorporates amplitude information, thus synthesizing the phase-amplitude. In the configuration of the present invention, a phase detector (Phase Detector; PD for short) intermediate frequency signal input to the PLL is generated using the phase of the input signal. The output of the PLL is connected to the pa. The amplitude of the input signal is then used to modulate the gain of the PA to synthesize the RF output. [Embodiment] Please refer to the drawings, and Fig. 3 shows a first embodiment of the present invention. In this embodiment, the I/Q baseband is utilized using a quadrature modulator using analog to digital converters (A/D) (10) and (1 2) and a phase shifting architecture (14). The vector produces an accurate phase modulated carrier intermediate frequency (IF). The intermediate frequency produced by the quadrature modulator is then fed to the reference phase input of a phase detector (PD) (16) of a PLL. A low pass filter (LP) (18) adjusts the output signal of the PD. The oscillator frequency (Oscillator Frequency; referred to as OF) signal is mixed in the feedback loop, and the output of the Voltage Controlled Oscillator (VCO) (20) generates one of the sum signals of the IF + 0F. The frequency of the upconversion, and retaining the original phase information of the I/Q signals. The signal then drives a PA (22) to cooperate with a low pass harmonic filter (23) and uses a non-linear PA, which replaces a higher cost high order bandpass filter and utilizes this The purer output spectrum of the PLL. The amplitude information of the input signal is essentially proportional to the magnitude of the vector I+Q, and is changed by the gain or the output track in the alternative embodiment. In the PA, the 85265 1327011 amplitude amplitude information is not shown in FIG. The towel, the amplitude generator ^ $) determines the output of the (10) converter, the wiper H has a variable gain and linearity for most of the PA'. Therefore, in the embodiment shown in Fig. 3, a closed loop of (4) is provided. (d) m amplitude detector (adet) (24) (implemented as a radio frequency diode in each embodiment) and analog shift function (G(s)) (26) (implemented as an operation in each embodiment) Amplifier) to perform the closed loop control described above. For the Ι/Q architecture shown in Figure 3, the modulated signal of the pLL contains amplitude information. For some modulation types such as QPSK, the amplitude can temporarily become close to zero. In order to avoid the splash/’/Q carrier transition path caused by the missing phase edge during the phase transition, "zero," or "near zero amplitude" should be avoided. For example, when changing from point a to point B shown in Fig. 7, a zero amplitude is temporarily generated in the intermediate frequency. In the figure, rl*pi/4卩"min is not necessarily the minimum carrier amplitude of zero, and r2 is a QPSK that will not cross the origin (in this technology, it is called offset QPSK (〇ffset qPSK) The minimum carrier amplitude of a changed trace in the )) "modifies the UQ vector to be near the origin" and thus has at least one minimum size ^ 2 ^ The best use of the invention is to use Offset QPSK or alternative QAM, GMSK Or another non-zero crossover modulation technique. Figure 4a illustrates a second embodiment of the present invention that is more suitable for use in a silicon wafer implementation. In the illustrated embodiment, the Ι/Q vectors are not used at all, thus There is no need for an A/D converter for Ι/Q analog signals. It uses phase-amplitude information in the form of polarity, ie phase angle and size. A Direct-Digital Synthesizer (DDS) (28) Receiving the phase signal and generating an intermediate frequency signal to provide 85265 •8-1327011 to each of the PLL elements (PD(16), LP(18), and VC〇(20)). Figure 4b shows the second embodiment. , in which a Pulse Width Modulator (PWM) (28') is substituted for DDS, and the phase is provided. The digital synthesis to produce the intermediate frequency signal for the PLL. In another embodiment of the embodiment shown in FIG. 4c, a system using a second PLL (28 ") instead of the the DDS. The DDS or an alternate PWM or second PLL, and the PD, LP, and VCO components of the PLL are placed in an integrated circuit (IC) (30). The embodiment shown in Figure 5 enhances the cost reduction that can be achieved by the present invention by integrating a amplitude modulation function using a pulse width modulator (PWM) (32) in 1C, thus applying digital amplitude information. It is not necessary to convert the digital amplitude information into an analog signal before going to the circuit. Fig. 6 shows an alternative embodiment in which the components for amplitude detection and transfer function generation for PA control are implemented in 1C. ADET (34) receives the signal from the PA and transmits the output of the ADET (34) via A/D (3 6). The digitized signal is mixed with amplitude in a digital function generator (T(z)) (38), and then the mixed signal is transmitted via a digital to analog converter (D/A) (40) so that Provide a feedback signal for the PA. For other embodiments, such as alternatives to PA gain modulation, amplitude modulation can also be accomplished in the following manner: changing the power supply voltage on the PA transistor; changing the input matching parameters or using a radio frequency attenuator. In addition, spectral shaping can be achieved by using the equations shown in Figure 4d, Phase = Arctan(Q/I), Amplitude = SQRT(I2 + Q2), and deriving the phase and amplitude from the original I/Q signal to maintain the spectral requirements. . In addition, partial filtering of the phase can also be performed in the low pass chopper of the PLL. 85265 1327011 The SpicE simulation of an embodiment of the invention shown in Figure 3 confirms the power of the circuit. In the simulation shown in Figure 8, as shown by trace (42), the carrier frequency in this model is 19 〇〇 MHz and has a QPSK symbol rate of 1 MHz. To illustrate the modulation of the facsimile using the present invention, the input signal of the baseband I/Q amplitude provided in the pattern (44) shown is formed by the 1900 MHz carrier shown as signal (46). Amplitude envelope comparison. The present invention has been described in detail in the light of the appended claims, and it is understood by those skilled in the art that various modifications and changes can be made to the specific embodiments disclosed herein. Such modifications are still within the scope and intent of the invention as defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages of the present invention will become more readily apparent from the <RTIgt; Figure 2 is a schematic diagram of a conventional qPSk/QAM transmitter; Figure 3 is a schematic diagram of a first embodiment of the present invention using quadrature phase and amplitude information; Figure 4a is a polar phase And a schematic diagram of a second embodiment of amplitude signal information and having a direct digital synthesizer for IF signal generation; FIG. 4b is a pulse width information for polar phase and amplitude signal and having a pulse width for IF signal generation A schematic diagram of the second embodiment of the modulator; FIG. 4c is a schematic diagram of the second embodiment using polar phase and amplitude signal information and having a phase locked loop for intermediate frequency signal generation; FIG. 4d is a representation The i-q signal of the polar phase and amplitude signal information is subjected to a base 85265 • 10- 1327011 band filtering for spectrum shaping. FIG. 5 is a polar orientation. A schematic diagram of an alternative embodiment of an embodiment; FIG. 6 is a schematic diagram of a second alternative embodiment of a fully integrated polar vector modulator employing the present invention; FIG. 7 is a QPSK amplitude of an embodiment of the present invention. An orthogonal pattern; and FIG. 8 is a data pattern of carrier and envelope data in a SPICE simulation using a multimode modulator of the embodiment of FIG. 3 in accordance with the present invention and the resulting signal output. [Description of Symbols] 10,12, 36 analog to digital converter 14 Phase shift architecture 16 Phase detector 18 Low pass filter 20 Voltage controlled oscillator 22 Power amplifier 23 Low pass harmonic filter 15 Amplitude generator 24 , 34 amplitude detection benefit 26 analog transfer function 28 direct digital synthesizer 28', 32 pulse width modulator 2 8" second phase locked loop 30 integrated circuit 38 digital function generator 85265 -11 1327011 40 digital to analog converter 42 Trace 44 Graphic 46 Signal-12- 85265