TWI326452B - Method for detecting word line leakage in memory devices - Google Patents

Description

Sanda number: TW369卯A IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a 1C)' and particularly relates to a method and apparatus. Integral circuit (integrated circuit, # IC memory device leakage current test [prior art] Figure _1 - a functional block diagram of a traditional memory device. As shown in Figure 1, the heart is not The device 1 includes a word line power generator (9) and a plurality of zfell 11G, ill.....119, and the word line power generator 1〇1 is connected to each memory area. In operation, the word line power supply H 101 will provide the desired power of the word line, such as the read voltage level required for the read operation. As is well known, there is often leakage in the memory element. State, which often judges the leakage state by monitoring the power consumption of the memory component. However, there are still many limitations and inconveniences in the conventional technology, so an improved technique for memory leakage testing is currently required. SUMMARY OF THE INVENTION The present invention relates to an integrated circuit (IC), and more particularly to a method and apparatus for leakage current testing of an ic memory device. The present invention provides a monitoring memory component only by way of example.Current (cell current) technique, thereby detecting a state of the word-line leakage defects caused by the process. In addition, the scope of application of the present invention is extremely wide 1,326,452

Three-sided: TW3699PA The other leakage state in the memory component, which can be applied, for example, to testing. The method for extracting word line leakage in a phase memory component is provided by the present invention. The method comprises: connecting a plurality of first word lines in a memory component to a plurality of second word lines in a voltage source sub-coupled body component To the grounding level of quasi-snow, Yi · Zhongming ^ a complex r, eight - Yu Yuan line adjacent to the first character line one of which corresponds to the first character 狳.丄 ^ The method includes waiting for a first predetermined time to make the first character lines

The listener reaches a predetermined voltage level, such as the desired word line voltage level above the memory read 柽#. And, after the sub-element lines reach a predetermined voltage level, the first word lines are separated from the voltage source. Second, the first word line is discharged after a second predetermined time. At this time, the word line voltage level will decrease due to intrinsic leakage or extrinsic leakage, such as junction leakage, and external leakage is, for example, process defect ( Process defect). Thereafter, the method includes detecting a memory component current corresponding to the first word lines and comparing the current to a predetermined reference current. The predetermined reference current is used to identify the leakage state corresponding to the first word lines. The method further includes determining whether the word line leakage state exists. For example, if the current measured by the Russian system is lower than the predetermined reference current, it is determined that the word line leakage state exists. An example of this embodiment is shown in Figures 1 - 3 . The first word line and the second word line are selected from a memory array of a memory element. The memory array is, for example, lightly coupled to a voltage source via an array select switch. As shown in Fig. 2, 'each of the first word lines and each screaming number 452'

Erda number: TW3699PA ^The two-character line includes a word line driving device, which is coupled to a voltage source or a ground level voltage, which is known, for example, using conventional techniques and known in the art. Decoding circuit (dec〇ding circuit). In the example of the first, seventh figure, the first word line includes a plurality of even numbers of memory elements = 疋 lines, and the second word lines include a plurality of odd digital elements of the memory element. 'Line. The step of detecting current includes performing a memory read operation to determine a memory component current corresponding to the first word line. The parameters used for testing are used under specific test conditions. For example, when the second predetermined time is selected, the voltage corresponding to the first word lines can be discharged, and the characters can be identified. Line leakage state. According to the leakage detection standard and the capacitance of the word line, the second predetermined time is about 丨 microseconds (# s e c) to 200 microseconds. When the predetermined reference current is selected, it is higher than the intrinsic leakage current corresponding to the first sub-line and conforms to the operating range of the sense amplifier. This predetermined reference current is, for example, about 10 microamperes (# A). According to another embodiment, the present invention provides a method of detecting leakage of a word line in a memory device, wherein the memory element includes a plurality of word lines. The method includes selecting one of a plurality of word lines of the suffix element as a first sub-element, and coupling the first word line of the memory element to the voltage source 'and The remaining word lines are grounded. The method includes waiting for a -first predetermined time for the first word line to reach a predetermined read voltage level. The method includes separating the first word line from the voltage source, and lightly connecting the first word το line to a floating voltage terminal (f〇ating v〇hage terminal), and after a second predetermined time A word line can be placed 8

Three-face number: TW3699PA electricity. The method includes detecting a memory component current corresponding to the first word line, and comparing the current with a predetermined reference current to verify a word line leakage state, wherein the predetermined reference current is used to identify a word The leakage state of the yuan line. The method further includes determining whether the word line leakage state exists. In this embodiment, the word lines are coupled to the voltage source via an array select switch. The step of coupling the first word line to the voltage source includes turning on a word line select switch. In this embodiment, the step of coupling the first word line to the floating voltage terminal includes coupling one of the first word line to a closed state of a metal oxide half field effect transistor (MOSFET). According to the leakage detection standard and the capacitance of the word line, the second predetermined time is about 1 microsecond (//sec) to 200 microseconds. Its predetermined reference current is approximately 10 microamperes (//A). An example of this embodiment is shown in Figures 14-17. According to still another embodiment, the present invention provides a method of detecting leakage of word lines in a memory device. The method includes coupling one or more word lines in the memory element to a voltage source, and coupling at least one corresponding word line adjacent to the one or more word lines to a ground voltage. The method includes waiting for a first predetermined time to separate the one or more word lines from the voltage source after the one or more word lines have reached a predetermined read voltage level. The method includes waiting for a second predetermined time to cause the one or more of the word lines to be discharged. Then, the voltage corresponding to the one or more word lines is compared with a reference voltage, wherein the reference voltage is used to identify a leakage state of one of the one or more word lines. The method further includes determining whether the word line leakage state exists. As shown in FIG. 5, the memory component includes a switching component and a comparator circuit. This switching element 1326452

Sanda number: TW3699PA responds to a memory leakage test command signal to couple one or more word lines of a memory component to a voltage source or comparator circuit. In this embodiment, the memory component includes a plurality of memory arrays, and further includes a switching element corresponding to each of the memory arrays and a comparator circuit. Each of the switching elements is responsive to a memory leakage test command signal to couple one or more word lines of the corresponding memory array to the voltage source or comparator circuit. An example of this embodiment is shown in Figures 4-9. The present invention has many advantages over conventional techniques. For example, the method of the present invention is more convenient to use than the conventional technology. The method of the embodiment of the present invention can detect the leakage state of the word line of the memory under the condition that the conventional technology is difficult to detect. The technique of the present invention can detect the word line leakage state through the comparison memory read current and the predetermined reference current, and can detect the leakage state corresponding to the plurality of word lines or the single word line. Alternatively, the word line leakage state can be tested by monitoring the word line voltage level. Here, the advantages of the present invention will be described in detail in the following description, and the present invention will be more apparent. In order to make the above-mentioned contents of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings will be described in detail as follows: [Embodiment] The present invention relates to an integrated circuit (integrated circuit) , IC), and in particular, a method and apparatus for leakage current testing of a 1C memory component. The present invention proposes, by way of example only, a technique for monitoring a cell current in a memory element, whereby the debt measurement is caused by a process defect 10 1326452

Sanda number ·- TW3699PA Word line leakage state. In addition, the application range of this issue is very wide. For example, it can be applied to the test of other leakage states in IC memory components. • 'The memory component (10) in Figure 1 referenced above is traditionally hunted by monitoring the power loss of its device' to detect the leakage of the memory • g. However, according to an embodiment of the present invention, the memory element tends to have a leakage current, which is caused, for example, by an inherent junction leakage c_nt. A certain level of leakage current, such as standby leakage current (zero ieakawent), is often acceptable. In contrast, the leakage state caused by defects is necessary for identification. This is because when there is a high impedance after the leakage circuit, the leakage current caused by the defect is larger than the essential leakage current. In the conventional technology, it is still impossible to distinguish the leakage state caused by the essential leakage state and the defect. Therefore, there is an improved technology for memory leakage (4). Fig. 2 and Fig. 3 are simplified diagrams showing the leakage state of the word line of the memory element in accordance with the embodiment of the present invention. The drawings are for illustrative purposes only and are not intended to limit the scope of the scope of the application, and those of ordinary skill in the art should understand that they can make various changes and modifications. In addition, similar reference numerals and elements in the drawings should be the ordinary knowledge in the technical field of the present invention, and the functions thereof will not be described again. Referring to Figure 2, there is shown a simplified schematic diagram of a s-remember element of a % example in accordance with the present invention. As shown in FIG. 2, the ="fe' body element 200 includes one or more memory arrays, such as a memory area (Sector) 0, ..., a memory area (Sect〇r) n, ie 210 ... .. 290. For example, memory area 210 includes a word line driver 1326452

Sanda number: TW3699PA 211, word line WL 0 (212), word line driver 213, and word line WLO (214). The word line driver 211 is coupled to the word line 212, and the line driver 213 is coupled to the word line 214. An array selection switch 222 is coupled to the memory area 0..... memory area N, and the array selection switch 222 is, for example, a gold oxide half field effect transistor (MOSFET). In Fig. 2, the array selection - switch 222 responds to a command signal SECB and connects the memory area 〇..... memory area N to a voltage source PWR (220). Referring to FIG. 3, a simplified schematic diagram of the memory device 300 in a leakage state in accordance with an embodiment of the present invention is shown. As shown in FIG. 3, the word line driver 311 is coupled to the word line 312, and the word line driver 313 is coupled to the pre-element 314. In FIG. 3, 'the two leakage paths corresponding to the word line 312 are displayed. One of the leakage paths exists between the word line 312 and the substrate, and the other leakage path exists in the word line 312. Between the word line 314 adjacent thereto. The conventional technology detects a leakage current through a tester to monitor the leakage current from the supply voltage to the ground. However, in some cases, this leakage current will not exceed the essential leakage of the word line driver benefit, such as the junction leakage of the word line driver. For example, if there is a path of impedance between the word lines, then the leakage current will be comparable to the junction leakage of the word line. Secondly, it is more difficult to detect the existence of the leakage state of the word line by the traditional test method. Therefore, there is an urgent need for an improved technique for memory leakage testing. Figure 4 is a simplified schematic diagram of a memory component in a leakage test in accordance with an embodiment of the present invention. The drawings are for illustrative purposes only and are not intended to limit the scope of the patent application, and the general knowledge of the technical field 12 1326452

Sanda number: TW3699PA should understand that it can be used for various changes and retouching. As shown in Fig. 4, the memory element 400 includes a plurality of memory areas, ..., memory areas n, which are ... 410 ..... 490. For example, memory area 410 includes a word line driver 411, word line 412, word line driver 413, and word line 414. The word line driver 411 is lightly connected to the word line 412, and the word line driver 413 is connected to the word line 414. An array selection switch 422 is coupled to the memory area .0..... memory area N, and the array selection switch 422 is, for example, a MOSFET. In the embodiment of Figure 4, array select switch 422 is a p-channel MOSFET device (PM0S) whose gate terminal is connected to a ground voltage level (GND). The memory component 400 also includes a power supply 42A, a comparator circuit 430, and a test switching component 421. The test switching element 421 connects the memory areas to the power source 42 or one of the input terminals 432 of the comparator circuit 430 in accordance with a command signal (not shown). In this embodiment, the present invention provides a method of testing memory 400. The method includes connecting the memory array including the memory area n, ..., memory area n to the power source 420 for a predetermined time by using the test switching element 421, thereby charging the selected word line in the memory array to a The voltage level PWR, which is, for example, a read voltage level. In the test state, these adjacent word lines are respectively biased to the power waste level (pwR) or ground level (GND) of the power supply. For example, in Figure 4, word line 412 is coupled to voltage level PWR and word line 414 is coupled to ground level GND. Next, the just-tested switching element 421 connects the memory array to the input terminal 432 of the comparator circuit 43A. Then, after the voltages of the word lines are deactivated at a specific time, the voltage levels of the word lines are tied to the input terminal 432 and a reference 13 1326452.

Sanda number: TW3699PA Voltage level Vref (431) for comparison. Thus, the leakage state can be discriminated. The details of this method will be described in detail later. Figure 5 is a schematic illustration of a memory component in a leakage test in accordance with another embodiment of the present invention. The drawings are for illustrative purposes only, and are not intended to limit the scope of the patent application, and those of ordinary skill in the art will recognize that the invention can be modified. As shown in Figure 5, memory component 500 is similar to memory component 400. In Figure 5, each memory region of memory component 500 includes an array select switch and a test switch component. For example, an array selection switch 522 and a test switching element 521, an array selection switch 524 and a test switching element 523 correspond to the memory area N (ie, 590), and the test switching elements respectively connect the memory areas. To power supply 520 or input 532 of comparator circuit 530. In this example, the present invention provides a method of testing memory 500 that is similar to the method illustrated in Figure 4 above, and similarities thereof are not described again. The method of testing memory 500 includes causing the memory arrays to be discharged after being charged to a read voltage level and compared to a reference voltage level Vref. Since each memory area has an array selection switch and a test switching element, each memory area can be individually tested. Figure 6 is a schematic diagram of a word line leakage test method for a memory device in accordance with an embodiment of the present invention. In Figure 6, memory areas 510..... 590 are charged to a certain level of read voltage level and are coupled to input 532 of comparator circuit 530. The method for discriminating the leakage state will be described in detail below with reference to Figs. 7 and 8. 14 1326452

Sanda number: TW3699PA Figure 7 is a schematic diagram of the leakage test method for the character line in Figures 5 and 6. As shown in Figure 7, capacitor 740 (Ct()tal) represents the total capacitance of the word line corresponding to the test. In Fig. 7, when the word line is charged to a predetermined voltage level and ready to be discharged, the portion indicated by the broken line I leakage in the figure represents a potential leakage current path 742. Figure 8 is a graph showing the voltage versus time of the word line leakage test method of Figures 5 and 6, which plots the voltage level versus time as the voltage is discharged. For example, in FIG. 8, a solid line 803 represents a curve of a memory array having an essential junction leakage when the voltage is discharged with time, and a broken line 804 represents a memory array having a word line leakage state and an essential junction leakage at the same time. The curve when the time is discharged. Initially, the solid line 803 and the dashed line 804 are both at voltage 801. After a predetermined time 805 (i.e., the Detection time of Figure 8), the dashed line 804 is lowered below the solid line 803, which is indicative of the effect of the leakage state of the word line. Thus, the word line voltage level and the reference voltage level 802 can be compared at a predetermined time 805 to identify the leakage state. In an embodiment of the invention, the reference voltage level 802 and the predetermined time 805 are selectively variable with the leakage state to be monitored. Figure 9 is a flow chart showing a method of character line leakage test of a memory device in accordance with an embodiment of the present invention. The drawings are for illustrative purposes only and are not intended to limit the scope of the patent application, and those skilled in the art will recognize that the invention can be modified. Please refer to Figure 9, the method can be briefly listed as follows. 1. (Step 910) coupling the word line to the voltage source; 15 1326452

'Sanda number: TW3699PA - 2. (Step 920) Wait for the word line to reach the read voltage level; 3. (Step 930) separate the word line and voltage source; • 4. (Step 940) Wait for the word line Discharge; * · 5. (Step 950) compare the word line voltage and the reference voltage; and 6. (Step 960) discriminate the word line leakage state. The method shown in Fig. 9 will be described in detail below with reference to Figs. 4-8. In step 910, the method includes coupling one or more of the memory elements to a voltage source. In the embodiment of Figures 4-6, such word line % can be selected in different ways. For example, in the memory device 400 of FIG. 4, when a word line is to be selected from each memory area, the word line 412..... of the memory area 0 is switched to the memory area N by the switching element 421. The word line 492 is connected to a voltage source 420. In another example, the memory element 500 of FIG. 5 is to select a word line from one of the memory areas for the leakage current test, and the word line 512 of the memory area 0 is used by the switching element 521. Connected to voltage source 520 for testing, and subsequently tested to word line 592 of memory region N in succession. However, in another example shown in Figure 6, it is possible to select more than one word line at the same time for testing. These selected word lines are, for example, coupled to a voltage source PWR, which is 420 of FIG. 4 and 520 of FIG. According to the embodiment of Figures 4-6, the method includes grounding certain word lines to which the selected word line is to be adjacent, thereby effectively testing the leakage state between the word lines. In step 920, the step includes waiting for a first predetermined time to cause the one or more word lines to reach a predetermined read voltage level. The predetermined voltage level is, for example, the read voltage level of the memory operation 16 1326452

• No.: TW3699PA (Read level)' It can of course be other suitable 34 steps 930' The method includes separating the word line and the electrical plane. Next, in step 940, the method includes waiting - a second predetermined time: to cause the character ς to be discharged. After that, in the (four) 95G towel, the method "will correspond to the character

Line-Calculation: Refer to the electrical line comparison. This reference is used to identify the leakage state of the word line corresponding to the selected 7G line. The comparison method can be performed by a comparison-H circuit, for example, 43G of Fig. 4 and 53A of Fig. 5. This is the reference voltage curve 802 of Figure 8, which can be used to identify the leakage state. In step 96, the method discriminates whether or not the word π line leakage state exists. As shown in Fig. 8, after time 805, the discharge curve 804 indicates that one or more of the word lines have a leakage current corresponding to the curve 8 〇 3 of the reference word line. In summary, different test parameters are used in different test situations. For example, during testing, the first predetermined time for charging the word line, or for example, the reference voltage level and the reference current level determined according to the experiment. According to the leakage detection standard and the capacitance of the word line, the second predetermined time is about 1 microsecond (a sec) to 200 microseconds. When selecting its predetermined reference current, it is south of the fundamental leakage current corresponding to those first word lines and is in accordance with the operating range of the sense amplifier. This predetermined reference current is approximately 1 〇 microamperes (#A). Of course, other parameters can be changed and modified. According to an embodiment of the present invention, a method of leakage of a debt test word line is proposed by the above steps. In summary, the method includes charging the selected word line, waiting for the word line to discharge, and monitoring the voltage of the word line to determine its leakage state. For other changes and modifications, if it is increased 17 1326452

The 'Sanda Number·· TW3699PA' step, the reduction of one or more steps, and the order in which one or more steps are changed shall be considered as the scope of the patent application in the text. Details of the method • The description is described in the full text of the specification, in order to make the method more obvious and easy to understand, its * - detailed description is as follows. Figure 10 is a schematic illustration of a memory component in a leakage test in accordance with another embodiment of the present invention. The illustrations are for illustrative purposes only and are not intended to limit the scope of the patent application, and the general knowledge of the technical field should be understood as a variety of changes and refinements. As shown in Fig. 10, the memory element 1000 includes one or more memory arrays, such as memory area 0 (i.e., 1010) of FIG. The memory area 1010 includes a plurality of word lines and a plurality of word line drivers, wherein each of the word lines is coupled to a word line driver. For example, the word line driver 1011 is coupled to the word line 1012, and the word line driver 1013 is coupled to the word line 1014. An array of select switches 1022 is coupled to the memory region 1010 and a power supply 1020. The array select switch 1022 is, for example, a MOSFET. The array select switch 1022 is coupled to a power supply 1020 in response to a command signal (ie, SEC0B in FIG. 10). In the embodiment of Fig. 10, the memory element may comprise a plurality of memory arrays, and the memory array is divided into a plurality of sectors. In this embodiment, the memory area can be connected to a particular array select switch. It is also possible to have two or more memory arrays connected to an array selection switch. Figure 11 is a timing diagram showing the word line leakage test method in accordance with another embodiment of the present invention. The drawings are for illustrative purposes only and are not intended to limit the scope of the scope of the patent application, and the general knowledge of the technical field 1326452

. Three number: TW3699PA ' should understand that it can be used for a variety of changes and retouching. The method will be described below with reference to the device 1000 of the first drawing. The method includes activating the command signal number SEC0B to connect the memory array 1010 to the power source 1020 for a predetermined time, ** enabling the selected word line in the memory array to be charged up to a voltage level * PWR, the voltage level PWR For example, a read voltage level (Read Level). Under a preferred test condition, these adjacent word lines are biased to the voltage level (pWR) or ground level (GND) of the power supply, respectively. For example, in Figure 10, the even digital line is connected to pwR, • b such as word line WL 0 (i.e., 1012), and the odd digital line is connected to GND, such as 1-ary line WL1 (i.e., 1014). When the selected word line (ie, even digital line) waits for a time Tdelayl and charges to a predetermined voltage level (such as 1^&(11^\^1) in Figure n (as shown in Figure 11) , £]^^^ curve), remove the command signal SEC0B (as shown in Figure 11 at T1 to remove SEC〇B), make the array selection switch 1022 cut from 'ΌΝ' to "〇ff", and wait for a while The word line voltage is discharged, and this period is the range marked between the broken line T1 and the broken line T2 in the πth figure. Secondly, a memory reading operation is started by the command signal READEN. The details of the method of this embodiment will be described in detail. Figure 12 is an IV graph of a character line leakage test method according to an embodiment of the present invention. The drawings are for illustrative purposes only and are not intended to limit the scope of the patent application scope herein. The general knowledge should understand that it can be used for various changes and retouching. As shown in Figure 12, it is based on the read current of the memory array and the word line voltage. Position A represents the word το line voltage is at the maximum reading. Read current at voltage level (ie, Read Level in Figure 12). Position b Table wordline voltage due to the nature of surface 191326452

Sanda number: TW3099PA The cell current IB corresponding to the leakage and a slight decrease. The position C represents the microcurrent Ic corresponding to the word line voltage due to a large drop in the word line leakage caused by the defect. In this embodiment, the reference current level Iref is used to identify the word line leakage state. If the read current is less than Iref, the state of the word line leakage can be identified. Of course, the parameters are for other changes and modifications. The method for testing the leakage state of the word line will be described in detail below with reference to Figures 10-13. Figure 13 is a flow chart showing a method of character line leakage test of a memory element in accordance with another embodiment of the present invention. The drawings are for illustrative purposes only and are not intended to limit the scope of the scope of the patent application, and those of ordinary skill in the art will recognize that various modifications and changes can be made. Please refer to Figure 13, the method can be briefly listed as follows. 1. (Step 1310) connect the selected word line to the supply voltage; 2. (Step 1320) Wait for the selected word line to reach the predetermined read voltage level; 3. (Step 1330) Separate the word line and Voltage source; 4. (Step 1340) Wait for the word line to discharge; 5. (Step 1350) Detect the current of the corresponding word line; 6. (Step 1360) Compare the detected current with the reference current; 7. (Step 1370) Discriminate the word line leakage state. In step 1310, the method includes coupling a plurality of first word lines in the memory element to a voltage source, and coupling the plurality of second word lines in the memory element to a ground level voltage, wherein Each of the second character line lines adjacent to one of the first word lines corresponds to the first word line. According to the invention {20

Number: TW3699PA 1〇 = For example, these words can be selected by not using the method. For example, in the case of the voxel, the even digital line in the memory area is connected to the memory of the memory. In the 10th fiscal year, the selected character line is pure to (4) the source pwR ( P 02G). - In (4), (4) includes waiting - the first predetermined (e.g., the aforementioned Td) to enable the first word line to reach a predetermined 2 voltage level. The predetermined voltage level may be, for example, the voltage level of the memory operation, that is, the read voltage level (ReadLevel) corresponding to the even digital line (evenwl) of the u-th image, "of course, it may be other suitable Voltage (four). In step (10), the (4) includes a separate word line and an electrical waste source. Next, at step mG, the steps include waiting for a second predetermined time (e.g., 11th to 11th) to cause the word line to be discharged. Thereafter, in step 135G, the method package (4) measures the power corresponding to the selected word line "IL in step 1360, the method comprising comparing the detected current with the reference current. This reference current is used to identify the word = line leakage state corresponding to the first word line. In step 丨, this method is the existence of the leakage state of the word line. For example, as shown in Fig. 12, if the detected electric 2 is lower than the reference electric 8Iref, it can be identified as having an external leakage state. As described above, different test parameters are used in different test situations. For example, during testing, the first and second predetermined times for charging the word line, or for example, the reference voltage level and the reference current level determined according to the experiment. In the example, according to the leakage detection standard and the capacitance of the word line, the first pre-emphasis is about [microseconds (#sec) to microseconds. When the predetermined reference current is selected, it is higher than the essential leakage of the corresponding first-character line.

Sanda number: TW3699PA flow, and the operation of the sense amplifier is 10 microamperes ("). This reference 2: the predetermined reference current is about according to the above embodiment, and can be made other changes and modifications. A method for detecting the leakage of a word line is charged by the word line of the total J, and waiting for the word line to be discharged: =, the current corresponding to the selected current is determined by the discrimination and the side sub-line is tested. If it is 増 addition and subtraction; ^ for other changes and repairs or the order of multiple steps, ^ 2 = a step, and a change in the details of the method of the patent in the range of requirements. Obviously easy to understand, its details == Mingshu The full text, in order to make this method more one-way;! 51 is based on the invention of the invention - the actual word line leakage measurement (10). This figure is only used for illustration, not for limiting the library = 2 range Fan 4' and the general knowledge of this technical field ^ Tian understands that it can be used for various changes and retouching. Figure 14 is a schematic diagram of the leakage test of the body of the body according to the present invention. The memory component is just 〇* "With the ability to test character lines separately, the system and memory elements 000 similar evening. As shown in Fig. 14, the memory element 14GG includes - or one. The hidden array' memory array is, for example, memory area 0 (i.e., 1410). Memory ^ 1410 includes a plurality of word lines and a plurality of word line drivers, wherein each of the sub-line lines is coupled to a word line driver. For example, the word line driver ΗΠ is coupled to the word line test selection device, and the word line test selection device includes a PMOS transistor 1412 and an NMOS transistor 1413 ′ in response to the command signal WLSEL ′ and includes an NMOS battery. The crystal 1414' responds to the command signal WLFLOATB. An array of choices to open {' S > 22 1326452

'Sanda number: TW3699PA' The switch 1422 is coupled to the memory area 1410 and a power source 1420, and the array selection switch 1422 is, for example, a MOSFET. The array select switch 1422, when responding to a finger command signal (ie, SEC0B of Figure 14), connects the memory area 1410 to a power source 1420. According to this embodiment, the present invention provides a method of testing the memory of the sub-line leakage of the body element 1400, which is described in detail below. The method includes charging the selected word line in the memory array and grounding the remaining word lines. Next, 'coupled the selected word line to a floating' voltage terminal and discharges it. After a predetermined period of time, a memory reading operation is performed to determine the leakage state. For example, as shown in Fig. 14, the word line WL0 (i.e., 1411) to be tested is selected by turning on the PMOS M12 and turning off the NMOS 1413. Then, by turning off the PMOS 1412, turning on the NMOS 1413, and turning off the NMOS 1414, the word line WL 0 is connected to the floating voltage terminal. Next, word line WL0 (i.e., 1411) is coupled to the NMOS terminal of NMOS 1414 that is turned off. Fig. 15 is a timing chart showing the method of testing the word line leakage of the memory element 1400 of Fig. 14. Fig. 16 is a graph showing the IV curve of the memory element Lu 1400 word line leakage test method of Fig. 14. The method for testing the leakage state of the word line will be described in detail below with reference to Figure 14-17. Figure 17 is a flow chart showing a method of character line leakage test of a memory element in accordance with still another embodiment of the present invention. This illustration is for illustrative purposes only and is not intended to limit the scope of the scope of the patent application, and it is understood by those of ordinary skill in the art that various changes and modifications can be made. Please refer to Figure 17, the method can be briefly listed as follows. 1. (Step 1710) Selecting a plurality of word lines of the memory element 23 2326452

'Sanda number: TW3699PA • One as a first word line; 2. (Step 1720) Coupling the first word line to the voltage source and grounding the remaining • word lines; • - 3. (Step 1730) Waiting for a first predetermined time to bring the first word line to a predetermined read voltage level; 4. (Step 1740) coupling the first word line to a floating voltage terminal; 5. (Step 1750) Waiting for a second predetermined time to cause the first word line to be discharged; • 6. (Step 1760) detecting the current corresponding to the first word line; 7. (Step 1770) comparing the detected current with the predetermined reference current, The predetermined reference current is used to identify the word line leakage state; and 8. (Step 1780) to determine if the word line leakage state exists. In step 1710, the method includes selecting one of the plurality of word lines of the memory element as a first word line. For example, in Figure 14, the word line WL 0 (i.e., 1411) is selected for testing. In step 1720, the method includes coupling the first word line to the voltage source (e.g., the operation of the WLSEL of fifteenth) and grounding the remaining word lines. For example, in Fig. 14, when the word line WL 0 (i.e., 1411) is selected for testing, the word line WL 1 to the word line WL Μ are connected to a ground voltage. In step 1730, the method includes waiting for a first predetermined time to cause the first word line (e.g., the WL0 curve of Figure 15) to reach a predetermined read voltage level (e.g., Read Level of Figure 15). In step 1740, the method includes coupling the first word line to a floating voltage terminal (as in the operation of WLFLOATB in FIG. 15). In step 1750, a second predetermined time is waited for the first character line to be 24 1326452

' Sanda number: TW3699PA

• Discharge, this second predetermined time is for example Tdelay2 in Figure 15. In step 1760, a memory read operation (such as the operation of the READEN of Figure 15) is performed to detect the current corresponding to the first word line. In step 1770, the method includes comparing the detected current to a predetermined reference current, the predetermined reference current being used to identify the word line leakage state. In step 1780, the method includes determining if a word line leakage state exists. As shown in Fig. 16, it shows the different currents corresponding to the word line test. Here, similar to the 12th figure, the detected current is compared with the reference current Iref to determine the leakage. status. In summary, different test parameters are used in different test situations. For example, during testing, the first and second predetermined times for charging the word line, or for example, the reference voltage level and the reference current level determined according to the experiment. According to the leakage detection standard and the capacitance of the word line, the second predetermined time is about 1 microsecond (/z sec) to 200 microseconds. When the predetermined reference current is selected, it is higher than the essential leakage current corresponding to those first word lines and is in accordance with the operating range of the sense amplifier. This predetermined reference current is approximately 10 micro ® amps (# A). Of course, other parameters can be changed and modified. According to an embodiment of the present invention, a method of detecting leakage of a word line is proposed by the above steps. In summary, the method includes charging the selected word line, waiting for the word line to discharge, and monitoring the voltage of the word line to determine its leakage state. For other changes and modifications, such as adding steps, reducing one or more steps, and changing the order of one or more steps should be considered as the scope of the patent application. In summary, although the invention has been disclosed in some preferred embodiments, such as 25 λ 1326452

Sanda number: TW3699PA', but it is not intended to limit the invention. Those skilled in the art having the ordinary skill in the art can make various changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the patent application. isiMyi

Sanda number: TW36WpA [Simple description of the diagram] . ^ The functional block diagram of the traditional memory component. FIG. 2 is a simplified diagram of a memory device in accordance with an embodiment of the invention. FIG. Figure 3 is a simplified schematic diagram of the leakage state of a memory device in accordance with an embodiment of the present invention. • Figure 4 is a simplified schematic diagram of a memory component in a leakage current test in accordance with an embodiment of the present invention. Figure 5 is a simplified schematic diagram of a memory component in a leakage test in accordance with another embodiment of the present invention. FIG. 6 is a simplified diagram showing a method of testing a word line leakage of a memory element in accordance with an embodiment of the invention. ^ Figure 7 is a simplified schematic diagram showing the leakage test method for the word line of Figures 5 and 6. Figure 8 is a graph showing the % voltage versus time of the word line leakage test method of Figures 5 and 6. FIG. 9 is a flow chart showing a method for testing a word line leakage of a memory element according to an embodiment of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified schematic diagram of a memory device in accordance with another embodiment of the present invention. Fig. 11 is a timing chart showing the word line leakage test method of the memory element of Fig. 10. Fig. 12 is a graph showing the IV curve of the word line leakage test method for the memory element of Fig. 10. 27 1326452

&quot; Sanda number: TW3699PA' Fig. 13 is a flow chart showing the method of character line leakage test of the memory element of Fig. 10. </ RTI> Figure 14 is a simplified schematic diagram of a memory element in accordance with a further embodiment of the present invention. Fig. 15 is a timing chart showing the word line leakage test method of the memory element of Fig. 14. Figure 16 is a diagram showing the word line leakage test of the memory element of Figure 14; #图17 is a flow chart showing a method of character line leakage test of the memory element of Fig. 14. [Description of main component symbols] 100, 200, 400, 500, 600, 1000, 1400 · Memory elements; 101: Word line power generators; 110, 111, 119, 210, 290, 410, 490, 510, 590, • 1010, 1410, Sector: memory area; 211, 213 '311, 313, 411, 413, 491, 493, 511, 513, 591, 593, 1011, 1013: word line driver; 212 '214, 312 ' 314 ' 412 ' 414 ' 492 ' 494 ' 512 ' 514, 592, 594, 1012, 1014, WL: word line; 220, 420, 520, 1020, 1420: voltage source; 222, 422, 522, 524, 1022, 1422: array selection switch; 421, 521, 523: test switching element; 28 1326452

Sanda number: TW3699PA '430, 530, 730: comparator circuit; 431, 531, 731, 802, Vref: reference voltage; • 432, 532: input; - 740: capacitor; • 742: leakage current path; 801, PWR: voltage source; 803, 804: curve; 805, Tdelayl, Tdelay2, ΤΙ, T2. B Between; # 1412: P-channel MOS half-field effect transistor; 1413, 1414: N-channel MOS half-field effect Crystal

Gnd : ground voltage;

Ileakage . Electric 沁11·,

Icell, Ιβ, Ic: current,

Iref: reference current;

Real Level: Reads the electric dust; SECB, SEC0B, WLSEL, WLFLOATB, READEN: ® command signals. 29

Claims (1)

1326452 - Sanda number: TW369卯A X. Patent application scope: 1. A method for detecting leakage of a word line in a memory component, comprising: • coupling a plurality of first word lines of the memory component to a voltage • a source coupled to the plurality of second word lines of the memory component to a ground potential. The quasi-voltage, each of the second character lines is adjacent to the first word lines; waiting for a first a predetermined time for the first word lines to reach a predetermined read voltage level; 'separating the first word lines from the voltage source; and waiting for a second predetermined time to cause the first characters The line is discharged; detecting a current corresponding to one of the first word lines; and comparing the current with a predetermined reference current, wherein the predetermined reference current is used to identify one of the first word lines Leakage condition. 2. The method of claim 1, wherein the first word line and the second word line are selected from a memory array in the memory element, the memory array is transmitted through an array A selector switch is coupled to the voltage source. 3. The method of claim 2, wherein each of the first word lines and each of the second word lines comprises a word line driving device, the word line driving device is coupled Connect to the voltage source or the ground level voltage. 4. The method of claim 2, wherein the first word line comprises a plurality of even digital lines of the memory element, the second word lines comprising a plurality of the memory elements Odd digital line. 5. The method of claim 1, wherein detecting the 30 1326452 three-numbered: TW3699PA 'current step comprises performing a memory read operation to detect corresponding coupling of the first words One of the bit lines of one of the current lines. 6. The method of claim 1, wherein the second -* predetermined time is for discharging a voltage corresponding to one of the first word lines to identify the word line leakage state. 7. The method of claim 1, wherein the second predetermined time is about 1 microsecond (/z sec) to 200 microseconds based on the leakage detection standard and the capacitance of the word line. 8. The method of claim 1, wherein the predetermined reference current is higher than an intrinsic leakage current corresponding to one of the first word lines. 9. The method of claim 1, wherein the predetermined reference current is about 10 microamperes (/i A) based on the operating range of the sense amplifier. 10. detecting the characters in the memory component. In the method of line leakage, the memory component includes a plurality of word lines, the method comprising: selecting one of the word lines of the memory element as a first word line, and the word lines The unselected word line is designated as a plurality of second word lines; the first word line coupled to the memory element is coupled to a voltage source, and the second word lines of the memory element are Grounding; waiting for a first predetermined time to enable the first word line to reach a predetermined read voltage level; separating the first word line from the voltage source; 31 1326452 Sanda number: TW3699PA coupled to the first a word line to a floating voltage terminal; waiting for a second predetermined time to discharge the first word line; detecting a current corresponding to the first word line; and comparing the current with a predetermined Reference current, wherein the predetermined reference It should be based on those used to identify one of the first character line word-line leakage state. 11. The method of claim 10, wherein the word lines are coupled to the voltage source via an array selection switch. 12. The method of claim 10, wherein the step of coupling the first word line to the voltage source comprises turning on a word line select switch. 13. The method of claim 10, wherein the step of coupling the first word line to the floating voltage terminal comprises coupling a first word line to a closed state One end of a transistor (M0SFET). 14. The method of claim 10, wherein the second predetermined time is between about 1 microsecond and 200 microseconds, based on the leakage detection criteria and the capacitance of the word line. 15. The method of claim 10, wherein the predetermined reference current is about 10 microamps based on the operating range of the sense amplifier. 16. A method for detecting leakage of a word line in a memory device, comprising: coupling one or more word lines of the memory element to a voltage source, and coupling at least one corresponding adjacent word line to a Grounding voltage; f Death 32 1326452 &quot; Sanda number: TW3699PA ' Wait for a first predetermined time so that the strip or the word lines can reach a predetermined reading voltage level; 'The strip or the strips The word line is separated from the voltage source; -· waiting for a second predetermined time to cause the strip or the first word line of the strip to be discharged; and comparing the voltage of one of the corresponding strips or the strip of characters And a reference voltage, wherein the reference voltage is used to identify a leakage state of one of the corresponding word lines or one of the word lines. 17. The method of claim 16, wherein the memory component comprises a switching component and a comparator circuit, the switching component is responsive to a memory leakage test command signal to couple the strip or the A number of word lines are wired to the voltage source or the comparator circuit. 18. The method of claim 16, wherein the memory component comprises a plurality of memory arrays, the memory component further comprising a switching component corresponding to each of the memory arrays and a comparator circuit, each of the plurality of memory arrays The switching element is responsive to a memory leakage test command signal to couple the strip or the word line corresponding to the memory array to the voltage source or the comparator circuit. 33