JPH1050098A - Semiconductor integrated circuit device, monitoring method for stress test monitor for semiconductor integrated circuit device and stress test for semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can judge whole selection of word lines and whole selection of bit lines, or whole non- selection of word lines without destructing a chip. SOLUTION: A semiconductor integrated circuit device has a memory cell array 1 including respectively memory cells MC connected to word lines WL1-WL4 and bit lines BL1-BL4, and performs operation for arranging potentials VWL1 -VWL4 of the word lines WL1-WL4 simultaneously in a stress test mode used for sereening the memory cell MC. Also, this device is provided with a stress test monitor circuit 2 which detects whether the potentials VWL1 -VWL4 are arranged actually or not when the potentials VWL1 -VWL4 of the word lines WL1-WL4 are arranged simultaneously, and transmits the detected result DS to a pad 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device (EPROM / FLASH-EEPROM) and a one-chip microcontroller incorporating the semiconductor integrated circuit device (EPROM / FLASH-EEPROM).

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit device, a stress test is performed on a cell or a specific transistor. The stress test refers to a cell arbitrarily selected (in the case of a cell, all cells are often selected in consideration of reduction in test time) or a transistor.
This is a test for applying a high potential that causes a stress to the gate, the drain, and the like to check the degree of the deterioration. Stress testing is an important factor among several test items.

Hereinafter, as one example of a stress test,
A gate stress test of the EEPROM cell will be described.
FIG. 19 is a circuit diagram of a cell array of a NOR type EEPROM.

When a gate stress test is performed on the cell A shown in FIG. 19, the bit line BL1 connected to the drain of the cell A is grounded, and the high potential is applied to the word line WL1 which is the control gate of the cell A. Is applied. Thus, a high potential difference can be generated between the control gate and the substrate of the cell A in a state where there is no potential difference between the source and the drain of the cell A. As a result, an electric stress is applied around the control gate of the cell A. In such a stress state, a large electric field is applied to an interlayer insulating film near the control gate, for example, an interlayer insulating film that insulates the control gate from the floating gate. If the insulating property of the interlayer insulating film is originally not good due to the electric field, a phenomenon (punch-through) in which electric charges jump over the interlayer insulating film occurs, or the interlayer insulating film is broken. Such an approach is called electric field screening. That is, the stress test is performed to confirm whether sufficient insulation can be maintained over a long period of time by using electric field screening.

Conventionally, when the device is placed in a stress test mode, cells (all word lines selected or all word lines not selected and all bit lines selected) are properly selected, and an electrical stress is actually applied. There was no means to confirm from outside whether or not there was. In the stress test mode, a cell to which no electric stress has been applied passes the stress test mode without performing a stress test. In order to prevent such a situation, an operation for confirming whether a cell is properly selected in a stress test mode is performed in a factory. This operation is currently performed by placing a needle on the word line WL or the bit line BL and measuring the voltage of the word line WL or the bit line BL.

However, according to this method, since the chip itself is damaged, the cell is destroyed and the word lines WL, WL,
This causes a problem such as disconnection of the bit line BL and also significantly increases the test time, which is a serious problem.

[0007]

In a test of a semiconductor integrated circuit device or the like, there is a stress test in which a potential serving as a stress is applied to a gate or a drain of a cell to test the deterioration of the cell. This test takes into account the shortening of the test time, and all word lines WL or all bit lines BL
However, it was not possible to judge whether stress was actually applied from outside.

The present invention has been made in view of the above circumstances, and a first object of the present invention is to completely select a word line and all bit lines, or deselect all word lines, by destroying a chip. It is an object of the present invention to provide a semiconductor integrated circuit device which can be determined without any problem and a stress test monitoring method thereof.

A second object is to prevent a memory cell from accidentally passing a stress test, and to improve the accuracy of screening of a memory cell. Is to provide.

[0010]

In order to achieve the first object, according to the first aspect of the present invention, a plurality of word lines,
A semiconductor integrated circuit device having a memory cell array including a plurality of bit lines and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines, respectively, wherein the potentials of the plurality of word lines are And a stress test monitor circuit that detects at least one of the potentials of the plurality of bit lines and the potentials of the plurality of bit lines all at once, and transmits the detection result to an external pad.

According to the first aspect of the present invention, there is provided a stress test monitor circuit for detecting at least one of the potentials of a plurality of word lines and the potentials of the plurality of bit lines all at once. Have. Further, the stress test monitor circuit transmits the detection result to an external pad. Therefore, in the stress test mode, at least one of the potentials of the plurality of word lines and the potentials of the plurality of bit lines are determined at the same time without breaking the chip. You can know more.

In the invention according to claim 2, claim 1 is
In the invention according to the invention, the stress test monitor circuit includes a connection circuit that electrically connects the external pad and the in-circuit power supply potential with a plurality of transistors connected in series, and the plurality of transistors connected in series. The potential of the plurality of word lines is supplied to each gate.

According to the second aspect of the present invention, the stress test monitor circuit includes an external pad and a power supply potential in the circuit.
A connection circuit electrically connected by a plurality of transistors connected in series is provided, and a potential of a plurality of word lines is supplied to each gate of the plurality of transistors connected in series. Therefore, the circuit scale of the stress test monitor circuit does not need to be so large, and the stress test monitor circuit for word lines can be formed on the chip while suppressing an increase in the chip area.

According to the third aspect of the present invention, there is provided the first aspect.
In the invention according to the invention, the stress test monitor circuit includes a connection circuit that electrically connects the external pad and the in-circuit power supply potential by a plurality of transistors connected in parallel, and the plurality of transistors connected in parallel. The potential of the plurality of word lines is supplied to each gate.

According to the third aspect of the present invention, the stress test monitor circuit includes an external pad and a power supply potential in the circuit.
A connection circuit electrically connected by a plurality of transistors connected in parallel is provided, and potentials of a plurality of word lines are respectively supplied to gates of the plurality of transistors connected in parallel. Therefore, the circuit scale of the stress test monitor circuit does not need to be so large, and the stress test monitor circuit for word lines can be formed on the chip while suppressing an increase in the chip area.

In the invention according to claim 4, claim 3
According to the invention, the plurality of transistors connected in parallel, which are included in the stress test monitor circuit, are configured by dummy memory cells provided in the memory cell array.

According to the present invention, the plurality of transistors connected in parallel included in the stress test monitor circuit are constituted by dummy memory cells provided in the memory cell array. Furthermore, the word line stress test monitor circuit can be formed on the chip while suppressing an increase in the chip area.

Further, in the invention according to claim 5, according to claim 1,
In the invention according to the invention, the stress test monitor circuit includes a connection circuit that electrically connects the external pad and the in-circuit power supply potential with a plurality of transistors connected in series, and the plurality of transistors connected in series. The potential of the plurality of bit lines is supplied to each gate.

According to the fifth aspect of the present invention, the stress test monitor circuit includes an external pad and a power supply potential in the circuit.
A connection circuit electrically connected by a plurality of transistors connected in series is provided, and a potential of a plurality of bit lines is supplied to each gate of the plurality of transistors connected in series. Therefore, the circuit scale of the stress test monitor circuit does not need to be so large, and the stress test monitor circuit for the bit line can be formed on the chip while suppressing an increase in the chip area.

In the invention according to claim 6, according to claim 2,
6. The invention according to claim 5, wherein the stress test monitor circuit has one end electrically connected to the external pad and the other end electrically connected to the connection circuit. And a circuit for causing a current to flow to the outside through the external pad when the operation is performed.

According to the sixth aspect of the present invention, a circuit for flowing a current to the outside through the external pad when the connection circuit is turned on is further provided, so that a larger current can be supplied to the external pad. Can flow out to the outside. Therefore, it is possible to improve monitoring accuracy by the stress test monitor circuit.

In the invention according to claim 7, claim 2 is
6. The conductive circuit according to claim 5, wherein the stress test monitor circuit has one end electrically connected to the external pad and the other end electrically connected to the connection circuit. A latch circuit for inverting latch data according to a state, a precharge circuit for precharging an interconnection point between the latch circuit and the connection circuit and initializing the latch data, and a power supply potential in the connection circuit and the circuit; And a discharge circuit that is connected in series between the two and discharges the supply terminal of the in-circuit power supply potential of the connection circuit.

According to the seventh aspect of the present invention, since a latch circuit for inverting latch data in accordance with the conduction state of the connection circuit is further provided, the detection result can be latched in the stress test monitor circuit. . Therefore, it is possible to improve monitoring accuracy by the stress test monitor circuit.

In order to achieve the first object, in the invention according to claim 8, a plurality of word lines, a plurality of bit lines,
And a stress test monitoring method for a semiconductor integrated circuit device having a memory cell array including a plurality of memory cells respectively connected to the plurality of word lines and the plurality of bit lines, wherein the potentials of the plurality of word lines are simultaneously Or at least one of the potentials of the plurality of bit lines are simultaneously detected by a stress test monitor circuit provided inside the device, and the detection result of the stress test monitor circuit is transmitted to the device. It is characterized in that it is taken out from the provided external pad.

According to the present invention, at least one of the potentials of a plurality of word lines and the potentials of a plurality of bit lines are provided at the same time inside the device. The test result is detected by an external stress pad provided in the device. For this reason,
At the time of the stress test mode, it is possible to know at least one of whether the potentials of the plurality of word lines are simultaneously aligned and whether the potentials of the plurality of bit lines are simultaneously aligned without breaking the chip.

In order to achieve the second object, according to the ninth aspect of the present invention, a plurality of word lines, a plurality of bit lines,
And a stress test for a semiconductor integrated circuit device having a memory cell array including a plurality of memory cells respectively connected to the plurality of word lines and the plurality of bit lines, wherein the memory cells include A stress applying step of applying a stress by at least one of aligning potentials at the same time and aligning potentials of the plurality of bit lines at the same time; and in the stress applying step, the potentials of the plurality of word lines are simultaneously adjusted. And a stress application verifying step for verifying at least one of whether the potentials of the plurality of bit lines are aligned at the same time.

According to the ninth aspect of the present invention, after the stress applying step, at the time of the stress applying step, whether the potentials of the plurality of word lines or the potentials of the plurality of bit lines are uniform at the same time Since the method includes the stress application verifying step of verifying at least one of them, it is possible to prevent the memory cell from accidentally passing the stress test. As described above, in the stress test performed through the two stages of the stress application and the stress application verification, the accuracy of the memory cell screening can be further improved.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. FIG. 1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 1 shows a NOR type memory cell array 1.
Is shown. In the memory cell array 1, a plurality of word lines WL1 to WL4 and a plurality of bit lines BL1 to BL4 are arranged. The plurality of memory cells MC are arranged at each intersection of the word line WL and the bit line BL. The memory cell MC is
The semiconductor integrated circuit device according to the first embodiment is a nonvolatile device having a floating gate FG.
And the like. Or E
1 with built-in PROM or FLASH-EEPROM
Construct a chip microcontroller. Memory cell M
The connection state between C and a word line and a bit line will be described focusing on a memory cell MC indicated by reference numeral A in the figure.
The drain D is connected to the bit line BL1, and the source S is connected to the source line SL1.

The semiconductor integrated circuit device according to the first embodiment has a stress test monitor circuit 2. The stress test monitor circuit 2 is connected to each of the word lines WL1 to WL4
And the pads 31 in the external pad group 3 are electrically coupled to each other. Stress test monitor circuit 2
Are the potentials V _{WL1 to} V _WL of the word lines _{WL1 to} WL4, respectively.
Receiving a _WL4, and detects whether these potential V _WL1 ~V _WL4 respective potential levels are all equal, the state DS in the detection, by the potential or signal, transmitted to the pad 31.

In the semiconductor integrated circuit device according to the first embodiment having the above configuration, by monitoring the detection state DS transmitted to the pad 31, all the word lines are selected in the stress test mode. It can be checked from the outside whether or not all the word lines have been deselected, without breaking the chip.

FIG. 2 is a circuit diagram showing a first example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the first embodiment. As shown in FIG. 2, the stress test monitor circuit 2 according to the first circuit example includes a series connection circuit 21 that connects a pad 31 and an in-circuit ground point GND to each other. Series connection circuit 21
Is an N-channel MOSFET (hereinafter referred to as NMO) in which a current path is connected in series between a pad 31 and a ground point GND.
S) It comprises 211-214. NMOS 21
The potential V _WL1 is supplied to the gate of the NMOS 1 and the NMOS 212
Is supplied with the potential V _WL2 , the gate of the NMOS 213 is supplied with the potential V _WL3 , and the gate of the NMOS 214 is supplied with the potential V _WL4 .

Next, the word line potential detecting operation performed by the circuit shown in FIG. 2 will be described. First, the probe 4 of the tester is brought into contact with the pad 31. The probe 4 is connected to a high potential power supply in a tester (not shown).

Next, the gate inputs of the series connection circuit 21 are connected to word lines WL1 to WL4, respectively,
The potentials V _{WL1 to} V _WL1 are respectively applied to the gates of 211 to 214.
It is assumed that _WL4 is supplied.

Next, the semiconductor integrated circuit device is set to the stress test mode. In this stress test mode, all the word lines _WL1 to WL4 are selected, that is, the potentials V _WL1 to V _WL1 to WL4 are selected.
In this mode, V _WL4 is all set to a high potential. At this time, if the potentials V _{WL1 to} V _WL4 are all high potentials, N
All the MOSs 211 to 214 are turned on. As a result, the current flows from the probe 4 through the pad 31 to the ground GND.
Flows towards Conversely, of the potentials V _{WL1 to} V _WL4 ,
If any one of them has a low potential, the NMOS 2
Since any of the switches 11 to 214 is turned off, no current flows.

As described above, in the circuit shown in FIG. 2, when the word lines WL are all selected, a current flows if all of the potentials V _{WL1 to} V _WL4 become high. By examining whether or not this current flows, it is possible to confirm whether or not the potentials V _{WL1 to} V _WL4 are normally high in the stress test mode.

FIG. 3 is a circuit diagram showing a modification of the first circuit example shown in FIG. As shown in FIG. 3, the series connection circuit 21 may connect the pad 31 and the in-circuit high-potential power supply VDD to each other.

When a potential detection operation is performed by the circuit shown in FIG. 3, the probe 4 of the tester may be connected to a ground point in the tester (not shown). Thus, similarly to the circuit shown in FIG. 2, in the stress test mode, it is determined whether or not all the word lines WL1 to WL4 have been selected by flowing a current from the in-circuit high-potential power supply VDD to the in-tester ground point. It can be confirmed by whether it flows.

FIG. 4 is a circuit diagram showing a second example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the first embodiment. As shown in FIG. 4, the stress test monitor circuit 2 according to the second circuit example includes a series connection circuit 21 and a current detection circuit 22 for connecting the pad 31 and the in-circuit ground point GND to each other.
The series connection circuit 21 has the same configuration as that of the first circuit example shown in FIG. 2, but the series connection circuit 21 connects the in-circuit ground point GND and the current detection circuit 22. That is different.

The current detection circuit 22 includes, for example, the inverter 2
21. The input of the inverter 221 is connected to the series connection circuit 21, and the output of the inverter 221 is connected to the pad 31. Current detection circuit 2
Reference numeral 2 denotes a circuit for flowing a current to the tester via the pad 31 when all of the transistors 211 to 214 included in the series connection circuit 21 are turned on.

Next, the word line potential detecting operation performed by the circuit shown in FIG. 4 will be described. First, the probe 4 is connected to the pad 31
Contact. Hereinafter, similarly to the circuit shown in FIG. 2 or FIG. 3, the word lines WL1 to WL4 are connected to the series connection circuit 21.
After that, the semiconductor integrated circuit device is set to the stress test mode. At this time, if the potentials V _{WL1 to} V _WL4 are all high potentials, all the NMOSs 211 to 214 are turned on, and the input of the inverter 221 becomes “L” level.
A current flows from the in-circuit high-potential power supply VDD toward the pad 31. As a result, a current I flows from the output of the inverter 221 to the ground point in the tester. On the other hand, the potential V _WL1
If any one of .about.V _WL4 has a low potential, one of the NMOSs 211 to 214 is turned off, so that the inverter 221 has, for example, a high impedance and no current flows.

As described above, in the circuit shown in FIG.
As in the circuit shown in FIG. 3, it can be confirmed whether or not all the word lines WL1 to WL4 have been selected in the stress test mode, based on whether or not a current flows.

The current detection circuit 22 of the second circuit example has an effect of amplifying the current flowing through the series connection circuit 21. Therefore, the value of the current flowing through the pad 31 can be increased. For this reason, the current flowing from the pad 31 can be easily detected by the tester. Therefore, the verification accuracy when verifying the stress test can be further improved.

FIG. 5 shows a third example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the first embodiment.
3A is a circuit diagram, and FIG. 3B is a timing chart of an input clock input to a third circuit example.

As shown in FIG. 5A, the stress test monitor circuit 2 according to the third circuit example has a ground point GN in the circuit.
A discharge circuit 23 for discharging the power supply terminal 24 of the series connection circuit 21 from the D to the pad 31; a series connection circuit 21; a precharge circuit 25 for precharging the output terminal 26 of the series connection circuit 21; A latch circuit 27 for latching the potential of the output terminal 26 of the series connection circuit 21 as binary data of “H” level and “L” level. The discharge circuit 23
An NMOS 23 having a current path connected in series between a ground point GND in the circuit and a power supply terminal 24 of the series connection circuit 21
Consists of one. The precharge circuit 25 includes an NMOS 251 having a current path connected in series between the in-circuit high-potential power supply VDD and the output terminal 26 of the series connection circuit 21.

Next, the word line potential detecting operation performed by the circuit shown in FIG. 5A will be described. First, the probe 4 is brought into contact with the pad 31, and the word lines WL1 to WL4 are connected to the series connection circuit 21, and then the stress test mode is set.

Next, as shown in FIG.
The precharge signal / PR is at "L" level, the discharge signal DIS is at "H" level, and the latch signal LU is at "L" level.
Level. Thus, the power supply terminal 24 of the series connection circuit 21 is first discharged.

Next, at time t0, the precharge signal / PR is set to "H" level, and the discharge signal DIS
At "L" level and the latch signal LU at "H" level. As a result, the output terminal 26 of the series connection circuit 21 is precharged to the “H” level.

Next, at time t1, the precharge signal / PR is set at "H" level and the discharge signal DIS is
At "H" level and the latch signal LU at "L" level. Thereby, the power supply terminal 24 of the series connection circuit 21
Are connected to the ground point GND in the circuit.

Next, at time t2, the precharge signal / PR is set at "L" level and the discharge signal DIS
At "H" level and the latch signal LU at "L" level. As a result, the output terminal 26 of the series connection circuit 21
Discharge is performed according to the conduction state of the series connection circuit 21. In the circuit shown in FIG. 5A, if the potentials V _{WL1 to} V _WL4 are all high, the NMOS 21
1 to 214 are all turned on, and the output terminal 26 is discharged via the series connection circuit 21. As a result, the potential of the output terminal 26 is inverted to the “L” level. Conversely, if any one of the potentials V _{WL1 to} V _WL4 has a low potential, one of the NMOSs 211 to 214 is turned off, and the potential of the output terminal 26 remains at the “H” level. . Such a potential of the output terminal 26 is latched by the latch circuit 27 as binary data indicating a verification result.

As described above, in the circuit shown in FIG.
As in the circuit shown in FIG. 4, whether or not all the word lines WL1 to WL4 have been selected in the stress test mode can be confirmed by the latch data of the latch circuit 27. In the circuit shown in FIG. 5 (a), the potential V _WL1 ~
If V _WL4 is all high potential, the latch circuit 27
Latch the “L” level. On the contrary, the potentials V _{WL1 to} V _WL
If any one of _WL4 has a low potential, the latch circuit 27 latches the "H" level. The data latched by such a latch circuit 27 is transmitted to the probe 4
It is possible to confirm whether or not all of the word lines WL1 to WL4 have been selected in the stress test mode. Since the third circuit example also includes the latch circuit 27 that latches data indicating the success or failure of the verification result, it is possible to improve the accuracy of the stress test verification as in the second circuit example.

Next, a semiconductor integrated circuit device according to a second embodiment of the present invention will be described. In the first embodiment, the stress test monitor circuit having a circuit configuration suitable for detecting whether or not all the word lines are selected in the stress test mode has been described.

The second embodiment relates to a stress test monitor circuit having a circuit configuration suitable for detecting whether or not all word lines are unselected in a stress test mode.

The semiconductor integrated circuit device according to the second embodiment has the same circuit blocks as the semiconductor integrated circuit device according to the first embodiment shown in FIG. Less than,
A circuit example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the second embodiment will be described.

FIG. 6 is a circuit diagram showing a first example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the second embodiment. As shown in FIG. 6, the stress test monitor circuit 2 according to the first circuit example includes a parallel connection circuit 28 that connects the pad 32 and the in-circuit ground point GND to each other. The parallel connection circuit 28
The current path is constituted by NMOSs 281 to 284 connected in parallel between the pad 32 and the ground point GND. The potential V _WL1 is supplied to the gate of the NMOS 281, the potential V _WL2 is supplied to the gate of the NMOS 282, the potential V _WL3 is supplied to the gate of the NMOS 283, and the potential V _WL4 is supplied to the gate of the NMOS 284.

Next, the potential detection operation performed by the circuit shown in FIG. 6 will be described. First, the probe 4 connected to a high-potential power supply in a tester (not shown) is brought into contact with the pad 32.

Next, the gate inputs of the parallel connection circuit 28 are connected to word lines WL1 to WL4, respectively.
The potentials V _{WL1 to} V _WL1 are respectively applied to the gates of 281 to 284.
It is assumed that _WL4 is supplied.

Next, the semiconductor integrated circuit device is set to the stress test mode. In this stress test mode, all the word lines WL1 to WL4 are unselected, that is, the potential V _WL1
To V _WL4 are all set to a low potential (for example, 0 V). At this time, if the potentials V _{WL1 to} V _WL4 are all low, all of the NMOSs 281 to 284 are turned off. As a result, no current flows through the pad 32. Conversely, _if any one of the potentials V _{WL1 to} V _WL4 becomes a high potential, one of the NMOSs 281 to 284 turns on,
A current I flows from the probe 4 to the ground GND via the external pad 32.

As described above, in the circuit shown in FIG. 6, when all the word lines WL are deselected, if the potentials V _{WL1 to} V _WL4 are all low, no current flows. Conversely, _if at least one of the potentials V _{WL1 to} V _WL4 is not low, the current I flows. Depending on whether or not this current flows, in the stress test mode, the potentials V _{WL1 to} V _WL4 are all
It can be confirmed whether or not the potential is normally low.

FIG. 7 is a circuit diagram showing a modification of the first circuit example shown in FIG. As shown in FIG. 7, the parallel connection circuit 28 may connect the pad 32 and the in-circuit high-potential power supply VDD to each other.

When a potential detection operation is performed by the circuit shown in FIG. 7, the probe 4 of the tester may be connected to a ground point in the tester (not shown). Thereby, similarly to the circuit shown in FIG. 6, it is determined whether or not all the word lines WL1 to WL4 have been deselected in the stress test mode.
It can be confirmed by whether or not a current flows from the high potential power supply VDD in the circuit toward the ground point in the tester.

FIG. 8 is a circuit diagram showing a second example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the second embodiment. As shown in FIG. 8, the stress test monitor circuit 2 according to the second circuit example includes a parallel connection circuit 28 and a current detection circuit 22 that connect the pad 32 and the in-circuit ground point GND to each other.
The parallel connection circuit 28 has the same configuration as that of the first circuit example shown in FIG. 6, but the parallel connection circuit 28 connects the in-circuit ground point GND and the current detection circuit 22. That is different.

The current detection circuit 22 includes, for example, the inverter 2
21. The input of the inverter 221 is connected to the parallel connection circuit 28, and the output of the inverter 221 is connected to the pad 32. Current detection circuit 2
Reference numeral 2 denotes a circuit for flowing a current to the tester via the pad 32 when any one of the transistors 281 to 284 included in the parallel connection circuit 28 is turned on.

Next, the word line potential detecting operation performed by the circuit shown in FIG. 8 will be described. First, the probe 4 is connected to the pad 32
Contact. Hereinafter, similarly to the circuit shown in FIG. 6 or 7, the word lines WL1 to WL4 are connected to the parallel connection circuit 28.
After that, the semiconductor integrated circuit device is set to the stress test mode. At this time, _if any one of the potentials V _{WL1 to} V _WL4 is a high potential, one of the NMOSs 281 to 284 is turned on, the input of the inverter 221 goes to the “L” level, and the current is reduced to a high level in the circuit. It flows from the potential power supply VDD toward the pad 32. Thereby, the inverter 221
, An electric current I flows toward the ground point in the tester. On the other hand, if all of the potentials V _{WL1 to} V _WL4 are low potentials, N
Since all of the MOSs 281 to 284 are turned off, the inverter 221 has a high impedance, for example, and no current flows.

As described above, in the circuit shown in FIG. 8, in the stress test mode, whether or not all of the word lines WL1 to WL4 are unselected is determined in the same manner as the circuits shown in FIGS. It can be confirmed by whether it flows. Further, the current detection circuit 22 included in the second circuit example has an action of amplifying the current flowing through the parallel connection circuit 28. Therefore, the value of the current flowing through the pad 32 can be increased. For this reason, there is an advantage that the verification accuracy when verifying the stress test can be improved.

FIG. 9 shows a third example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the second embodiment.
3A is a circuit diagram, and FIG. 3B is a timing chart of an input clock input to a third circuit example.

As shown in FIG. 9A, the stress test monitor circuit 2 according to the third circuit example has a ground point GN in the circuit.
A discharge circuit 23 for discharging the power supply terminal 24 of the parallel connection circuit 28 from the D to the pad 32; a parallel connection circuit 28; a precharge circuit 25 for precharging the output terminal 26 of the parallel connection circuit 28; And a latch circuit 27 for latching the potential of the output terminal 26 of the parallel connection circuit 28 as binary data of “H” level and “L” level. The discharge circuit 23
An NMOS 23 having a current path connected in series between a ground point GND in the circuit and a power supply terminal 24 of the parallel connection circuit 28
Consists of one. The precharge circuit 25 includes an NMOS 251 having a current path connected in series between the in-circuit high-potential power supply VDD and the output terminal 26 of the parallel connection circuit 28.

Next, the word line potential detecting operation performed by the circuit shown in FIG. 9A will be described. First, the probe 4 is brought into contact with the pad 32, and the word lines WL1 to WL4 are connected to the parallel connection circuit 28. Then, the stress test mode is set.

Next, as shown in FIG. 9B, first,
The precharge signal / PR is at "L" level, the discharge signal DIS is at "H" level, and the latch signal LU is at "L" level.
Level. Thus, the power supply terminal 24 of the parallel connection circuit 28 is first discharged.

Next, at time t0, the precharge signal / PR is set to "H" level, and the discharge signal DIS
At "L" level and the latch signal LU at "H" level. As a result, the output terminal 26 of the parallel connection circuit 28 is precharged to the “H” level.

Next, at time t1, the precharge signal / PR is set to "H" level, and the discharge signal DIS
At "H" level and the latch signal LU at "L" level. Thereby, the power supply terminal 24 of the parallel connection circuit 28
Are connected to the ground point GND in the circuit.

Next, at time t2, the precharge signal / PR is set at "L" level and the discharge signal DIS
At "H" level and the latch signal LU at "L" level. As a result, the output terminal 26 of the parallel connection circuit 28
Discharge is performed according to the conduction state of the parallel connection circuit 28. In the circuit shown in FIG. 9A, if any one of the potentials V _{WL1 to} V _WL4 becomes a high potential,
One of the NMOSs 281 to 284 turns on, and the output terminal 2
6 is discharged via the parallel connection circuit 28, and the potential of the output terminal 26 is inverted to "L" level. Conversely, _if all of the potentials V _{WL1 to} V _WL4 are low,
Since the OSs 281 to 284 are all turned off, the potential of the output terminal 26 remains at the “H” level. Such an output terminal 2
The potential of 6 is latched by the latch circuit 27 as binary data indicating the verification result.

As described above, in the circuit shown in FIG.
As in the circuit shown in FIG. 8, whether or not all of the word lines WL1 to WL4 are not selected in the stress test mode can be confirmed by the latch data of the latch circuit 27. In the circuit shown in FIG. 9A, potentials V _WL1 to V _WL1 to
If V _WL4 is all low potential, the latch circuit 27
Latch "H" level. On the contrary, the potentials V _{WL1 to} V _WL
If any one of _WL4 has a high potential, the latch circuit 27 latches the “L” level. The latch data latched by the latch circuit 27 is transmitted to the probe 4
It is possible to confirm whether or not all of the word lines WL1 to WL4 have been unselected in the stress test mode. Since the third circuit example also includes the latch circuit 27 that latches data indicating the success or failure of the verification result, it is possible to improve the accuracy of the stress test verification as in the second circuit example.

FIG. 10 is a circuit diagram of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the second embodiment.
FIG. 9 is a circuit diagram illustrating a fourth circuit example. As shown in FIG. 10, the parallel connection circuit 28 included in the device according to the second embodiment may be configured by using the dummy cell columns 11 provided in the memory cell array 1. When activating the stress test monitor circuit 2, the dummy cell row 11
Is connected to the power supply terminal 2 of the parallel connection circuit 28.
4, and the bit line BL0 is used as the output terminal 26 of the parallel connection circuit 28. Then, the source line SL0
Is connected to a discharge circuit 23, and the bit line BL0
Is connected to a precharge circuit 25 for precharging the latch circuit 27 and the output terminal 26.

In the fourth circuit example shown in FIG. 10, since the parallel connection circuit 28 is formed using the dummy cell row 11,
It is not necessary to provide the parallel connection circuit 28 in the integrated circuit chip. Therefore, an increase in the number of integrated elements due to the provision of the stress test monitor circuit 2 can be suppressed.

In the stress test monitor circuit 2 shown in FIG. 10, the third circuit example shown in FIG. 9A is used, but the parallel type of the circuit examples shown in FIGS. 6, 7 and 8 is used. Of course, the connection circuit 28 can be configured using the dummy cell column 11.

Next, a semiconductor integrated circuit device according to a third embodiment of the present invention will be described. FIG. 11 is a block diagram of a semiconductor integrated circuit device according to the third embodiment of the present invention.

As shown in FIG. 11, the semiconductor integrated circuit device according to the third embodiment includes bit lines BL1 to BL4
And a stress test monitor circuit 2 electrically coupled to the external pad 3 and the external pad 3, respectively. Stress test monitor circuit 2 receives potentials V _{BL1 to} V _BL4 of bit lines _{BL1 to BL4} , respectively. And the potential V _BL1
ＶV _BL4 are detected as to whether or not all of them have the same potential level, and the detection state DS is transmitted to the pads 33 included in the external pad group 3 by a potential or a signal.

FIG. 12 shows the stress test monitor circuit 2 of the semiconductor integrated circuit device according to the third embodiment.
FIG. 3 is a circuit diagram illustrating a first circuit example. As shown in FIG. 12, the stress test monitor circuit 2 according to the first circuit example includes a series connection circuit 21 that connects a pad 33 and an in-circuit ground point GND to each other. The series connection circuit 21 includes NMOSs 211 to 214 having current paths connected in series between the pad 33 and the ground point GND. The gate of the NMOS 211 is supplied with the potential V _BL1 , the gate of the NMOS 212 is supplied with the potential V _BL2 , the gate of the NMOS 213 is supplied with the potential V _BL3 , and the gate of the NMOS 214 is supplied with the potential V _BL4 .

Next, the bit line potential detecting operation performed by the circuit shown in FIG. 12 will be described. First, probe 4 of the tester
The pad 33 is brought into contact with the pad 33. The probe 4 is connected to a high potential power supply in a tester (not shown).

Next, the gate inputs of the series connection circuit 21 are connected to bit lines BL1 to BL4, respectively,
The potentials V _{BL1 to} V _BL1 are respectively applied to the gates of 211 to 214.
_BL4 is supplied.

Next, the semiconductor integrated circuit device is set to the stress test mode. In this stress test mode, all the bit lines _BL1 to BL4 are selected, that is, the potentials V _BL1 to V _BL1 are selected.
In this mode, V _BL4 is all set to a high potential. At this time, if the potentials V _{BL1 to} V _BL4 are all high potentials, N
All the MOSs 211 to 214 are turned on. As a result, the current flows from the probe 4 through the pad 33 to the ground GND.
Flows towards Conversely, of the potentials V _{BL1 to} V _BL4 ,
If any one of them has a low potential, the NMOS 2
Since any of the switches 11 to 214 is turned off, no current flows.

As described above, in the circuit shown in FIG. 12, when the bit lines BL are all selected, a current flows if all of the potentials V _{BL1 to} V _BL4 become higher. By examining whether or not this current flows, it is possible to confirm whether or not the potentials V _{BL1 to} V _BL4 are normally high in the stress test mode.

FIG. 13 is a circuit diagram showing a modification of the first circuit example shown in FIG. As shown in FIG. 13, the series connection circuit 21 may connect the pad 33 and the in-circuit high-potential power supply VDD to each other.

When a potential detection operation is performed by the circuit shown in FIG. 13, the probe 4 of the tester may be connected to a ground point in the tester (not shown). As a result, similarly to the circuit shown in FIG. 12, in the stress test mode, whether or not all the bit lines BL1 to BL4 have been selected is determined by the current flowing from the in-circuit high potential power supply VDD to the in-tester ground point. It can be confirmed by whether it flows.

FIG. 14 is a circuit diagram of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the third embodiment.
FIG. 9 is a circuit diagram illustrating a second circuit example. As shown in FIG. 14, the stress test monitor circuit 2 according to the second circuit example
Includes a series connection circuit 21 and a current detection circuit 22 for connecting the pad 33 and the in-circuit ground point GND to each other. The series connection circuit 21 has the same configuration as the first circuit example shown in FIG.
However, the difference is that the grounding point GND in the circuit and the current detection circuit 22 are connected.

The current detecting circuit 22 includes, for example, the inverter 2
21. The input of the inverter 221 is connected to the series connection circuit 21, and the output of the inverter 221 is connected to the pad 33. Current detection circuit 2
Reference numeral 2 denotes a circuit for flowing a current to the tester via the pad 33 when all of the transistors 211 to 214 included in the series connection circuit 21 are turned on.

Next, the bit line potential detecting operation performed by the circuit shown in FIG. 14 will be described. First, the probe 4 is connected to the pad 3
3 is brought into contact. Hereinafter, similarly to the circuit shown in FIG. 12 or FIG. 13, after connecting the bit lines BL1 to BL4 to the serial connection circuit 21, the semiconductor integrated circuit device is set to the stress test mode. At this time, the potentials V _{BL1 to} V _BL4 are
If the potentials are all high, the NMOSs 211 to 214 are all turned on, the input of the inverter 221 goes to the “L” level, and current flows from the in-circuit high potential power supply VDD to the pad 33. As a result, a current I flows from the output of the inverter 221 to the ground point in the tester. On the other hand, the potential V
Of _BL1 ~V _BL4, if a low potential even one, since the off either NMOS211～214, inverter 221, for example, a high impedance, current does not flow.

As described above, in the circuit shown in FIG.
2. As in the circuit shown in FIG. 13, whether or not all the bit lines BL1 to BL4 have been selected in the stress test mode can be confirmed by whether or not a current flows.

The current detection circuit 22 of the second circuit example has an effect of amplifying the current flowing through the series connection circuit 21. Therefore, the value of the current flowing through the pad 33 can be further increased. Therefore, the detection of the current flowing from the pad 33 can be easily performed by the tester. Therefore, the verification accuracy when verifying the stress test can be further improved.

FIGS. 15A and 15B show a third example of the stress test monitor circuit 2 included in the semiconductor integrated circuit device according to the third embodiment. FIG. 15A is a circuit diagram, and FIG. 9 is a timing chart of an input clock input to a third circuit example.

As shown in FIG. 15A, the stress test monitor circuit 2 according to the third circuit example has a ground point G in the circuit.
A discharge circuit 23 for discharging the power supply terminal 24 of the series connection circuit 21 from the ND to the pad 33; a series connection circuit 21; a precharge circuit 25 for precharging the output terminal 26 of the series connection circuit 21; A latch circuit 27 for latching the potential of the output terminal 26 of the series connection circuit 21 as binary data of “H” level and “L” level. Discharge circuit 23
Is an NMOS having a current path connected in series between a ground point GND in the circuit and a power supply terminal 24 of the series connection circuit 21.
231. Further, the precharge circuit 25 is connected to the in-circuit high-potential power supply VDD and the output terminal 26 of the series connection circuit 21.
And an NMOS 251 having a current path connected in series.

Next, the bit line potential detecting operation performed by the circuit shown in FIG. 15A will be described. First, the probe 4 is brought into contact with the pad 33, the bit lines BL1 to BL4 are connected to the series connection circuit 21, and then the mode is set to the stress test mode.

Next, as shown in FIG. 15B, first, the precharge signal / PR is set at "L" level, the discharge signal DIS is set at "H" level, and the latch signal LU is set at "L" level. Thereby, the series connection circuit 21
Is first discharged.

Next, at time t0, the precharge signal / PR is set to "H" level, and the discharge signal DIS
At "L" level and the latch signal LU at "H" level. As a result, the output terminal 26 of the series connection circuit 21 is precharged to the “H” level.

Next, at time t1, the precharge signal / PR is set at "H" level and the discharge signal DIS is
At "H" level and the latch signal LU at "L" level. Thereby, the power supply terminal 24 of the series connection circuit 21
Are connected to the ground point GND in the circuit.

Next, at time t2, the precharge signal / PR is set at "L" level and the discharge signal DIS
At "H" level and the latch signal LU at "L" level. As a result, the output terminal 26 of the series connection circuit 21
Discharge is performed according to the conduction state of the series connection circuit 21. In the circuit shown in FIG. 15A, if the potentials V _{BL1 to} V _BL4 are all high, the NMOS 2
11 to 214 are all turned on, and the output terminal 26 is discharged via the series connection circuit 21. As a result, the potential of the output terminal 26 is inverted to the “L” level. Conversely, if any one of the potentials V _{BL1 to} V _BL4 has a low potential, one of the NMOSs 211 to 214 is turned off, so that the potential of the output terminal 26 remains at the “H” level. . Such a potential of the output terminal 26 is latched by the latch circuit 27 as binary data indicating a verification result.

As described above, in the circuit shown in FIG.
Similarly to the circuits shown in FIGS. 2 to 14, whether or not all the bit lines BL 1 to BL 4 have been selected in the stress test mode can be confirmed by the latch data of the latch circuit 27. In the circuit shown in FIG.
If _BL1 ~V _BL4 are all high potential, the latch circuit 27
Latches the “L” level. Conversely, the potential V _BL1 ~
If any one of V _BL4 has a low potential, the latch circuit 27 latches the “H” level. By taking out the data latched by the latch circuit 27 outside the chip by the probe 4, it is possible to confirm whether or not all the bit lines BL1 to BL4 have been selected in the stress test mode. Since the third circuit example also includes the latch circuit 27 that latches data indicating the success or failure of the verification result, it is possible to improve the accuracy of the stress test verification as in the second circuit example.

FIG. 16 is a diagram showing a result of monitoring the word line selection state by the semiconductor integrated circuit device according to the first embodiment. FIG. 16 shows that at the time of the stress test, all the word lines were at a low potential (a = 0), some of the word lines were at a low potential (0 <a <all), Is high when (a = all)
Two cases are shown. In these three cases,
Only “a = all” indicates that the stress test was normal.

FIG. 17 is a diagram showing a result of monitoring a word line non-selected state by the semiconductor integrated circuit device according to the second embodiment. FIG. 17 shows that at the time of the stress test, all the word lines are at a high potential (b = 0), some of the word lines are at a high potential (0 <b <all), Are low potentials (b = all). In these three cases, only "b = all" indicates that the stress test was normal.

FIG. 18 is a diagram showing a result of monitoring a bit line selection state by the semiconductor integrated circuit device according to the third embodiment. FIG. 18 shows that all the bit lines are at a low potential (c = 0) and some of the bit lines are at a low potential (0 <c <all) during the stress test. Is high when (c = all)
Two cases are shown. In these three cases,
Only “c = all” indicates that the stress test was normal.

As shown in FIGS. 16 to 18, respectively, in the semiconductor integrated circuit devices according to the first to third embodiments,
The selected / non-selected state of the word line and the selected state of the bit line can be monitored externally. For this reason, unlike the related art, it is not necessary to destroy the chip to know the word line selection / non-selection state and the bit line selection state, and the time required for the stress test verification can be reduced.

In the current semiconductor technology, miniaturization has progressed, and the chip size itself has become very small. The measurement of the internal voltage by the conventional needle contact increases the difficulty level in proportion to the progress of miniaturization, and may cause the chip to be damaged or broken. Such a situation is solved in the semiconductor integrated circuit devices according to the first to third embodiments.

If the monitoring result from the stress test monitor circuit 2 is output using an unused pad of the external pad group 3, the number of pads does not increase and the chip size does not increase. .

In the case of the semiconductor integrated circuit devices according to the first to third embodiments, during the stress applying step, during the stress applying step, during the stress applying step, the potentials of the plurality of word lines are changed. A stress application verifying step for verifying whether the potentials of all the bit lines are aligned at the same time and the potentials of the plurality of bit lines may be newly included. In a conventional checking operation using a needle contact, it is difficult to include a stress application verifying step in a stress test sequence, and it has been only a spot inspection.

However, in the case of the semiconductor integrated circuit devices according to the first to third embodiments, a stress application verification step can be included in the stress test sequence. Thus, during the stress test sequence,
By including the stress application verification step, it is possible to verify whether or not stress has been applied to all the semiconductor integrated circuit devices, and to reliably prevent memory cells from accidentally passing the stress test. Can be. Therefore, the reliability of the stress test can be further improved.

The stress test monitor circuits included in the semiconductor integrated circuit devices according to the first to third embodiments can be combined and formed in one chip.

[0108]

As described above, according to the present invention, all of the word lines of a cell, all of the bit lines of a cell, and all of the word lines can be unselected without breaking the chip. Semiconductor integrated circuit device that can be determined, stress test monitoring method thereof, and novel semiconductor integrated circuit that can prevent memory cells from inadvertently passing a stress test and can further improve the accuracy of memory cell screening Each can provide a stress test for the device.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment.

FIG. 2 is a circuit diagram showing a first example of a stress test monitor circuit included in the semiconductor integrated circuit device according to the first embodiment;

FIG. 3 is a circuit diagram showing a modification of the first circuit example shown in FIG. 2;

FIG. 4 is a circuit diagram showing a second example of the stress test monitor circuit included in the semiconductor integrated circuit device according to the first embodiment;

FIGS. 5A and 5B are diagrams showing a third example of the stress test monitor circuit included in the semiconductor integrated circuit device according to the first embodiment. FIG. 5A is a circuit diagram, and FIG. Timing chart.

FIG. 6 is a circuit diagram showing a first example of a stress test monitor circuit included in a semiconductor integrated circuit device according to a second embodiment.

FIG. 7 is a circuit diagram showing a modification of the first circuit example shown in FIG. 6;

FIG. 8 is a circuit diagram showing a second example of the stress test monitor circuit included in the semiconductor integrated circuit device according to the second embodiment.

FIGS. 9A and 9B are diagrams showing a third example of the stress test monitor circuit included in the semiconductor integrated circuit device according to the second embodiment, wherein FIG. 9A is a circuit diagram, and FIG. Timing chart.

FIG. 10 is a circuit diagram showing a fourth example of the stress test monitor circuit included in the semiconductor integrated circuit device according to the second embodiment;

FIG. 11 is a block diagram of a semiconductor integrated circuit device according to a third embodiment.

FIG. 12 is a circuit diagram showing a first example of a stress test monitor circuit included in a semiconductor integrated circuit device according to a third embodiment.

FIG. 13 is a circuit diagram showing a modification of the first circuit example shown in FIG. 12;

FIG. 14 is a circuit diagram showing a second example of the stress test monitor circuit included in the semiconductor integrated circuit device according to the third embodiment.

FIGS. 15A and 15B are diagrams illustrating a third example of the stress test monitor circuit included in the semiconductor integrated circuit device according to the third embodiment. FIG. 15A is a circuit diagram, and FIG. Timing chart.

FIG. 16 is a view showing a result of monitoring a word line selection state by the semiconductor integrated circuit device according to the first embodiment;

FIG. 17 is a diagram illustrating a result of monitoring a word line non-selected state by the semiconductor integrated circuit device according to the second embodiment;

FIG. 18 is a diagram illustrating a result of monitoring a bit line selection state by the semiconductor integrated circuit device according to the third embodiment;

FIG. 19 is a circuit diagram of a memory cell array.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Stress test monitor circuit, 3 ... External pad, 4 ... Probe, 11 ... Dummy cell row, 21 ... Series connection circuit, 22 ... Current detection circuit, 23 ... Discharge circuit, 24 ... Power supply end, 25: Precharge circuit, 26: Output terminal, 27 Latch circuit, 28: Parallel connection circuit, 31, 32, 33 ... External pad 211-214, 231, 251, 281-284 ... N
MOS.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/115 G01R 31/28 B H01L 27/10 434

Claims (9)

[Claims] 1. A semiconductor integrated circuit device having a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines, respectively. A stress test monitor circuit for detecting at least one of the potentials of the plurality of word lines and the potentials of the plurality of bit lines simultaneously, and transmitting a result of the detection to an external pad. A semiconductor integrated circuit device characterized by the above-mentioned. 2. The stress test monitor circuit includes a connection circuit for electrically connecting the external pad and the power supply potential in the circuit by a plurality of transistors connected in series, and the plurality of transistors connected in series. 2. The semiconductor integrated circuit device according to claim 1, wherein the potential of each of the plurality of word lines is supplied to each of the gates. 3. The stress test monitor circuit has a connection circuit for electrically connecting the external pad and the in-circuit power supply potential by a plurality of transistors connected in parallel, and the plurality of transistors connected in parallel. 2. The semiconductor integrated circuit device according to claim 1, wherein the potential of each of the plurality of word lines is supplied to each of the gates. 4. The plurality of transistors connected in parallel, which are included in the stress test monitor circuit, are configured by dummy memory cells provided in the memory cell array. 3. The semiconductor integrated circuit device according to 1. 5. The stress test monitor circuit has a connection circuit for electrically connecting the external pad and the in-circuit power supply potential by a plurality of transistors connected in series, and the plurality of transistors connected in series. 2. The semiconductor integrated circuit device according to claim 1, wherein each gate is supplied with a potential of said plurality of bit lines. 6. The stress test monitor circuit having one end electrically connected to the external pad and the other end electrically connected to the connection circuit. 6. The semiconductor integrated circuit device according to claim 2, further comprising a circuit for flowing to the outside via an external pad. 7. The stress test monitor circuit having one end electrically connected to the external pad and the other end electrically connected to the connection circuit, and inverts latch data according to a conduction state of the connection circuit. A latch circuit for precharging an interconnection point between the latch circuit and the connection circuit, a precharge circuit for initializing latch data, and a serial connection between the connection circuit and the power supply potential in the circuit; 6. The semiconductor integrated circuit device according to claim 2, further comprising a discharge circuit configured to discharge a supply end of the in-circuit power supply potential of the connection circuit. 8. A stress test for a semiconductor integrated circuit device having a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines. A monitoring method, wherein a stress test monitor circuit provided inside a device determines at least one of the potentials of the plurality of word lines and the potentials of the plurality of bit lines all at once. A stress test monitoring method for a semiconductor integrated circuit device, comprising: detecting and detecting a detection result of the stress test monitor circuit from an external pad provided on the device. 9. A stress test for a semiconductor integrated circuit device having a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines. A stress application step of applying a stress to at least one of the memory cells at the same time by simultaneously adjusting potentials of the plurality of word lines and simultaneously adjusting potentials of the plurality of bit lines; A stress application verifying step for verifying at least one of whether the potentials of the plurality of word lines are simultaneously aligned or the potentials of the plurality of bit lines are simultaneously aligned during the applying step. Stress test for semiconductor integrated circuit devices.