TWI325522B - - Google Patents

Description

1325522 丨月聊修 Replacement page 98-12-24 Nine, invention description: [Technical field of invention]

The present invention provides an adjustment circuit in which the internal detection circuit determines whether the resistance of the switch and the resistance of the circuit are increased or not, regardless of whether the fuse is positive or not. The control unit can detect the level signal according to the received signal, and cooperate with the logic conversion mechanism to output "on" or "off" to the function of the relative transistor switch.

[Prior Art] Instrument, yak conductor industry is moving towards the design-oriented trend... ▼Leading again with the second C integration and system single-chip (soc) hair is hot, @为# focus on low price ,high efficiency,

When the light binding is short and the number of faces can be clear, only the more accurate reduction is better. The number of crystals that can be accommodated in the unit of the red age is more and more, the forest components = 敕People have also gradually achieved remarkable results under the efforts of developers. , Wangkou "on the chip circuit" need a reference voltage generation circuit to the right, so we use this as an example; the main reference of the voltage reference source to the external fine - effective _ = deviation, so the relevant industry to solve this The power output of the wheel is H = 遂, the number of small resistors connected in series to the main electrical difference 砀 ' -3 kg not 'system diagram of the reference voltage generation circuit for μ and 5 22 22 98-12-

The voltage output table, from the figure, can be used to refer to the deviation of the voltage 'in the reference; = road = the circuit contains money (4) (four) in the main burial, the resistor B1 is connected to the fuse B2, 'moving I: =B1 to fine tune the absolute value of the main resistor A1, and micro-achieve. The fuse B2 in parallel with the resistor B1 is blown or not. The reference electric test circuit is as follows. 1. The reference voltage generating circuit used in the following is used after the wafer is fabricated, ... = off, Wire B2, but the fuse B2 cannot be added. Therefore, before the "Si:: tuning" wafer is unprocessed, all the fuses B2 ^ are counted as unbaked (short circuit)' so the output voltage A2 must be low (such as Figure 2; the power generation of the two-voltage generating circuit A is the action of using the current to make the blow, and the standby =: the logic of the predicted demand "." or - the setting = the desire ===' is to engage in this It is necessary for the industry to compile. The relevant industry is making progress and innovation design 1325522 98·12·24 ~Ό, in order to achieve the above-mentioned lack of use, the applicant designed another detection adjustment circuit, which is to use the voltage reference circuit. The main resistor is provided with a plurality of adjusting resistors connected in series with the main resistor, and each resistor is connected in parallel with a transistor switch and connected to the logic controller, and the logic controller converts and receives the voltage level control relative to the transistor switch according to the logic conversion table. And then issued • 〇’· represents unburned or "1” represents the voltage level of the blow to the logic controller' to determine whether the transistor switches are turned on or off.

SUMMARY OF THE INVENTION Nowadays, in view of the lack and deficiency of the above-mentioned detection adjuster, the inventor has invented such a programmable detection adjuster by continuously improving and experimenting with the experience of many years of research and invention in this industry. . /,shell

. The main purpose of the present invention is to control the conduction of the transistor switch by using a logic controller provided by the adjustment circuit for fine-tuning the voltage parameter, the absolute value of the main resistance of the circuit, and the electric summer output of the voltage reference circuit. There is no case where the voltage is low before the treatment is carried out. The secondary object of the present invention is that regardless of whether the fuse of the detecting circuit is broken or not, the resistance value of the fuse is compared with the resistance value of the resistance of the detecting circuit, and the relative relationship is the same. When it comes to 'requires the user's needs before shipment and adjust the relative relationship of the logic controller to simplify the lack of stock. [Embodiment] In order to achieve the above object and structure, and in order to enable the reviewing committee to be able to do this 7 _ _ _ , -τ * - *«.9 L _ »· ·._·»*»·»· - 98- 12-24 The purpose and effect of the invention has a further understanding of the technical means, S_ is based on the invention, and the method adopted by the present invention is described in detail as follows: τ:ί: H is the circuit diagram of the present invention. As seen from FIG. 3α, the present invention is connected to the adjustment circuit 2 on the main reference 11 of the voltage reference _ (bandgap) i, and the adjustment circuit 2 has the adjustment of the series connection of the resistors 11. Resistor 21, and adjusting resistor 21 crystal switch 22' and each transistor switch 22 is connected to

The logic control 1123 is connected to the detection circuit 24 which is equal to the transistor ! Here, although only three adjustment resistors 21 and three transistors _ 22 * have been drawn in Fig. 3A, the present invention is not limited thereto. In the present embodiment, the number of the adjustment resistors 21 is the same as that of the electric toe switch 22 and the detection circuit 24, and the second transistor switch 22 corresponds to the ith adjustment resistor 21 (i is a positive integer), and the earth, detection circuit 24 corresponds to the i-th transistor switch 22. As shown in FIG. 3A, the first transistor switch 22 (the transistor switch 22 at the top of FIG. 3A) corresponds to the first adjustment resistor 21 (ie, the adjustment resistor labeled 4R); the second transistor switch 22 (the transistor switch 22 in the middle of FIG. 3A) corresponds to the second adjustment resistor 21 (ie, the adjustment resistor labeled 2R); and the third transistor switch 22 (the transistor switch at the bottom of FIG. 3A) 22) corresponds to the third adjustment resistor 21 (ie, the adjustment resistor labeled R). In addition, the 'first detection circuit 24 (the one at the top of Fig. 3A is 8 98-12-24 Z circuit 24) corresponds to the first solid crystal switch 2 - the transistor switch 22); That detection circuit 24) for the library, 24 (the middle of the middle 3 图 — — — 22 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( (曰 group = 22 (the figure from the bottom of the - a transistor switch such as.

^Upper handle interpretation, the field of the invention has a wealth of knowledge should not be difficult ^ 3 or more embodiments 'There is no longer a table here (t η 然: right 1 is more than 3, the following logical conversion two : The corresponding modification must be made. However, since such a modification can still be known from the disclosure of the following embodiment, it will not be described here. Therefore, the following is only an example in which i is equal to 3. A detailed description will be apparent to those of ordinary skill in the art.

Please refer to FIG. 3A and FIG. 4 at the same time, which is a schematic circuit diagram of the circuit diagram and the programmable detection circuit of the present invention ("" can be clearly seen from the figure, when the adjustment circuit 2 pairs the voltage reference circuit (bandgap) 1 When the output voltage (VBG) 12 is fine-tuned, each of the detection circuits 24 detects whether the fuse 249 is blown and detects whether the gate of the third transistor switch 248 has a large current flowing through the fuse 249, and the fuse If the 249 is blown, the detecting circuit 24 outputs a high level voltage (ie, a detection signal) to the logic controller 23, and vice versa, outputs a low level voltage to the logic controller 23; in addition, whether the fuse 249 is to be blown. The process is determined by controlling whether the third transistor switch 248 is turned on or not, but the current flowing through the fuse 249 will be limited by the impedance of the third transistor switch 248. If the voltage is not large enough, the fuse 249 is not blown. 13 1325522 When the occurrence occurs, the relative relationship of the resistance 247 in the circuit 24 shown in FIG. 5 is used to determine the output low level = or the south level voltage to the logic controller 23, regardless of whether the fuse is f or not. No blown, also As a result, the final voltage reference circuit Γ turns out. The current flowing through the fuse 249 is not large enough to cause the fuse 24& the broken beer situation occurs, the debt measurement circuit shown in Figure 5 flows through the fuse, 249 The current and the current flowing through the resistor R generate a detection signal to the logic controller 23 (to be detailed later), 'from the present embodiment, when the logic controller 23 receives the voltage level 粋J II That is, according to the logic diagram shown in Figure 3Β conversion table conversion: the relative relationship between the tiger and the tiger, to control the relative transistor switch (four) switch, circuit! The main resistance = absolute value. Thus, before the wafer is processed, == 23 Then adjust the electro-crystallizer = with the logic conversion table shown in Figure 3B to avoid the wafer being unprocessed but the fuse is fully retained: Off: The problem of the output voltage 12 of the reference circuit 1 is low. Soil = f Switch NM 〇S or PM〇S, and such a simple modification and equivalent two 3 = the same is included in the patent _ of the present invention, and the combination of the ^ ^ 应, this 'Please also refer to _ 3 and Figure 4, For the schematic circuit diagram (1) of the 3 and ^ _ circuits, as can be seen from the figure, the circuit 24 includes Inverters 241 to 244, nm 〇s electro-crystals 10 1325522 98-12-24' 245 and 246 (first and second transistor switches), electric 247, PMOS transistor 248 (third transistor switch) The fuse 249, and the buffer 250. The input end of the inverter 241 is configured to receive a power on reset signal (POR). The input end of the inverter 242 is connected to the inverter 241. The output terminal of the NMOS transistor 245 is coupled to the output terminal of the inverter 241 and the source of the NMOS transistor 245 is coupled to the ground potential.

The input of the inverter 243 is coupled to the drain of the NMOS transistor 245. The input of the inverter 244 is coupled to the output of the inverter 243, and the output of the inverter 244 is coupled to the input of the inverter 243. NMOS transistor

The gate of the NMOS transistor 246 is coupled to the input of the inverter 244, and the source of the NMOS transistor 246 is coupled to the first terminal of the resistor 247. The input of the buffer 25A is coupled to the input of the reverse benefit 244, and the output of the buffer 250 is coupled to the logic controller 23 to rotate the detection signal. The gate of the PM〇s transistor 2 is used to receive the ton signal Trim, the source of the PM〇s transistor is connected to the power supply VCC'PMQS transistor 248, the bottom of the bucking fuse 249 - The terminal is coupled to the second end of the resistor 247 and the fuse 2 is coupled to the ground potential. 'Dogate 248 § When the fuse 249 is not blown or the resistance of the third transistor switch 248 is not increased, the hybrid 24 is outputting a low power plant so that the logic (4)||23 can be received To _. =: For the relationship, and with the logic to turn the system, turn,, or "off the crystal switch 22, to control the conduction of each transistor _ 22, the sub-98-12-24 ^ = - the main electricity of the circuit 1 1111 each light resistor 21 to fine-tune the absolute value 1 of the main 11 to achieve the purpose of unbiased adjustment. - Li = 4 see Figure 5 is a programmable detection circuit diagram of the invention (2) ' can be clearly seen from the figure The _ circuit 24 includes transistors M3 〜 M5 and 248, NM 〇 s transistors M 〇 M M2, Λ Π 糸 糸 249 ′ and buffer 250. The PMOS transistor is used for ΐ ΐ Receive-detection signal (surface 6 Signal) SenSe, and the source of S-electrode_3 is connected to the power supply vcc. The source of the body M0 and the source of the 汲_pTM〇=NM〇S transistor_ The ground terminal is grounded. The gate of the crystal M1 of the blown crystal M1 is the gate of the transistor M0. The source of the transistor M1 is connected to the first end of the resistor R and is connected to the ground potential. The transistor M4 _ Connected to - transistor: t ^ vcc, Tpmos Γ δ 1 Β θθ ^ M5 ^ The idle pole of the transistor class. The gate of the electric body M5 consumes m〇s wire NMOS ί Γ body M2 Connected to NM〇S Gate of M0: The source of the M2 of the immersed face of the coffee machine Μ5 is connected to the first end of the fuse 249, and the second end of the fuse is transferred to the ground potential. The drain of M2' and the buffer 25 output terminal minus the logic controller 23 to output the detection signal. The source of the pMQs 248 is connected to the power supply Vcc, and the gate of the pM〇s transistor ice is used for 12

February zy0 correction replaces page I 98-12-24 ' receives the trim signal Trim, and the drain of pM0S transistor 248 couples the first end of fuse 249. Based on the above, when the detecting circuit 24 detects that a large current has passed through the transistor M3, due to the relationship of the current mirror, if the resistance of the fuse 249 is smaller than the preset resistance R, the current flowing through the transistor M2 is higher than that of the transistor. M1 is large, and the current of the transistor Μ1 is transmitted to the transistor M 5 through the transistor M4 current mirror, so the transistor Μ 5 current is smaller than the transistor M 2 , so the logic of the output circuit 24 output Lu will be “〇” Or "off", conversely, if the value of the fuse 249 is greater than the preset resistance R, the logic that the detection circuit 24 will output will be ", or "on"; again, as shown in Figure 6, based on The configuration of the above circuit and the function of the current mirror, the third transistor switch 248 and the fuse 249 can be set at the power supply end, thereby achieving the effect of adjusting the voltage without deviation. Further, please refer to FIG. The detecting circuit 24 includes NM〇s transistors M0 to M3 and 248, PMOS transistors M4 and M5, a resistor R, a fuse 249', and a buffer 250. The gate of the NM〇s transistor is used to receive a Sense signal Sense is detected, and the source of NM〇s transistor Μ] is coupled to The potential of the NMOS transistor M0 is coupled to the power supply VCC, the first end of the resistor R, and the first end of the fuse 249, and the gate and the source of the NMOS transistor M0 are coupled to the NM〇s transistor M3. The drain of the NMOS transistor M1 is coupled to the two ends of the resistor scale, and the gate of the NMOS transistor M1 is coupled to the gate of the NMOS transistor. The source of the PMOS transistor M4 is coupled to the gate NM. 〇s the source of the transistor M1, and the drain of the PMOS transistor M4 is coupled to: 13 1325522 98-12

$年十二月#曰Correct replacement page I bit. The gate of the NMOS transistor M2 is coupled to the gate of the NM〇s transistor, and the gate of the NMOS transistor M2 is coupled to the second end of the fuse 249. The PMOS transistor M5 has a pole _ NM 〇 s transistor, and the PMOS transistor source is reduced by the source of the NM 〇 s transistor M2, and the PMOS transistor M5 is coupled to the ground potential. The gate of the NMOS transistor 248 is used for receiving-adjusting the signal, as the s|g=Tnm 'NM0S transistor is torn by the flip-chip fuse, and the source of the NMOS transistor 248 is connected to the ground potential. . The input of the buffer 250 is switched to the source of the PMOS «Crystal M5, and the output of the buffer 25G is connected to the logic (4) 23 to input the (four) signal. The operation principle of the detecting unit 24 in FIG. 6 is similar to the detecting unit 24 of FIG. 5, and thus will not be described herein. Therefore, the key to the programmable detect adjuster of the present invention is: ° . (-) The present invention provides a plurality of series-connected adjustment resistors 21 for the can-hole circuit 2, and each of the adjustment resistors 21 is separately coupled to the crystal switch a, and each transistor _ 22 is connected to the logic control 23 to enable the logic circuit to receive When the calibration is on time, T or T is output according to the logic conversion table, and the relative transistor switch 22' is controlled to control the conduction of each transistor switch 22, and the main resistance u of the voltage reference circuit 可 can be adjusted by using the adjustment circuit ^ The adjustment resistor 21 is placed to finely adjust its absolute value, and the voltage output from the voltage spring circuit 1 is not lowered. (2) The present invention uses the adjustment circuit 2 to detect the presence or absence of the fuse 249, and whether the resistance 247 of the detection circuit 24 is increased or not. 14 ^ (1 98-12-24 '23' can be pressed to the logic Control 11 Μ, so that the logic control, turn '249' into the turn-on or turn-off of the body switch 22, and when the fuse 1 is directly connected, the circuit 24 is not connected to the voltage reference circuit, and the fuse 249 The current generation control circuit 1 loses its function to the voltage reference circuit 1, and the voltage is referenced to the rabbit Ueda. The invention uses the detection circuit 24 and the logic to make the device. • <Power adjustment reference circuit lm· ^铒 制 23 23' to the number of PAD χ 1 resistance 11 ugly dragon, without the need to increase to avoid taking up too much space.夕二四) The present invention uses the detection circuit 24 to inspect the debt measurement circuit 24 λ , and the presence or absence of the addition of the relative _ & == 9 « and ... to follow the sugar = indeed judged ::: Γ 二 险 249 249 The resistance value 'will satisfy the problem of making = and reducing the stock preparation. The example of the ^^^^Γ electrical circuit (bandgap) is only - said that the use of the force is not limited to the second of the present invention: two: the second: the technical spirit of the disclosure: the patent Fan, = the effect of the person is improved, Cheng is in line with the novelty, invention and progress of the special = elements, Mai Yi f proposed ", hope that the trial committee will grant the case as soon as possible, to protect the moon: Xingu" Any doubts, please do not hesitate to indicate that the inventor will try his best to cooperate with him.吝米 15 1325522 β^Ιι, 98-12-24 [Simple diagram of the diagram] Figure 1 is a circuit diagram of a conventional reference voltage generation circuit. Fig. 2 is a voltage output table of a conventional reference voltage generating circuit. Fig. 3A is a circuit diagram of the present invention. 3B is a schematic diagram of a logical conversion table of the present invention. 4 is a schematic circuit diagram (1) of the programmable detection circuit of the present invention. FIG. 5 is a schematic circuit diagram (2) of the programmable detection circuit of the present invention. 6 is a schematic circuit diagram of the programmable detection circuit of the present invention. [Main component symbol description] I: voltage reference circuit II: main resistor 12: output voltage Lu 2: adjustment circuit 21: adjustment resistor 22: transistor switch 23: Logic controller 24: detection circuit 241: first inverter 242: second inverter 16 1325522

98-12-24 243: third inverter 244: fourth inverter 245: first transistor switch 246: second transistor switch ^ 247, R: resistor 248: third transistor switch 249: fuse A : Reference voltage generation circuit A1: Main resistance A2: Voltage B: Fine adjustment circuit B1: Resistance B2: Fuses M0 to M5: Transistor

17

Claims (1)

1325522, 2 o'clock correction replacement page 98-12-24 X. Patent application scope: 1. An adjustment circuit for adjusting a reference voltage outputted from an output end of a reference voltage generating circuit, the reference voltage generating circuit includes a a main resistor, wherein: the first end of the main resistor is coupled to the output end of the reference voltage generating circuit, and the second end of the main resistor is coupled to a ground potential through the adjusting circuit, the adjusting circuit includes: a plurality of adjustment resistors connected in series between the second end of the main resistor and the ground potential; a plurality of first switches, wherein the ith first switch corresponds to the ith adjustment resistor, and the ith first The switch is connected in parallel with the ith adjustment resistor, i is a positive integer; a plurality of detection circuits, wherein the ith detection circuit corresponds to the ith first switch for detecting the ith detection circuit Whether a fuse is blown, or a relationship between a current flowing through the fuse and a current flowing through a resistor in the i-th detecting circuit, thereby generating a detecting signal; and a logic controller coupling The plurality of switches and the plurality of first detection circuit for all the combinations of the detection signal by the detection circuit looking from the plurality of logic conversion table is generated, and accordingly controls the plurality of first switch is turned on. 2. The adjustment circuit of claim 1, wherein the first switches are NMOS transistors. 3. The adjustment circuit of claim 2, wherein the first end and the second end of the i-th first switch are connected in parallel with the i-th adjustment resistor, and the third of the i-th first switch The end is coupled to the logic controller, 1S 1325522 98-12-24, wherein the first end of the i-th first switch is a drain, and the second end of the i-th first switch is a source, and the i The third end of the first switch is a gate. 4. The adjustment circuit of claim 2, wherein each of the detection circuits further comprises: a first inverter, wherein the input of the first inverter is configured to receive a power-on reset signal (p〇wer-on reset signal); a second inverter, wherein the input end of the second inverter consumes the output of the first inverter; a second switch, wherein the first end of the second switch is coupled to the first reverse The second end of the second switch is coupled to the ground potential; the second inverter, wherein the third end of the second switch; the third! The input to the device The output end of the fourth inverter is coupled to the input of the opposite state; the third end of the second switch in μ3 is connected to the second end of the second switch. The second wheel is connected to the fourth reverse input 钿' and the third end of the second switch is coupled to the buffer, wherein the input end of the buffer is lightly connected to the input end and the buffer The output terminal is in the reverse direction of the detection signal; and, "the controller is rotated by a fourth switch, wherein the trim signal is the first end of the fourth switch for receiving The second end of the four-switch is coupled to the power supply, and the third end of the fourth switch is coupled to the first end of the fuse and the second end of the resistor. The second end of the fuse is coupled to the ground potential. 5. The adjustment circuit of claim 4, wherein the second switch and the third switch are NMOS transistors, and the fourth The switch is a PMOS transistor. 6. The adjustment circuit of claim 5, wherein the first end of the second switch is a gate The second end of the second switch is a source, and the third end of the second switch is a drain. 7. The adjustment circuit of claim 5, wherein the first end of the third switch is a gate, a second end of the third switch is a drain, and a third end of the third switch is a source. 8. The adjustment circuit according to claim 5, wherein the fourth switch One end is a gate, the second end of the fourth switch is a source, and the third end of the third switch is a drain. 9. The adjustment circuit according to claim 2, wherein each detector The measuring circuit further includes: a second switch, wherein the first end of the second switch is for receiving a sense signal, and the second end of the second switch is connected to a power source; The third end of the third switch is coupled to the third end of the second switch, and the third end of the third switch is coupled to the ground potential; a fourth switch, wherein the a first end of the fourth switch is coupled to the first end of the third switch, and a second end of the fourth switch is coupled to the resistor One end, 1325522 98-12-24, and the second end of the resistor is coupled to the ground potential; a fifth switch, wherein the first end of the fifth switch is coupled to the power source, - and the fifth switch The second end and the third end are coupled to the third end of the fourth switch; -: a sixth switch, wherein the first end of the sixth switch is coupled to the power source, and the second end of the sixth switch is The first end of the fifth switch is coupled to the first end of the fifth switch, wherein the first end of the seventh switch is coupled to the first end of the third switch, and the second end of the seventh switch is coupled to the sixth end a third end of the switch, the third end of the seventh switch is coupled to the first end of the fuse, and the second end of the fuse is coupled to the ground potential; a buffer, wherein the input end of the buffer is coupled Connected to the second end of the seventh switch, the output of the buffer is coupled to the logic controller to output the detection signal; and an eighth switch, wherein the first end of the eighth switch is coupled to the a power supply, the second end of the eighth switch is configured to receive a trim signal, and the eighth open The third terminal is coupled to a first terminal of the fuse. The adjustment circuit of claim 9, wherein the second switch, the fifth switch, the sixth switch, and the eighth switch are PMOS transistors, and the third switch and the fourth switch And the seventh switch is an NMOS transistor. 11. The adjustment circuit of claim 10, wherein the first end of the second switch is a gate, the second end of the second switch is a source, and the third end of the second switch is Bungee jumping. 12. The adjusting circuit according to claim 10, wherein the first end of the 21 1325522 is open, the second end of the third switch is infinite, and the third end of the second switch is 5 For the source. For example, please use the light circuit mentioned in Item 1G to renew the switch. The first end is the gate, the second end of the fourth switch is the source, and the third end of the fourth switch is the bungee. . 14. If the application is requested, the first end is the source, the second end of the fifth switch is closed I and the third end of the fifth switch is the drain. ~15. As for the light circuit described in the application _ ω, wherein the first end of the switch is the source, the sixth open and the third end of the sixth switch. And the adjustment circuit according to the first aspect of the patent application, wherein the first end of the earth gate is a gate, the second of the seventh switch, and the third of the seventh switch The end is the source. ·,, '... Π Π · As in the adjustment circuit described in claim 10, == one end is the source, the second end of the eighth switch is the gate and the third end of the fifth switch It is not very good. 18. The adjustment circuit of claim 2, wherein the detection circuit further comprises: a first switch of the first switch, wherein the first switch of the second switch is a signal signal and the second switch is The second end is lightly connected to the ground potential, the third switch, wherein the first end of the third switch is coupled to a power source, the first end of the resistor, and the first end of the fuse, and the third switch The second end and the third end are coupled to the third end of the second switch; *, 22 1325522 Γ — ' -- __ 98-12-24 ' * ^ a fourth switch, wherein the first end of the fourth switch The second end of the fourth switch is coupled to the second end of the third switch; the fifth switch is coupled to the first end and the second end of the fifth switch Connected to the third end of the fourth switch, and the third end of the fifth switch is coupled to the ground potential; a sixth switch, wherein the first end of the sixth switch is coupled to the second end of the third switch a second end of the sixth switch coupled to the second end of the fuse; a seventh switch, wherein the seventh switch The second end of the seventh switch is coupled to the third end of the sixth switch, and the third end of the seventh switch is coupled to the ground potential; An eighth switch, wherein the first end of the eighth switch is configured to receive a trim signal, the second end of the eighth switch is lightly connected to the second end of the fuse, and the third end of the eighth switch is And a buffer, wherein the input end of the buffer is coupled to the second end of the seventh switch, and the output of the buffer is coupled to the logic controller to output the detect Test signal. 19. The adjustment circuit of claim 18, wherein the second switch, the third switch, the fourth switch, the sixth switch, and the eighth switch are NMOS transistors, and the fifth switch And the seventh switch is a PMOS transistor. 20. The adjustment circuit of claim 19, wherein the 23 1325522 98-1 9S-U second switch has a first end of the second end, a second end of the second switch, and a third end of the second switch The end is recorded. ^ is the adjustment circuit described in item 19 of the source--^^ patent scope, the first end of the switch is a drain, the third switch is the third open source and the third end is the source & is the interpole, # 22 · as in the adjustment circuit described in claim 19, the first end of the off is the drain, the second end of the fourth switch is the gate and the fourth switch The third end is the source. 23. The adjustment circuit of claim 19, wherein the first end of the switch is the source, the second end of the fifth switch is the gate, and the third end of the fifth switch is the pole. The adjustment circuit of claim 19, wherein the first end of the f-switch is a gate, the second end of the sixth switch is a drain, and the third end of the sixth switch For the source. 25. For the adjustment circuit described in claim 19, the first end of the off is the gate, the second end of the seventh switch is the source, and the third end of the fifth switch is the drain. . 26. The adjustment circuit of claim 19, wherein the first end of the product is a gate, the second end of the eighth switch is a drain, and the third end of the eighth switch For the source. _ 27. The adjustment circuit of claim 1, wherein if the current of the fuse is less than the current flowing through the resistor, the i-th path outputs a signal of "logic OR, OFF"; Conversely, if the current flowing through the lightning current is greater than the current flowing through the resistor, the ith detection circuit outputs a signal that is logic 1" or "on". twenty four