TWI324774B - Biasing and shielding circuit for source side sensing memory - Google Patents

Description

1324774

- Sanda number: TW3728PA IX. Description of the invention: 1. Field of the Invention The present invention relates to a circuit for biasing and shielding, and in particular to a source-sensing memory (Source · « Side Sensing Memory) The circuit of dust and shadow. [Prior Art] With the development of technology, non-volatile memory, such as flash memory, is widely used in various electronic products. In the reading operation of recording data in the flash memory device, the sensing circuit is used to sense the memory cell current of the target memory cell (Cell), so as to refer to FIG. 1, which shows the conventional flash memory. The intent of the memory cell matrix of the device. When the memory cell Ca is accessed, the memory cell current II of the memory cell Ca should be sensed to determine the data value of the memory cell Ca storage. During the sensing operation, the sensing circuit 100 is coupled to the memory cell Ca. Since the memory cell current II is difficult to detect and mask, the sensing current 12 is utilized in the sensing operation to know the size of the memory cell current 记忆 of the memory cell Ca. The memory cell current II and the sense current 12 satisfy the equation: 11 = 12 + 13 13 is the leakage current shunted through the memory cell Cb, wherein the memory cell Cb is adjacent to the memory cell Ca. The leakage current 13 will affect the accuracy of the sense current II and affect the correctness of the data values sensed by the sense circuit 100. The smaller the difference between the memory cell current and the sense current, the more accurate the sensing operation performed by the sensing circuit 100. Here, the difference between the memory cell current and the sense current is defined as 1324774

- Sanda number: TW3728PA error current. In this way, how to design a flash memory circuit with a small error current and a relatively accurate data value sensing result is one of the directions that the industry is constantly striving for. SUMMARY OF THE INVENTION The present invention relates to a bias and shingling circuit that can bias a target memory cell (Cell) to have substantially the same voltage level as a source electrode voltage of an adjacent memory cell. quasi. The circuit of bias voltage and shielding can have a private effect to avoid the memory cell current of the target memory cell being subjected to the source of the adjacent memory cell; the source of the body is Lei Ren Xi;; 鄕.,,. & :: Effectively improve the accuracy of data values and improve the sensing speed of the sensing unit. According to the invention, a biasing (Biasing) and Shielding are used to sense the memory (STM heart ^ (Cell) output, ff extreme sensing memory target memory current The source path of the first adjacent memory cell includes a pre-discharge F flow to the sensing node of the sensing unit, the voltage pull-down unit and the first-connected and the second press unit, the first and second electrical signals The position of the pre-discharge device is used to be at the first control voltage level. The::== sets the voltage level of the sensing node to negative to respectively target; (4) the unit responds to the second bias position The quasi-voltage bias voltage to the source voltage of the second I and the source current of the adjacent memory cell pass through the first and second quasi-. wherein the 'sensing current and the source current are respectively the first and second _,»-bias The level is close to the ground level. The low level is used for the second control signal to be low level X S- > 7 1324774

Sanda number: TW3728PA column. The multiplexer (Multiplexer) 24 is configured to provide the bungee bias signal DB to the drain of the target memory cell or provide the DB to the adjacent memory cell via the corresponding bit line in response to the address signal. Cell. The column decoder 14 is coupled to Word Lines WL1 WLW, which are arranged in parallel with the bank memory cells in the memory cell array 16. The column decoder 14 is responsive to the address signal to provide the word signal w to the bank memory cells in the memory cell array. In response to the corresponding bungee-bias signal DB and the character signal W', the cell of the target memory cell is turned on, and the imaginary pole: stream I(10) is generated. The sensing unit 22 is configured to perform a light measurement current according to the sensed current value of the sensed current (=4) of the memory data value of the sense memory (the sense current) connected to the source of the transistor ω) of the target memory cell. IS(10) is close to the source current I(iJ). For example, the drain bias signal D^ provided by the sense bit line BL4 is responsive to the source current t generated by the word signal W (two: the line WU is T (1, 3). With the source current 叩, 3 ) corresponding to the sense current crystal element line BL3 output. L (, 3) is used by the bit masking circuit 20 to avoid subtracting the source current I of the transistor Taj-D of the detonator (〇(1,ji is subjected to the adjacent memory current IS(i,j) to sensing) Unit 2 〇. The next "impact" and provide the operation of sensing the crystal T (U) as an example. For the shielding of the electrical tracking system 20, please refer to Figure 3 and Figure 4, the third operation Description: The detailed circuit diagram of the circuit 20, the fourth drawing of the factory diagram '\ is not the waveform diagram of the related signal of the mask 20 in the second figure. The sense 9 is not the shielding circuit in the third figure. The voltage detector is used to judge the sense Measure: 2: 'For example, the voltage level of voltage detection is higher than

Q HZ4//4

Sanda number: TW3728PA is lower than the reference voltage level or lower than the reference voltage level to determine the value of the memory data in the target memory cell. The masking circuit 20 includes a pre-discharge device 202, biasing singles 204, 206, voltage pull-down units 2〇8, 21〇, and a connection unit 212. Pre-% device 202 is connected to sense node sn' to control the voltage level of the sense node. The pre-discharge device 202 includes, for example, a transistor transistor

Ml is an N-type Metal Oxide Semiconductor (MOS) transistor. The transistor M1 includes a gate, a drain, and a source, which respectively receive the control signal SCi and are coupled to the sense. Measure the node and receive the negative voltage level VLN. During the period τρι, the control signal milk is caused, the transistor M1 is turned on and the voltage level of the sensing node SN is pre-discharged to the negative electric gate level VLN. In the period τρ2, the control signal SC2 is disabled, and the transistor M2 is turned off. The bias voltages 7L 2〇4 and 2〇6 are respectively connected to the transistors 吼3) and the source of T(l,2) and are respectively used to bias the electric crystal voltage to make the electric Β俨htj The source of the source solar TG, 3) and the source voltage of T (l, 2) are close to a bias voltage level. Hemiplegia 蜃 蜃 蜃 兀 204 and 206, for example, respectively, include transistors M2 and M3. t Β于Ώ (7) 匕 斗 斗 二 二 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日The gates of the transistors M2 and M3 are connected to the source of the transistors T(l,3) and Τπ, and the poles are respectively connected to Christine.) 210. The ridges M2 and m3 are turned on in response to the bias voltage a, the Τ B 曰 , and the bias level VLB2 , and the source voltages of the bodies M2 and M3 satisfy the equation:

Ve _ M2 = VLB2 + Vth M2 1324774

- Sanda number: TW3728PA . Ve_M3 = VLB2 + Vth_M3

Ve_M2 and Ve-M3 are the source voltage levels of transistors M2 and M3, respectively, and Vth_M2 and Vth-M3 are the critical voltages of transistors M2 and M3, respectively. The threshold voltages Vth_M2 and Vth__3 are, for example, substantially equal. For example, the source voltage levels of the 'diodes D1 (1, 3) and T (l, 2) are substantially equal. The bias level VLB2 is, for example, a negative voltage level, and the source voltage levels of the transistors M2 and M3 are both close to the ground level VLG. The sense currents IS(1, 3) and IS(1, 2) flow through the transistors M2 and V13, respectively. The voltage pull-down units 208 and 210 are coupled to the gates of the transistors M2 and M3, respectively, to pull the drain voltage levels of the transistors m2 and M3, respectively. The voltage pull-down units 208 and 210 include, for example, transistors M4 and M5, respectively, and the transistors M4 and M5 are, for example, p-type M〇s transistors. The gates of the transistors M4 and M5 receive, for example, the control signal SC2, and the source of the drain receiving ground level VLG' is coupled to the drains of the transistors m2 and M3, respectively. During the period τρι, the control signal SC2 is enabled and is essentially a negative voltage level. At this time, the transistors M4 and M5 are turned on, for example, to pull down the drain voltage levels of the transistors M2 and M3, respectively, so that the drain voltage levels of the transistors M2 and M3 are close to the ground level VLG. Thus, during the period τρι, the source voltage levels of the transistors M2 and M3 are substantially close to the ground level VLG, and the source voltage levels of the transistors T(1, 3) and D (1, 2) are also close. The grounding level is VLG. The control signal SC2 is, for example, an inverted signal of the control signal SC1. The connection unit 212 is coupled to the drain of the transistor M2 and the sensing node SN' to provide a sensing current is(i, 3) flowing through the transistor milk to the sensing node 11

Sanda number: TW3728PA SN, for the capacitor (^ charge. Connection unit M6. Transistor _ for example, n-type M〇s slightly daily, including the transistor including gate, immersion and source. Transistor M6: 曰The body 'transistor M6 package SC2, the source is coupled to the sensing node SN, and the ^ pole receiving control is simple. In the period of the claw towel, the transistor to the body of the transistor M2 and the sensing node S ]Si. Such crystal & 'sense current IS (1 is supplied to the capacitor Cl, while the sense node SN hair, L 1 can be related to the tears, 丨 流 stream IS (1, 3) and charging The product of time, so, ], the sensing unit 22 can find the data value in the target memory cell, and the value of the 楗 楗 is close, so that the drain of the transistor T (15 2) is between the source and the source. The cross-compacting f is small. For example, the source voltage levels of the transistors M3 and M2 are equal to % microvolts (Millivolt 'mV) and 214 mV, respectively, due to the source spot of the transistor τ(ι, 2). The circuit current of J 7 soil, '~叩妳柽 current 1 (1, 3) is very small. Thus, the bias voltage and shielding circuit 2〇 can effectively reduce the current, so that the source current is 1 (1, 3) and the sense current IS(1,3) is ^, so that the correct value of the data value sensed by the sensing circuit 22 is relatively high, and the source voltage is 1 (1, 2), that is, The leakage current of the source current I(u) is not small. Therefore, the bias voltage is similar to that of the leakage current due to the leakage of the source of the transistor M2 during the period TP2. Up to 2.6 volts (〇-(-2.6)), and substantially larger than the difference between the gate-source voltage across the transistor m2 and the voltage of the electric 3' body M2' during the period TP], the transistor M2 is substantially biased in the saturation region (Saturati〇n Region). Using the characteristics of transistor M2 during which TP2 is biased in the saturation region, the equivalent capacitance seen at the sensing node SN is substantially smaller than in the conventional source. The sensing capacitance of the extreme sensing memory SN sees the equivalent capacitance. For example, 12 .< S- 丄JZ4//4 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ & m m 屯 (4) brother package fan can be improved, the speed of fine work can be effectively improved. Bias and shielding circuit 20 also includes negative snow. P_P) 222, level shift and logic unit 2 ^ ^ pump Tao café...arge To provide a negative voltage level negative voltage VLN 216. The charge pump 222 bit nodes Zhang quasi two negative voltage; ^ other sense, for example to set a level shifting negatively charged Pang Ren Μντχτ, 214 and 216 for early Wu The

^ 7 knives provide control signals SCI and SC2. A _, control signal SCU and SC2 high (four) (four) ^ VLG, control signal SC1, Beishang 4 at the grounding position, you are allowed to enter the low level of ντχτ ^, for example, substantially equal to the negative VLN. The biasing and shielding circuit 2 further includes a regulator f m) 2: 4 ′: the peripheral 224 generates a daily bias level VLB2 in response to the reference signal Ref and the power signal. The power signal nv is, for example, referred to by the negative power pump 222, which has a negative voltage level.

Referring to FIG. 2, the flash memory 1 of the present embodiment further includes a gamma multiplexer (touch (8) is called 18, which is coupled to the bit line to make a memory cell in the corresponding N-line memory cell. The sense current is generated. The γ multiplexer 18 responds to selecting two bit lines of the signal connection bit lines BL1 BLBLN on the fresh and old flow row ss to the source of the transistor milk and M3. For example, When the extreme bias unit 12 and the column decoder 14 provide the corresponding infinite bias signal DB and the word signal w to drive the transistor τ(ι, 3), the γ multiplexer 18 makes the bit lines BL3 and BL2 light, respectively. Connected to the transistor and the source of M3. Thus, the 'biasing and shielding circuit 2' can bias the source voltages of the transistors τ(1,3) and T(U) to near ground. And via 13 1324774

- Sanda number: TW3728PA. Y multiplexer 18 provides sense current 1 (1, 3) to sense unit 22. Although in the present embodiment, only the operation of connecting the bit lines BL3 and BL2 to the sources of the transistors M2 and M3 respectively by the Y multiplexer 18 is taken as an example, the Y multiplexer 18 is more responsive to Select the signal on the signal bus SS, and its value signal to connect the other bit lines to the sources of the transistors M2 and M3. In this way, the sensing unit 22 can detect the sensing current of the memory cells located in other memory cells, and the biasing and shielding circuit 20 can prevent the sensing current of the target memory cell from being the source of the transistor of the memory cell adjacent thereto. The effect of the pole current |. Although the operation of the bias voltage and shading circuit 20 is explained in the present embodiment only to avoid the case where the sensing current IS (1, 3) of the target memory cell is affected by the source current I (1, 2), The operation of avoiding the sensing current of other target memory cells being affected by the corresponding source current can be obtained by analogy with the operation of the foregoing example. In the biasing and shielding circuit 20 of the present embodiment, the biasing unit 206 and the voltage pulling unit 210 form a shielding device for preventing the sensing current of the target memory cell from being received by the source current of the adjacent memory cell. Shadow ^ sounds. Although the biasing and shielding circuit 20 including a shielding device is taken as an example in the present embodiment, the biasing and shielding circuit 20 of the present embodiment is not limited to including only one shielding device. For example, please refer to FIG. 5, which illustrates a second circuit diagram of the biasing and shielding circuit 20 in accordance with the present embodiment. In the biasing and shielding circuit 20' of Fig. 5, another shielding device including the biasing unit 206' and the voltage pulling unit 210' is incorporated in the biasing and shielding circuit 20 of Fig. 3. The biasing unit 206' and the voltage pulling unit 210' are respectively used to bias and pull the source voltage of the transistor T(1, l) 14 1324774

- Sanda number: TW3728PA Low voltage τ (1, 1) voltage level. Without this 'biasing and shielding circuit, the source voltage of the transistor T(u) can be effectively biased to lower the source current (!, 〗) of the Thai crystal T(l, l). Thus, the 'biasing and shielding circuit can effectively prevent the sensing current IS(1,3) from being interfered by the source currents 1(1 2) and 1(1,3)' and boost the sensing current is(1,3) ) accuracy. In the biasing and shielding circuit 20, the transistors M2, M4, η iVlb and the capacitor C1 form a sensing device for providing the sensing power of the target memory cell.

Flow to the sensing unit 22. Although in the present embodiment, the case where the bias voltage and the mask circuit 20 include only one sensing device is taken as an example, the biasing and shielding circuit 20 of the embodiment of the present invention is not limited to only including A sensing device. For example, please refer to FIG. 6, which illustrates a third circuit diagram of the biasing and shielding circuit 20 in accordance with the present embodiment. In the biasing and shielding power 1 way 20" of Fig. 6, the other connecting unit 212 is added to the circuit structure of the biasing and shielding circuit. The biasing unit 206, the voltage pulling unit 21 and The single 70 212' forms another sensing device to provide the detection current IS (1 and iS (1, 3) to the sensing node SN. Thus, the biasing and shielding circuit 2 可 effectively provides the sensing current IS(1,2) (ie, the source current In 3 > is a 漏, the leakage current shunted through the transistor T (1, 2)) to the sensing node SN. The sensing node is connected to the sensing current IS The sum of (1,3) and IS(1,2), and the sensing unit 22, the sensing current actually received, is measured compared to the sensing unit/yuan salt in Figures 3 and 5. The sensing current system is closer to the source current 1 (1, 3) ^ such that the voltage and shielding circuit 20" can effectively improve the sensing unit 22, and the accuracy of the current measurement. e, ·! In the foregoing examples, the bias and occlusion circuits 2〇, 2〇, and 2〇,,,, 15 1324774

- Sanda number: TW3728PA has one sensing and one shielding device, one sensing and two shielding devices and two sensing devices and one shielding device. However, the number of sensing devices and shielding devices included in the biasing and shielding circuit is not limited to the configuration disclosed in the embodiment.

The biasing and shielding circuit of this embodiment biases the source voltage of the target memory cell and the transistor of the adjacent memory cell to a level close to the ground. Therefore, the sensing current of the target memory cell can be effectively prevented from being affected by the source current of the adjacent memory cell. In this way, the traditional source extremes can accurately improve the accuracy of the data values detected by the flash memory. When the sense current 1 (1, 3) is supplied to the sensing node, the transistor M2 in the bias and concealer circuit of this embodiment is qualitatively biased in the saturation region. Thus, the equivalent capacitance seen at the sensing node SN is much smaller than the equivalent capacitance seen on the sensing node of the conventional source terminal sensing flash memory, and the charging speed and sense of the voltage on the sensing node SN The sensing operation speed of the measuring circuit can be effectively improved compared to the conventional method. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 16 1324774

- Sanda number: TW3728PA T(i,j): transistor BL1~BLN: bit line WL1~WLM: word line SS: select signal pin SN: sense node 202: pre-discharge device 204, 206: partial Pressure unit 208, 210, 210, 206': voltage pull-down unit

212, 212': connection unit 214, 216: level shifting and logic unit 222: negative charge pump 224: regulator

Ml~M6: transistor C1: capacitor

18

Claims (1)

1324774 Sanda number: TW3728PA X. Patent application scope: . Κ - Biasing and Shielding circuits, application - source, extreme sensing, source side Sensing Memory, To avoid one of the source extreme sensing memories, the target memory cell (Cell) output 谙 冽 current is received by one of the first adjacent memory cells (S〇urce), and provides the sense Measure the current to one of the sensing units, and the circuit includes: ^ Turn on the pre-emphasis device to use the first control signal when the level is high enough. The voltage level of the lang point is up to a negative voltage level; the second biasing unit: the first biasing unit and the second biasing unit are respectively responsive to a first reading pressure level to respectively source the target memory cell The voltage and the adjacent voltage are biased to a first bias level, wherein the sensed source current flows through the first and second bias units, respectively. The level is close to a ground level; - the first - the first voltage pull low ^ and the second voltage pull low unit The source voltage of the target memory cell and the neighboring memory cell is pulled close to the ground level when the λ signal is low, and the receiving unit is used to connect the unit to the high first control signal. Passing the sensing current to the first biasing unit on time, and rotating the sensing sensing node; wherein, the first adjacent memory cell has a drain and the target memory cell coupling 2 The circuit described in the first paragraph of the patent scope includes: a negative charge pump (Charge Pump) 'to provide - negative voltage level to 19 1JZ4 / / 4 i up number: TW3728PA status; and - f five crystal 'Includes a gate, a source and a drain, respectively receiving the second control gamma, the city to the third bias unit, and receiving the ground level. 6. As described in the scope of claim The circuit, wherein the connecting unit comprises: - a sixth transistor comprising a gate, a source and a drain, respectively receiving, a second (four) shouting, a secret female node and a secret to the first biasing unit. The circuit of the seventh aspect of the invention, wherein the sensing node 8. The circuit of claim 1, wherein the circuit of claim 1 further comprises: a third biasing unit for biasing the second biasing level in response to the second biasing level Two adjacent, the source voltage of the memory cell is substantially equal to the first bias level 'its +13⁄43⁄2 two adjacent memory cell secret current stream unit; and not one rain! The first pressure pull low single, use The second control signal is low, and the source of the second adjacent memory cell is turned to be close to the ground level; wherein the second adjacent memory cell has a drain line and the first adjacent memory cell The circuit described in claim 8 further includes: a (four) second connection unit 7 for "the source of an adjacent memory cell when the second control signal is at a high level" a pole current, and outputting a source current of the first adjacent memory cell to the sensing node. -< SO- 21