TWI323347B - Capacitance measuring device and method thereof - Google Patents

Capacitance measuring device and method thereof Download PDF

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TWI323347B
TWI323347B TW96111316A TW96111316A TWI323347B TW I323347 B TWI323347 B TW I323347B TW 96111316 A TW96111316 A TW 96111316A TW 96111316 A TW96111316 A TW 96111316A TW I323347 B TWI323347 B TW I323347B
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charging
discharging
measuring
tested
counting
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TW96111316A
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TW200839254A (en
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chun liang Li
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Cyrustek Co
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1323347 【發明内容】1323347 [Summary content]

鑒於上述之發明背景中,為了解決上述電容值量判 =上以及在量測之精财上關題,本發明提供—種電容值之量游更 ,,主要是制—個除縣置來調整駿裝置的累加數值。雷 容值之量測時’均將脈波訊號先經過除職置除以Μ,錢^于N次 的充電與放電,計數裝置則在Ν次的放電_累加每 除過的頻率,因此計數裝置中所累加值,則可以逹到平均的 得到-個歡的輸出數值1此,本㈣之—主要目的在提供一種電 容值量測裝置,使每個量測之電容值係經由計數裝置的累加,使得量 測值能夠達到平均的結果,因此可以測得—個穩定的電容值。 本發明之主要目的在提供_種電容值量職置,其可藉由選擇 運算的週期長短及次數,可消除量測時的市電之干擾。 本發明之還有-主要目的在提供一種電容值量測裝置,其可以藉由 縮小充放電裝置之電阻並提高計數脈波之頻率來提供一個快速的電容 值量測架構8In view of the above-mentioned invention background, in order to solve the above-mentioned capacitance value judgment and the measurement of the fine money, the present invention provides a measure of the capacitance value, which is mainly a system-by-county adjustment. The cumulative value of the device. When measuring the value of the thundering value, the pulse signal is first divided by the de-listing, the money is charged and discharged for N times, and the counting device is discharged at the time of _ accumulating the frequency of each division, so counting The accumulated value in the device can be averaged to obtain an output value of 1 -, the main purpose of this (4) - to provide a capacitance value measuring device, so that the capacitance value of each measurement is via the counting device Accumulating, so that the measured value can reach the average result, so a stable capacitance value can be measured. The main object of the present invention is to provide a capacitance value position, which can eliminate the interference of the commercial power during measurement by selecting the length and number of cycles of the operation. Still another object of the present invention is to provide a capacitance value measuring device which can provide a fast capacitance value measuring architecture by reducing the resistance of the charging and discharging device and increasing the frequency of the counting pulse wave.

依據上述之目的,本發明首先提供一種電容值量測裝置包括:一 個用以提供-第-參考電壓及-第二參考電壓之電壓產生裝置:一個 與電壓產生裝置連接之比較裝置;—個充電及放電裝置,其一端與電 壓產生裝置之第-參考電壓連接,而另—端則與比較裝置之一第二輸 入端連接;一個與比較裝置之輸出端連接之脈波產生裝置,用以提供 一個脈波訊號;一個與脈波產生裝置連接之除頻裝置,可將脈波訊號 除以一個設定值(Μ); —個與除頻裝置連接之計數裝置,可於充電及 放電裝置進行放電期間進行計數;以及一偭控制裝置,用以控制充電 及放電裝置、脈波產生裝置及除頻裝置,並提供除頻裝置之設定值 (Μ);其中當進入放電期間且比較裝置的輸出狀態改變時,則關閉脈 6 波產生裝置並由控姆置再啟動充電及放 置之啟動次數達到另-設定值W時,則由一顯八充電及放電裝 置之累計值。 不裝置顯示出计數裝 本發明接著提供-種t容值制之方法,包括 係對-個剌電容Cx進行 細—充電程序, 容Cx之蕾原㈣ 丁一放電程序,係於待測電 數程序传=1至Vrl後’隨即經進行放電程序;然後,執行-個計 ΪΓ比=開始時,由一個計數裝置進行•再接著, 較係經由一個比較裝置將參考電壓與放電電位進行比According to the above object, the present invention firstly provides a capacitance value measuring device comprising: a voltage generating device for providing a -first reference voltage and a second reference voltage: a comparing device connected to the voltage generating device; And a discharge device having one end connected to a first reference voltage of the voltage generating device and the other end connected to a second input end of the comparing device; a pulse wave generating device connected to the output end of the comparing device for providing a pulse wave signal; a frequency dividing device connected to the pulse wave generating device, which can divide the pulse wave signal by a set value (Μ); a counting device connected to the frequency dividing device, can discharge in the charging and discharging device Counting during the period; and a control device for controlling the charging and discharging device, the pulse wave generating device and the frequency dividing device, and providing a setting value (Μ) of the frequency dividing device; wherein when the discharging period is entered and the output state of the device is compared When changing, the pulse 6 wave generating device is turned off and the control is restarted by the control device and the number of starts of the placement reaches another set value W, then Charging and discharging means integrated value of the counter. The device does not display the counting device. The invention then provides a method for the t-capacity system, including performing a fine-charging procedure for the tantalum capacitor Cx, and the Cx ray original (four) Ding-discharge procedure is tied to the electricity to be tested. After the program passes =1 to Vrl, the discharge program is then performed; then, the execution-to-count ratio = at the beginning, by a counting device. • Then, the reference voltage is compared with the discharge potential via a comparison device.

Γ之,執行一充電及放電之累計程序,係將前述執 丁 序及=程序進行累計,直計值達到_個設定次數N 植# ¥並』不量測值其中於放電程序中提供~~脈波訊號至一個除 頻裝置’並且除頻裝置將脈波訊號除以一設定值M後由一計數裝置 執行該累計程序。 【實施方式】 本發明在此所探討的方向為__種電容值制之裝置及其量測之方 法特別疋種可以藉由除頻裝置及計數裝置之累加而達到一個平均 之電谷里測值。為了能徹底地瞭解本發明,將在下列的描述中提出詳 盡的步驟及其電路的組成。顯然地,本發明的施行絲限定於電容值 量測裝置之技藝者所熟習的特殊細節。另一方面,眾所周知的電容值 Ϊ測裝置或量測步驟等’並未描述於細節中,以避免造成本發明不必 要之限制。本發明的較佳實施例會詳細描述如下,然而除了這些詳細 描述之外,本發明還可以廣泛地施行在其他的實施例中,且本發明的 範圍不受限定,其以之後的專利範圍為準。 首先請參考第1圖,係本發明之電容值量測裝置的功能方塊示意 圖。如第1圖、所#,本發明之電容值量測裝置包括以下幾個I要部分: 一個用以提供第—參考電壓㈤)及第二參考電M (Vr2)之參考電 麼產生裝置30’· -個《電及放電裝置40,其一端與參考電虔產生裝置 30之第-參考電壓(Vrl)連接,一個比較裝置5〇,其第一輸入端與 第二參考電壓(Vr2)連接,而其第二輸入端與充電及放電裝置40連 接;-個與比較裝置5〇之輸出端連接之脈波產生裝置的,用以提供一 個脈波職⑷;-健脈波產生% p連^ %,可將 脈波域_ —健定值(M);-藏除射.置後裝置 8〇 ’可於充電及放電裝置40進行放電綱進行計數;錢-個控制裝 置10用以控制充電及放電裝置4〇、脈波產生裝置6〇及除頻裝置7〇, 並提供除縣置7G之設定值(M);然後由__個計數裝置⑼來累計每 一個放電週期中所累加之頻率。 為了進一步說明本發明之電容值量測裝置之詳細運作過程,請繼 續參考第2圖。第2 _本發明相應第丨圖中的充電及放電裝置以及 脈波產生裝置之實際·。如第2圖所示,充電及放電裂置仙包括電 阻R1〜R3、開㈣S1及S2以及;^測電容Cx,其中ri為一可調整電阻 值之可變電阻,而開關S1及S2由控制裝置⑴來控制。參考電壓產生 裝置(Reference voltage generator) 30是用來產生穩定的參考電位Vrl 及Vr2 ’其中參考電位Vr>2也可藉由參考電壓產生裝4 %直接提供一 電壓值,其也可以經由一個分壓裝置2〇來將參考電位Vrl以分壓電路 來產生參考電位Vr2,例如第3圖中的電阻RQR5所示。 當進行電容量測時’控制裝置1〇 t先驅動充電及放電裝置4〇中 的開關S1啟動(ON),而關閉開關S2 (〇FF),此時的充電及放電裝 置40進入一個對待測電容Cx的充電程序,係由參考電壓產生裝置3〇 之參考電位Vrl㈣開關si及電阻R3對制電容以紐充電,使得 1323347 待測電容Cx充電至與參考電位Vrl等電位,要強調的是,為了使待測 電容Cx能夠很快的充電至與參考電位Vrl的位準,通常電阻幻會使 用一個小電阻。此時’比較裝置50的第一輸入端電壓為參考電位細, 而比較裝置50的第二輸入端電壓為待測電容Cx經過充電後之電位 Vex ’很明顯地,此時待測電容Cx之充電電位—是大於參考電位 心接著,控制裝置10驅動充電及放電裝置4〇中的開㈣關閉() 而開關S2啟動(ON) ’此時充電及放電裝置4〇則進入一個放電之週 期,會由待測電容Cx經由開關S2與電阻R1及幻連接至參考電位 Vr3端點進行放電程序,在本發明的實施例中,參考電位端點為一 接地點。此時的制電容之電位Vex會隨著放電的_持續降低電壓 值,其中FU、R2做為制電容Cx的放電電阻,並藉由婦可變電阻 幻,可調整放電電阻大小,進而改變放電速率^在放電之週期中,比 較裝置50則持續比較待測電容Cx之電位Vcx與參考電位之大小。 然而,在控制裝置10驅動充電及放電裝置4〇進入放電週期的同 時,其也驅動開㈣S3啟動’使得脈波產生裝置6〇可以將一個脈波訊 號ck送入除頻裝置7〇 ’然後除頻裝置7〇經由控制裝置1〇所提供的一 健定數值Μ作為除數,將脈波訊號ck除至適當的脈波訊號此,也 就是說’將脈波訊號ck之頻率fck經由除頻裝置除至頻率胞(即 fck/M-fckl ’其中fck,fcki分別為ck與ckl之頻率)後,再將頻率fdd 送至計數裝置80進行累加。因此,Μ S3可由控織置ίο與比較裝 置50的輸出邏輯來控制。在此放電職中,比較裝置50則持續比較 待測電容Cx之電位Vcx與參考電位Vr2之大小。當待測電容&之 Vex電位小於參考電位Vr2時,則比較裝置5〇的輸出邏輯會改變,此 時會將關S3關閉(〇FF),目此脈波產轉置6()會停止並且也會使 計數裝置80停止計數。接著,控制裝置1〇會再次驅動充電及放電裝 置40進入另一次的待測電容Cx之充電程序以及放電程序,其過程與 9 上述過程_,直㈣軸 -個設定之她N時,則此_特# β魏钱置4G的次數達到Γ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The pulse signal is sent to a frequency dividing device' and the frequency dividing device divides the pulse signal by a set value M and then executes the cumulative program by a counting device. [Embodiment] The device discussed in the present invention is a device with a capacitance value and a method for measuring the same. In particular, an average voltage trough measurement can be achieved by accumulating the frequency dividing device and the counting device. value. In order to fully understand the present invention, the detailed steps and the composition of the circuit will be presented in the following description. Obviously, the application wire of the present invention is limited to the specific details familiar to those skilled in the art of capacitance measuring devices. On the other hand, the well-known capacitance value detecting means or measuring step, etc., is not described in detail to avoid unnecessarily limiting the present invention. The preferred embodiments of the present invention are described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the scope of the following patents. . First, please refer to Fig. 1, which is a functional block diagram of the capacitance value measuring device of the present invention. As shown in FIG. 1 and #, the capacitance value measuring device of the present invention includes the following I main parts: a reference power generating device 30 for providing a first reference voltage (5) and a second reference power M (Vr2). '··Electrical and discharge device 40, one end of which is connected to the first reference voltage (Vrl) of the reference power generating device 30, and a comparison device 5〇 whose first input terminal is connected to the second reference voltage (Vr2) And the second input terminal is connected to the charging and discharging device 40; a pulse wave generating device connected to the output end of the comparing device 5〇 for providing a pulse wave (4); ^ %, the pulse wave domain _ - Jian Jian value (M); - Tibetan removal shot. Post-device 8 〇 ' can be counted in the charging and discharging device 40; the money control device 10 is used to control The charging and discharging device 4〇, the pulse wave generating device 6〇 and the frequency dividing device 7〇, and providing a set value (M) of the 7G in addition to the county; and then accumulating each of the discharging cycles by the __ counting device (9) The frequency. In order to further explain the detailed operation of the capacitance value measuring device of the present invention, please refer to FIG. The second embodiment of the present invention relates to the charging and discharging device and the pulse wave generating device. As shown in Fig. 2, the charging and discharging cracking includes resistors R1 to R3, opening (four) S1 and S2, and measuring capacitance Cx, where ri is a variable resistance of an adjustable resistance value, and switches S1 and S2 are controlled. The device (1) is controlled. The reference voltage generator 30 is used to generate stable reference potentials Vrl and Vr2', wherein the reference potential Vr>2 can also directly provide a voltage value by the reference voltage generating device, which can also be supplied via a fraction. The voltage device 2 turns the reference potential Vrl into a reference voltage Vr2 by a voltage dividing circuit, for example, the resistance RQR5 in FIG. When performing the capacitance measurement, the control device 1〇t drives the switch S1 in the charging and discharging device 4〇 to start (ON), and turns off the switch S2 (〇FF), at which time the charging and discharging device 40 enters a test. The charging program of the capacitor Cx is charged by the reference potential Vrl (four) switch si and the resistor R3 of the reference voltage generating device 3 to charge the capacitor, so that the capacitor 3x to be tested is charged to the potential equal to the reference potential Vrl, it is emphasized that In order to enable the capacitor Cx to be charged to be quickly charged to the level of the reference potential Vrl, a resistor is usually used for the resistor. At this time, the voltage of the first input terminal of the comparison device 50 is thinner than the reference potential, and the voltage of the second input terminal of the comparison device 50 is the potential Vex of the capacitor Cx to be measured after being charged, and the capacitance Cx to be measured is at this time. The charging potential is greater than the reference potential. Next, the control device 10 drives the charging and discharging device 4A to turn on (4) turn off () and the switch S2 to turn on (ON). At this time, the charging and discharging device 4〇 enters a discharge cycle. The discharge procedure is performed by the capacitor Cx to be tested via the switch S2 and the resistor R1 and the terminal connected to the reference potential Vr3. In the embodiment of the present invention, the reference potential end point is a ground point. At this time, the potential Vex of the capacitor will continuously decrease the voltage value with the discharge _, wherein FU and R2 are used as the discharge resistor of the capacitor Cx, and the discharge resistor can be adjusted by the varistor of the resistor, thereby changing the discharge. Rate ^ During the period of discharge, the comparing means 50 continues to compare the potential Vcx of the capacitor Cx to be measured with the magnitude of the reference potential. However, while the control device 10 drives the charging and discharging device 4 to enter the discharge cycle, it also drives the ON (4) S3 start so that the pulse wave generating device 6 can send a pulse signal ck to the frequency dividing device 7〇 and then divide The frequency device 7〇 divides the pulse signal ck into an appropriate pulse signal by using a set value Μ provided by the control device 1〇 as a divisor, that is, 'dividing the frequency fck of the pulse signal ck by frequency division After the device is divided into frequency cells (i.e., fck/M-fckl 'where fck, fcki are the frequencies of ck and cgl, respectively), the frequency fdd is sent to the counting device 80 for accumulation. Therefore, Μ S3 can be controlled by the output logic of the comparison device 50. In this discharge operation, the comparing means 50 continues to compare the magnitude of the potential Vcx of the capacitor Cx to be measured with the reference potential Vr2. When the Vex potential of the capacitor to be tested is less than the reference potential Vr2, the output logic of the comparison device 5〇 will change, and the off S3 will be turned off (〇FF), and the pulse transposition 6() will stop. It also causes the counting device 80 to stop counting. Then, the control device 1 再次 again drives the charging and discharging device 40 to enter the charging program and the discharging program of the capacitor Cx to be tested another time, and the process is the same as the above process _, the straight (four) axis-set of her N, then _ special # β魏钱定4G times reached

Cx之電容值,“ #數裝置8G中之g加值即為待測電容The capacitance value of Cx, "The g-value added in the #8 device 8G is the capacitance to be tested.

Cx之電令值’最後將此累加值顯示於顯示器中。 很明顯地,本發明之電容 7〇來調整計數裝置8〇的累加♦ ^要是—個除頻裝置 訊號故紐過除縣置7叫2,;^;電容值之制時,均將脈波 後’计數裝置80則在N次的放雷期 的㈣输“ 人岐電期間累加每—次被除頻裝置70除過 的:號ckl,因此計數裝置8〇中所形成之累加值則可以達到平 均的效果’而制-個穩定的輸出數值。 再接著’請參考第4圖,係本發明之電容值量_步驟,圖中的 不制電容&之電位。如第4 _示…卿,餘值量測裝 置會先將樣裝置80做重置(咖),如程序·,織由控制裝置1〇 驅動進入充電程序’如程序2〇〇,此時開關幻〇n,而開關s2⑽, 故待測電容Cx會被充電至Vrl的電位,接著由控制裝置i()控制使充 電及放電裝置40進入放電程序’如程序3⑻,此時開關S2/S3 〇n,而 開關Si OFF ’故待測電容Cx開始透過w、把,往呢端放電,此時 脈波產生裝置60也會將脈波訊號ek開始送人除頻裝置,而計數裝置 8〇亦會開始計數’如程序400。在此放電的過程中,制電容&之電 位的絕對值會不斷降低,當其下降到小於Vr2時,則比較裝置5〇會在 輸出狀態改變後送出-個減將開關S3 〇FF,因此計數裂置⑽亦停止 计數,一直到放電程序結束。接下來,再由控制裝置1〇持續並重複進 行上述之充電及放電程序,如程序5〇〇,其中CNT用來統計在目前的 量測過程中,已經做過了幾次充電/放電,而\則代表一次量測過程中 所預計要運作的充電/放電之次數,因此每做完一次充電/放電程序,則 CNT的數值會加一,直到CNT的數值等於n為止。 〜在待測電容Cx進行放電程序的過程中計數裝置80則會不斷的 進行累加’第5圓所示即為待測電容&之電位Μ隨着充電及放電程 序不斷變化的_ ;第5 ®巾的COUNTING指的是關S3被啟動 (ON)的時間獅’ *此綱亦是經過除頻後的脈波訊號。以送進計 數裝置⑽梢的時間週期㈣顯地,COUNTING從-進入放電程 序時就開始進行,直到丨Vex丨小於丨Vf2丨時’比較裝置%會變號,此時將 開關S3 〇FF ’而計數裝置80之COUNTING也會停止。 在實際的量測中,當待測電容Cx之電容值越大,則由Vrl放電到The Cx's electric command value 'finally displays this accumulated value in the display. Obviously, the capacitor of the present invention is used to adjust the accumulation of the counting device 8〇. ♦ If a frequency-dividing device signal is used, the signal is removed from the county, and the battery is set to 2,; The post-counting device 80 accumulates the number ckl that has been removed every time the frequency-dividing device 70 is removed during the (fourth) input of the demining period of the N times, so the accumulated value formed in the counting device 8〇 The average effect can be achieved and a stable output value can be obtained. Then, please refer to Fig. 4, which is the capacitance value of the present invention _ step, the potential of the capacitor and the voltage in the figure. ...Qing, the residual value measuring device will first reset the sample device 80, such as the program, and the weaving device will drive the charging device into the charging program, such as the program 2〇〇, at this time, the switch is illusory n, and Switch s2 (10), so the capacitance Cx to be tested will be charged to the potential of Vrl, and then controlled by the control device i () to cause the charging and discharging device 40 to enter the discharge program 'as in program 3 (8), at this time switch S2 / S3 〇 n, and switch Si OFF 'The capacitor Cx to be tested starts to pass through w, and discharges to the terminal. At this time, the pulse wave generating device 60 will also The pulse signal ek starts to be sent to the frequency dividing device, and the counting device 8〇 will also start counting 'as in the program 400. During the discharging process, the absolute value of the capacitance of the capacitor & will continue to decrease, when it falls to When it is less than Vr2, the comparison device 5〇 sends out a minus switch S3 〇FF after the output state is changed, so the counting split (10) also stops counting until the end of the discharging process. Next, the control device 1 Continue and repeat the above charging and discharging procedures, such as the procedure 5〇〇, where CNT is used to count the number of charging/discharging in the current measurement process, and \ represents the process of one measurement. The number of charge/discharge cycles expected to be operated, so each time the charge/discharge process is completed, the value of CNT is incremented by one until the value of CNT is equal to n. ~ Counting device during discharge process of capacitor Cx to be tested 80 will continue to accumulate 'The fifth circle is the potential of the capacitor to be tested Μ with the charging and discharging procedures _; _ _ 5th towel COUNTING refers to the S3 is activated (ON) Time of the lion' * The outline is also the pulse wave signal after frequency division. The time period (4) of the feed device (10) is sent to the ground, and the COUNTING is started from the time of entering the discharge program until the 丨Vex丨 is less than 丨Vf2丨. Will change the number, at this time the switch S3 〇 FF ' and the COUNTING of the counting device 80 will also stop. In the actual measurement, when the capacitance of the capacitor Cx to be measured is larger, it is discharged by Vrl

Vr2所需的時間將越長。以下說明電容健放電時間的祕。由電容的 充/放電對時間的公式: V(t)= Vi + (Vf - Vi) * (1 - e^) t== RC * Ln(Vf - Vi / V(t). yf) --------⑴ 上式中的Vi為電容電位的初始值,vf為電容電位的終值,t則為 電容電位由Vi充/放電至v⑴所經過之時間。對本發明的放電期間而 言,待測電容的電位是由Vrl往Vr3放電,因此,在⑴式中,Vi為vh, Vf為Vr3,R為(R1+R2) ’若Cx從Vrl放電到Vr2所需的時間為τ, 此時的V(T)為vr2,將以上代入(1)式,則τ可由下式表示: T= (R1+R2) * Cx * Ln[(Vr3-Vrl) / (Vr2-Vr3)] ---------(2) 在(2)式中,Vrl、Vr2、Vr3 皆為固定值,因此 Ln[(Vr3-VrlXVr2_Vi3” 為一個固定常數,另外,R2亦為一固定值,而R1除了在校正時需要 微調,否則其亦為一定值,因此可令(R1+R2)* Ln[(Vr3-Vrl)/(Vr2_Vr3^ 為常數K,則(2)式可進一步簡化表示為: 11 (3) T= K * Cx ------------- 則The longer it takes for Vr2. The following explains the secret of the capacitor's hard discharge time. The formula for the charge/discharge of the capacitor versus time: V(t)= Vi + (Vf - Vi) * (1 - e^) t== RC * Ln(Vf - Vi / V(t). yf) -- ------(1) In the above formula, Vi is the initial value of the capacitor potential, vf is the final value of the capacitor potential, and t is the time elapsed since the capacitor potential is charged/discharged to v(1). For the discharge period of the present invention, the potential of the capacitor to be tested is discharged from Vrl to Vr3. Therefore, in the formula (1), Vi is vh, Vf is Vr3, and R is (R1+R2) 'If Cx is discharged from Vrl to Vr2 The required time is τ, where V(T) is vr2, and the above is substituted into (1), then τ can be expressed by the following equation: T = (R1+R2) * Cx * Ln[(Vr3-Vrl) / (Vr2-Vr3)] ---------(2) In the formula (2), Vrl, Vr2, and Vr3 are all fixed values, so Ln[(Vr3-VrlXVr2_Vi3" is a fixed constant, in addition, R2 is also a fixed value, and R1 needs to be fine-tuned except for correction. Otherwise, it is also a certain value, so (R1+R2)* Ln[(Vr3-Vrl)/(Vr2_Vr3^ is a constant K, then (2) The formula can be further simplified as: 11 (3) T = K * Cx -------------

Cx= T/K (Farad)-------- (4) 由⑶式可知’放電時間T與待測電容c 係,此線性關係可以由第6 成正比,且為-線性關 值不同的電容:C1與C2, #其八^明°第6圖係顯示的為兩個電容 位由爾化義所經過===請的電位放電時,其電 、b1刀別為T1與T2,則T1與T2的比 值會雜C1與C2之電容值的比值,即C1/C2 = T1/T2。 另卜在(4)式中的單位為Farad,當本發明的電容量測裝置要對— 個電容值細為nF或pF撕量畤例μ必_,綱式可表為: (5)Cx= T/K (Farad)-------- (4) From equation (3), the 'discharge time T is related to the capacitance to be measured c. This linear relationship can be proportional to the sixth, and is a linear threshold. Different capacitors: C1 and C2, #其八^明° Figure 6 shows that the two capacitors are discharged by the potential of === please, the electric and b1 are T1 and T2. Then, the ratio of T1 to T2 will be the ratio of the capacitance values of C1 and C2, that is, C1/C2 = T1/T2. In addition, the unit in the formula (4) is Farad. When the capacitance measuring device of the present invention is required to have a capacitance value of nF or pF, the numerical value can be _, and the outline can be expressed as: (5)

Cx=(T/K)* 109(nF) 另外,若除頻裝置70所除的數值為M時,則在放電時間τ的時 間内,計數裝置80所數到的數值為:T*fck/M,而由於計數裝置8〇會 累加N次,則其累加的總值為·· N*T*fck/M。由(5)式可知,在電路的 製作上’便是要取一個適當的K值,使得以下關係成立:Cx=(T/K)* 109(nF) Further, if the value divided by the frequency dividing device 70 is M, the value counted by the counting device 80 during the discharge time τ is: T*fck/ M, and since the counting device 8 累 is accumulated N times, the total value of the accumulation is ···******* It can be seen from equation (5) that in the fabrication of the circuit, an appropriate K value is taken to make the following relationship true:

Cx= (T/K)* 109 = N*T*fck/M ----------------------- ⑹ 則 K=(N/M)* 109/fck=(Rl+R2)*Ln[(Vr3-Vrl)/(Vr2-Vr3)]-一⑺ 12 1323347 欲使⑺式成立,可透過選取適當的幻、w、呢、州來達成, 而R2、W、Vr2、Vr3本身的誤差及比較器之造成的誤差皆可透 過膽可變電阻R1來校正’也就是說,本發明之實補可針對參考電 壓產生裝置〇充放電裝置40及比較裝置50所可能產生之誤差提供 -雛之功能。由⑹式中,校正的方式可藉由校正裝置__嫩(未 • 顯示於圖中)送出一已知電容值,藉由調整可變電阻IU,來調整電容 放電時間T的大小,因此計數裝置80之數值亦會改變最後調整到計 練置8G之數值與已知電容值—致即可完成調校。很明顯地,此一調 φ 整過程的改變量可透過顯示裝置90來觀察。 此外,在本發明的另外一個實施例中,也可以將除頻裝置7〇與計 數裝置80的連接關係相互對調,如第7圖所示,也就是說,當進入放 電週期的同時,計數裝置80會先開始累計脈波產生裝置6〇所送出的 脈波訊號ck的次數,當經過N次週期的累計後,再由一除法裝置75 以設定值Μ來除計數裝f80所累計的數值,如此所得到的結果也可以 近似取得一個平均值的電容值《對這兩種實施方式,均為本發明之實 施態樣,而本發明對此並未加以限制。 φ 接著,將進一步揭露將本發明之電容量測裝置與一個具有自動判 斷待測物種類之萬用電表結合使用之實施方式,其中具有自動判斷待 測物種類之量測裝置已於另一說明書中提出專利申請中。因此,在本 發明的實施例中,僅將萬用電表操作過程中與電容量測相關的部份敘 述0 第8圖係一種具有自動判斷待測物種類之萬用電表的功能方塊 圖’包括控制單元(CONTROLLER) 110、切換單元(SWITCH) 120、 偵測早元(TYPE DETECTOR ) 130、類比/數位轉換電路(A/f) CONVERTER) 140、資料處理電路(DATAPROCESSING CIRCUIT) 13 1323347 15〇、顯示裝置(DISpLAY) 16〇、短路偵測單元(SH0RT DETECT〇R)、 170、蜂鳴器(BUZZER) 180及檔位控制電路(RANGE control CIRCUIT) 190等等所組成。 如第8圖所示,本實施例中的自動判斷待測物種類之萬用電表係 由一個控制單元no來使萬用電表先進行一個偵測模式(detectm〇de) 並依序提供複數個掃瞄訊息;然後將此複數個掃瞄訊息傳送至切換單 元120,而切換單元12〇則會依據控制單元110所提供之複數個掃瞄訊 息依序執行切換動作,用以依序將複數個測試電路與輸入端連接;例 如當控制單元110提供一個二極體之掃瞄訊號時,其會先提供一個二極 體之正偏壓掃瞄訊號(P—DI〇_CHK),接著,則再提供一個二極體之負 偏壓掃瞄訊號(n_dio_chk)。 當切換單元120接收到控制單元110所傳送之p_di〇_chk訊號 時,切換單元120會執行一個切換動作,以使輸入端與第9圖中的電 路組態連接。此時,電路組態中的端點T2被接至正偏壓VDD,例如: VDD-3V,而端點T3則被接至接地點(gnd),同時端點T2還可與偵 測單元m中的比較器(未顯示於圖中)連接,用以摘測輸入端之電 位,其中R1為一個大電阻,rptc為一個分塵電阻,並且Rl>>RpTC, 在一較佳實施例中,心兀可是一熱敏電阻,可以用來保護電路。此時, 若輸入端連接一個順向(forward e〇nnecti〇n)之二極體時,如第如圖 所不,端點T2之電位(即VT2)將被箝制(damping)在二極體的導 通電位’例如:VT2=0.7V »此時電位將是落在,,0V,,與,,+Vr”的 範圍之内’其中+Vr為-個小於yj^D之電位。此時,若輸人端之二極 體被接成反向(reverse eGnneetiGii)時,如第9b圖所示,由於二極體 不會被導通,此時的VT2電位為RpT々R1分壓後的結果,因此當分 壓電阻被财成Rl»RPTe時,貞彳VT2之t位將接近於正偏壓VDD。 14Cx= (T/K)* 109 = N*T*fck/M ----------------------- (6) Then K=(N/M)* 109/fck=(Rl+R2)*Ln[(Vr3-Vrl)/(Vr2-Vr3)]-一(7) 12 1323347 To make (7) hold, it can be achieved by selecting the appropriate illusion, w, 、, state. The error of R2, W, Vr2, Vr3 itself and the error caused by the comparator can be corrected by the varistor R1. That is, the actual compensation of the present invention can be applied to the reference voltage generating device 〇 charge and discharge device 40 and The error that may be generated by the comparison device 50 provides the function of the chick. In the formula (6), the correction method can send a known capacitance value by the correction device __ (not shown in the figure), and adjust the variable discharge resistance IU to adjust the size of the capacitor discharge time T, thus counting The value of device 80 will also be changed to the final adjustment to the value of 8G and the known capacitance value - the calibration can be completed. Obviously, the amount of change in this tuning φ process can be observed through the display device 90. In addition, in another embodiment of the present invention, the connection relationship between the frequency dividing device 7A and the counting device 80 may be mutually adjusted, as shown in FIG. 7, that is, while entering the discharging cycle, the counting device 80 will first start the cumulative pulse wave generating device 6 〇 the number of pulse signal ck sent, after the accumulation of N cycles, and then a dividing device 75 to set the value accumulated by the counting device f80. The results obtained in this way can also approximate the capacitance value of an average value. For both embodiments, the embodiments of the present invention are not limited thereto. φ Next, an embodiment in which the capacitance measuring device of the present invention is used in combination with a universal meter having an automatic judgment type of the object to be tested is further disclosed, wherein the measuring device having the type of automatically determining the object to be tested is already in another The patent application is filed in the specification. Therefore, in the embodiment of the present invention, only the part related to the capacitance measurement during the operation of the multimeter is described. FIG. 8 is a functional block diagram of a multimeter having an automatic judgment of the type of the object to be tested. 'Includes control unit (CONTROLLER) 110, switching unit (SWITCH) 120, TYPE DETECTOR 130, analog/digital conversion circuit (A/f) CONVERTER 140, data processing circuit (DATAPROCESSING CIRCUIT) 13 1323347 15 〇, display device (DISpLAY) 16〇, short-circuit detection unit (SH0RT DETECT〇R), 170, buzzer (BUZZER) 180 and gear control circuit (RANGE control CIRCUIT) 190 and so on. As shown in FIG. 8, the universal meter for automatically determining the type of the object to be tested in the embodiment is controlled by a control unit no to first perform a detection mode (detectm〇de) and sequentially provide the same. The plurality of scan messages are sent to the switching unit 120, and the switching unit 12 依 sequentially performs the switching action according to the plurality of scan messages provided by the control unit 110, in order to sequentially A plurality of test circuits are connected to the input terminal; for example, when the control unit 110 provides a diode scan signal, it first provides a diode positive bias scan signal (P-DI〇_CHK), and then Then, a negative bias scan signal (n_dio_chk) of the diode is provided. When the switching unit 120 receives the p_di〇_chk signal transmitted by the control unit 110, the switching unit 120 performs a switching action to connect the input terminal to the circuit configuration in FIG. At this point, the terminal T2 in the circuit configuration is connected to the positive bias VDD, for example: VDD-3V, and the terminal T3 is connected to the ground point (gnd), and the terminal T2 can also be connected to the detecting unit m. The comparator (not shown) is connected to extract the potential of the input terminal, wherein R1 is a large resistance, rptc is a dust separation resistor, and R1>>RpTC, in a preferred embodiment The heart is a thermistor that can be used to protect the circuit. At this time, if the input terminal is connected to a forward (forward e〇nnecti〇n) diode, as shown in the figure, the potential of the terminal T2 (ie VT2) will be clamped in the diode. The conduction potential 'for example: VT2 = 0.7V » At this time, the potential will fall within the range of, 0V,, and, +Vr" where +Vr is - a potential less than yj^D. At this time, If the diode of the input terminal is connected to the reverse (reverse eGnneetiGii), as shown in Figure 9b, since the diode is not turned on, the VT2 potential at this time is the result of the partial pressure of RpT々R1. Therefore, when the voltage dividing resistor is made into Rl»RPTe, the t bit of 贞彳VT2 will be close to the positive bias VDD.

Claims (1)

0·種電容值量測之方法,包括: 待測序’係由一第一參考電壓經過一充電及放電裝置對一 位執行-玫電程序,係於該充電程序將待測電容充電至待測電容之電 卜隨即經由該充電及放電裝置進行該放電程序,且該放 ,測電容之電位的絕對值會隨著放電時間持續降低; h ^行―計數程序,係於該放電程相始時,由—計練置進行計數; 容之電 較程序,係經由一比較裝置將一第二參考電壓與該待測電 之電位進行比較並進行一判斷;當 ,第二參考電壓大於該制電容之電㈣,制續進行該計數程 序, 該第二參考電壓小於該制電容之電位時,則停止計數程序;及 ㈣充電及放電之累計程序,係將前述執行之該充電程序及該放 進&lt;7累計’直龍累計值__設定次數Ν後停止,並顯示一 篁測值; 其中於該放電程序中提供一脈波訊號至一除頻襄置,並且該除頻裝 置將該脈波訊號除以-設定值Μ後,由一計數裝置執行該累計程序。 如申請專利朗第10項所述之電容值量測方法,其中進行該放電 程序前,可進-步先執行-計數裝置之重置(R£set)程序。 12. 如申請專利範圍第1G項所述之電容值量測方法,其中該充電程序、 該放電程序及該計數程序可經由一控制裝置來執行 13. 如申請專利範圍第1〇項所述之電容值量測方法,其中該第二參考 電壓可經由一分壓裝置產生。 M.如中請專利細第H)項所述之電容值量測方法,其可進—步提供一調 校程序。 15. —種具有自動判斷待測元件種類之量測裝置,包括· 25 一控制單元’係依序提供複數個掃瞄訊息; 一切換單元,係由複數個測試電路所組成,其一第一端與—和待測 元件連接之輸入端連接,其一第二端與該控制單元連接,並依據該複 數個掃瞄訊息依序執行切換動作,用以依序將該複數個測試電路與該 輸入端連接; 一偵測單元,其一第一端與該切換單元之一第三端連接,並藉由一 比較電路依序對該輸入端之電壓進行比較,並將比較之結果由一第二 端送回至該控制單元,以使該控制單元依據該比較結果來判斷待測元 件之種類;及 一量測單元,係與該控制單元連接並依據該控制單元之判斷結果選 擇一相應之量測電路對該待測元件進行量測,並將量測之結果顯示於 一顯示裝置;其特徵在於該量測單元包括一電容值量測電路,且該電 容值量測電路包括: 一電壓產生裝置,用以提供一第一參考電壓及一第二參考電壓; 一比較裝置,其一第一輸入端與該第二參考電壓連接;一充電及放 電裝置,其一端與該電壓產生裝置連接,而另一端則與該比較裝置之 一第二輸入端連接; 一脈波產生裝置’與該比較裝置之輸出端連接,並提供一脈波訊號; 一除頻裝置,與該脈波產生裝置連接,並將該脈波訊號除以一第一 設定值;及 一計數裝置,與該除頻裝置連接,並於該充電及放電裝置進行放電 期間進行計數; 其中該控制裝置可進一步控制該充電及放電裝置、該脈波產生裝置 及該除頻裝置,並提供該除頻裝置之該第一設定值;並且當該比較器 之該第一輸入端與該第二輸入端之電壓相同時,則關閉該脈波產生裝 置’並由該控制裝置再啟動該充電及放電裝置直到該充電及放電裝置 26 1323347 之啟動次數達到一第二設定值時,則由一顯示裝置顯示出該計數裝置 之累計值。 16_如申請專利範圍第15項所述之量測裝置’其進一步包括一短路偵 測單元,其第一端與該切換單元之第三端連接,而其第二端則連接至 該控制單元。 Π·如申請專利範圍IM6柄述之量測裝置,其中該短路摘測單元可 進一步與一封鳴裝置連接。 18. 如申請專利範圍第15項所述之量測裝置,其中該控制電路所提供 之複數個掃瞄訊息依序為二極體,其次為電容,再其次為電阻。 19. 如申請專利範圍第18項所述之量測裝置,其中該二極體之掃瞒訊 息可進一步分為一二極體為順向連接或是反向連接。 20. 如申請專利範圍第15項所述之量測裝置,其中該切換單元中的測 試電路包括一二極體正偏壓測試電路組態、一二極體負偏壓測試電路 組態、一電容之充電測試電路組態、一電容之放電測試電路組態以及 一開路測試電路組態。 21. 如申請專利範圍第15項所述之量測裝置,其中該控制單元係以一 查表(LOOK-UPTABLE)彳式將該比較結果與一設定之表格比對並據 以判斷待測元件之種類。 22. 如申請專利範圍第20項所述之量測裝置,其中該切換單元中的二 極體正偏壓測試電路組態包括: 一待測元件之輸入端; 一第一端點,經由一第二電阻與該待測元件之輸入端連接; —第二端點,經由一偏壓電阻與該待測元件之輸入端連接;及 一第二端點,經由一第一電阻與該待測元件之輸入端連接; 其中該第-端點為懸空’該第二端點與_正麟及該侧元件中的比 較器連接,而該第三端點與接地點連接。 27 1323347 23.如申請專利範圍第20項所述之量測裝置,其中該切換單元中的二 極體負偏壓測試電路組態包括: 一待測元件之輸入端; 一第一端點’經由一第二電阻與該待測元件之輸入端連接; 一第二端點,經由一偏壓電阻與該待測元件之輸入端連接;及 一第三端點,經由一第一電阻與該待測元件之輸入端連接; 其中該第一端點為懸空,該第二端點與一負偏壓及該偵測元件中的比 較器連接’而該第三端點與接地點連接。0. A method for measuring a capacitance value, comprising: to be sequenced by a first reference voltage through a charging and discharging device to perform a one-single-electricity program, in which the charging program charges the capacitance to be tested The measuring capacitor is then subjected to the discharging process via the charging and discharging device, and the absolute value of the potential of the measuring capacitor is continuously decreased with the discharging time; h ^ line - counting program is started at the beginning of the discharging process When the power is compared with the program, the second reference voltage is compared with the potential of the power to be tested through a comparison device and a determination is made; when the second reference voltage is greater than the system The electric power of the capacitor (4) is continuously performed by the counting program. When the second reference voltage is less than the potential of the capacitor, the counting procedure is stopped; and (4) the accumulating procedure of charging and discharging is to perform the charging procedure and the discharging After entering the <7 cumulative 'straight dragon cumulative value __ set number of times, then stop, and display a measured value; wherein a pulse signal is provided to the frequency dividing device in the discharging program, and the frequency dividing device is installed The pulse signal by dividing - the set value of [mu], execution of the program by a cumulative counting means. For example, the capacitance value measuring method described in claim 10, wherein the resetting (R£set) procedure of the counting device can be performed first before the discharging process. 12. The method of measuring a capacitance value according to claim 1G, wherein the charging procedure, the discharging procedure, and the counting procedure are performed by a control device. 13. As described in claim 1 The capacitance value measuring method, wherein the second reference voltage is generated by a voltage dividing device. M. The capacitance value measurement method described in the patent detail item H) can further provide a calibration procedure. 15. A measuring device having an automatic determining device type to be tested, comprising: 25 a control unit to sequentially provide a plurality of scanning messages; a switching unit consisting of a plurality of test circuits, a first The terminal is connected to the input end connected to the component to be tested, and the second end is connected to the control unit, and the switching action is sequentially performed according to the plurality of scan messages, and the plurality of test circuits are sequentially connected thereto. The input terminal is connected; a detecting unit, a first end thereof is connected to the third end of the switching unit, and the voltage of the input terminal is sequentially compared by a comparison circuit, and the result of the comparison is determined by a first The two ends are sent back to the control unit, so that the control unit determines the type of the component to be tested according to the comparison result; and a measuring unit is connected with the control unit and selects a corresponding one according to the judgment result of the control unit. The measuring circuit measures the component to be tested, and displays the result of the measurement on a display device; wherein the measuring unit comprises a capacitance value measuring circuit, and the capacitance value The measuring circuit comprises: a voltage generating device for providing a first reference voltage and a second reference voltage; a comparing device, a first input end is connected to the second reference voltage; and a charging and discharging device is at one end Connected to the voltage generating device, and the other end is connected to a second input end of the comparing device; a pulse wave generating device 'connects with the output end of the comparing device and provides a pulse wave signal; Connecting to the pulse wave generating device, and dividing the pulse wave signal by a first set value; and a counting device connected to the frequency dividing device and counting during discharging of the charging and discharging device; wherein the controlling The device may further control the charging and discharging device, the pulse wave generating device and the frequency dividing device, and provide the first setting value of the frequency dividing device; and when the first input end and the second input of the comparator When the voltage of the terminal is the same, the pulse wave generating device is turned off and the charging and discharging device is restarted by the control device until the charging and discharging device 26 1323347 When the number reaches a second movable set value, by a display device showing the cumulative value of the counting means. The measuring device of claim 15 further comprising a short circuit detecting unit, the first end of which is connected to the third end of the switching unit, and the second end of which is connected to the control unit . Π·As claimed in the patent application scope of the IM6 handle measuring device, wherein the short circuit extraction unit can be further connected to a single sounding device. 18. The measuring device of claim 15, wherein the plurality of scanning messages provided by the control circuit are in the order of a diode, followed by a capacitor, and then a resistor. 19. The measuring device of claim 18, wherein the broom information of the diode is further divided into a diode for a forward connection or a reverse connection. 20. The measuring device according to claim 15, wherein the test circuit in the switching unit comprises a diode positive bias test circuit configuration, a diode negative bias test circuit configuration, and a Capacitor charging test circuit configuration, a capacitor discharge test circuit configuration and an open circuit test circuit configuration. 21. The measuring device according to claim 15, wherein the control unit compares the comparison result with a set table by a look-up table (LOOK-UPTABLE) and judges the device to be tested The type. 22. The measuring device of claim 20, wherein the diode positive bias test circuit configuration in the switching unit comprises: an input end of the device to be tested; a first end point, via a a second resistor is connected to the input end of the device to be tested; a second terminal is connected to the input end of the device to be tested via a bias resistor; and a second terminal is connected to the second resistor via the first resistor The input end of the component is connected; wherein the first end point is floating. The second end point is connected to the comparator in the side element and the third end point is connected to the ground point. The measuring device of claim 20, wherein the diode negative bias test circuit configuration in the switching unit comprises: an input end of the device to be tested; a first end point Connected to the input end of the device to be tested via a second resistor; a second terminal connected to the input end of the device to be tested via a bias resistor; and a third terminal via the first resistor The input end of the device to be tested is connected; wherein the first end point is suspended, the second end point is connected to a negative bias voltage and a comparator in the detecting element, and the third end point is connected to the ground point. 24.如申請專利範圍第20項所述之量測裝置,其中該切換單元中的電 容充電測試電路組態包括: 一待測元件之輸入端; 一第一端點,經由一第二電阻與該待測元件之輸入端連接; 一第二端點,經由一偏壓電阻與該待測元件之輸入端連接丨及 一第三端點’經由-第-電阻與該待測猶之輸人端連接; 偏 其中該第-端點與該摘測元件中的比較器連接,該第二端點與一負 壓連接,而該第三端點為懸空。 、、24. The measuring device of claim 20, wherein the capacitive charging test circuit configuration in the switching unit comprises: an input end of the device to be tested; a first end point, via a second resistor The input end of the device to be tested is connected; a second terminal is connected to the input end of the device to be tested via a bias resistor, and a third terminal 'passes the first-resistance and the input to be tested The terminal is connected to a comparator in the device to be tested, the second terminal is connected to a negative pressure, and the third terminal is suspended. , =·如申請專利範圍第20項所述之量測裝置,其中該切換單元中的電 容放電測試電路組態包括: —待測元件之輸入端; :第-端點’經由-第二電阻與該待測元件之輸入端連接 1二端點’經由-爐電阻與該待測元件之輸人端連接;及 :第三端點’經由-第-餘_待測元件之輸人端連接; =該第-義與躺點連接,料二咖_侧元件巾的比較器 連接’而該第三端點為懸空。 =,如申請專利範圍第20項所述之量測裝置,其中該切 路測試電路組態包括: T 28 一待測元件之輸入端; 一第一端點,經由一第二電阻與該待測元件之輸入端連接; —第二端點,經由一偏壓電阻與該待測元件之輸入端連接;及 一第二端點,經由一第一電阻與該待測元件之輸入端連接; 其中該第-端點與該偵測元件中的比較器連接,該第二端點為懸空, 而該第三端點與一參考電壓連接。 •工 27·如申請專利範圍帛23項所述之量測装置,其中該設定之表格為— 内建之邏輯表。 Μ 28. 如申請專利範圍帛15項所述之量測裝置,當判斷該輸入端為開路 時,即繼續執行該掃瞄程序,而不執行該量測程序。 29. -種萬用電表,設有一顯示裝置,用以顯示複數個量測模式及量測 之數值,一切換開關裝置,用以提供複數個切換選擇模式,以進行特 定信號之制’以及—對輸人軒,其特徵在於該複數個量測模式至 少包括一電容值量測裝置,且該電容值量測裝置包括: 一參考電Μ產生裝置,用已提供__第—參考電壓及—第二參考電 壓; 一比較裝置,其一第一輸入端與該第二參考電壓連接; -充電及放電裝置,其-端與該電壓產生裝置連接,而另一端則與 該比較裝置之一第二輸入端連接; -脈波產生裝置’與該比較裝置之輸出端連接,並提供—脈波訊號; 除頻裝置,與該脈波產生裝置連接,並將該脈波訊號除以一第一 設定值(Μ); 一汁數裝置,與該除頻裝置連接,並於該充電及放電裝置進行放電 期間進行計數;及 一控制裝置,用以控制該充電及放電裝置、該脈波產生裝置及該除 頻裝置,並提供該除頻裝置之該第一設定值(Μ); 29 丄以W47 其中當該比較裝置之該第二輸人端之電壓小於該第—輸人端之電壓 時’則關閉該脈波產生裝置,並由該控制裝置再敌動該充電及放電裝 置直到該充電及放電裝置之啟動缝達到_第二設定值⑻時,則由 一顯示裝置顯示出該計數裝置之累計值。 30.如申請專利範圍第29項所述之萬用電表,其中該電容值量測裝置 中的充電及放電裝置係藉由H關裝置及―第二開關裝置來控制 充電及放電,且該第-開關裝置及該第二開關裝置由該控制裝置控制。 M.如申請專利範圍帛29項所述之萬用電表,其中該電容值量測裝置 中的該充電及放電裝置中之放電電路至少包括一可變電阻。 32.如申請專利範圍f Μ項所述之萬用電表,其中該可變電阻可作為 電容值量測裝置之調校電阻。 33· —種電容值量測裝置,包括: 參考電壓產生裝置,用已提供一第一參考電壓及一第二參考電 壓; 一比較裝置,其一第一輸入端與該第二參考電壓連接; -充電及放電裝置’其-端與該電壓產生裝置連接,而另一端則與 該比較裝置之一第二輸入端連接; -脈波產生裝置’與該比較裝置之輸出端連接,並提供—脈波訊號; -計數裝置’與該脈波產生裝置連接,並_充電及放電裝置進行放電 期間進行該脈波訊號之計數; 一除法裝置,與該計數裝置連接,並將該計數裝置所計數之脈波訊 號除以一第一設定值(M);及 -控制裝S,用以控制該《電及放電裝置、該脈波產生裝置及該除 頻裝置,並提供該除頻裝置之該第一設定值(M); 其中當該比較裝置之該第二輸入端之電壓小於該第一輸入端之電 壓時’則關閉該脈波產生裝置,並由該控制裝置再啟動該充電及放電裝 30 1323347 置直到該充電及放電裝置之啟動次數達到一第二設定值(N)時,則由 一顯示裝置顯示出該計數裝置之累計值。 34. 如申請專利範圍第33項所述之電容值量測裝置,其中該充電及放 電裝置係藉由一第一開關裝置及一第二開關裝置來控制充電及放電,且 該第一開關裝置及該第二開關裝置由該控制裝置控制。 35. 如申請專利範圍第33項所述之電容值量測裝置,其中該充電及放 電裝置中的放電電路至少包括一可變電阻。 •如申請專利範圍第35項所述之電容值量測裝置,其中該可變電阻 可作為電容值量測裝置之調校電阻。The measuring device of claim 20, wherein the capacitor discharge test circuit configuration in the switching unit comprises: - an input end of the component to be tested; : a - end point 'via - a second resistor The input end of the device to be tested is connected to the two terminals 'connected to the input end of the device to be tested via a furnace resistance; and: the third end point is connected via the input end of the -first-to-be-test element; = The first meaning is connected to the lying point, and the comparator is connected to the side of the two side wipers and the third end point is suspended. The measurement device of claim 20, wherein the cut test circuit configuration comprises: T 28 an input end of the device to be tested; a first end point, via the second resistor The input end of the measuring component is connected; the second end is connected to the input end of the device to be tested via a bias resistor; and a second end is connected to the input end of the device to be tested via a first resistor; The first end point is connected to a comparator in the detecting component, the second end point is suspended, and the third end point is connected to a reference voltage. • Work 27 • The measuring device described in claim 23, wherein the table of settings is – a built-in logic table. Μ 28. If the measuring device described in claim 15 is open, when the input is judged to be open, the scanning process is continued without performing the measuring procedure. 29. A universal meter having a display device for displaying a plurality of measurement modes and measuring values, and a switching device for providing a plurality of switching selection modes for performing a specific signal system' - for the input switch, characterized in that the plurality of measurement modes include at least one capacitance value measuring device, and the capacitance value measuring device comprises: a reference power generating device, which has provided the __first reference voltage and a second reference voltage; a comparison device having a first input connected to the second reference voltage; - a charging and discharging device having a terminal connected to the voltage generating device and the other end being associated with the comparing device The second input terminal is connected; the pulse wave generating device is connected to the output end of the comparing device and provides a pulse signal; the frequency dividing device is connected to the pulse wave generating device, and the pulse signal is divided by a first a set value (Μ); a juice number device connected to the frequency dividing device and counting during discharge of the charging and discharging device; and a control device for controlling the charging and discharging device The pulse wave generating device and the frequency dividing device, and providing the first set value (Μ) of the frequency dividing device; 29 丄 to W47, wherein when the voltage of the second input terminal of the comparing device is less than the first When the voltage of the terminal is input, the pulse wave generating device is turned off, and the charging device and the charging device are again hosted until the starting slot of the charging and discharging device reaches the second set value (8), and then a display is performed. The device displays the cumulative value of the counting device. 30. The universal meter of claim 29, wherein the charging and discharging device in the capacitance measuring device controls charging and discharging by using an H-off device and a second switching device, and The first switching device and the second switching device are controlled by the control device. M. The universal meter of claim 29, wherein the discharge circuit of the charging and discharging device in the capacitance measuring device comprises at least one variable resistor. 32. The universal meter as claimed in claim 5, wherein the variable resistor is used as a calibration resistor of the capacitance value measuring device. 33. A capacitance value measuring device, comprising: a reference voltage generating device, wherein a first reference voltage and a second reference voltage are provided; and a comparing device, a first input end of which is connected to the second reference voltage; a charging and discharging device having its end connected to the voltage generating device and the other end connected to a second input of the comparing device; - a pulse generating device 'connecting to the output of the comparing device and providing - a pulse signal; a counting device is connected to the pulse wave generating device, and the charging and discharging device performs counting of the pulse wave signal during discharge; a dividing device is connected to the counting device, and the counting device counts The pulse signal is divided by a first set value (M); and - a control device S for controlling the "electric and discharge device, the pulse wave generating device and the frequency dividing device, and providing the frequency dividing device a first set value (M); wherein when the voltage of the second input terminal of the comparing device is less than the voltage of the first input terminal, the pulse wave generating device is turned off, and the charging device is restarted by the control device And the discharge device 30 1323347 is set until the number of starts of the charging and discharging device reaches a second set value (N), and the integrated value of the counting device is displayed by a display device. 34. The capacitance value measuring device according to claim 33, wherein the charging and discharging device controls charging and discharging by a first switching device and a second switching device, and the first switching device And the second switching device is controlled by the control device. 35. The capacitance value measuring device of claim 33, wherein the discharge circuit in the charging and discharging device comprises at least one variable resistor. The capacitance value measuring device according to claim 35, wherein the variable resistor is used as a calibration resistor of the capacitance value measuring device.
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