TWI322559B - Power circuit - Google Patents
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- TWI322559B TWI322559B TW95127923A TW95127923A TWI322559B TW I322559 B TWI322559 B TW I322559B TW 95127923 A TW95127923 A TW 95127923A TW 95127923 A TW95127923 A TW 95127923A TW I322559 B TWI322559 B TW I322559B
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1322559 弄月 95, 九、發明說明: 【發明所屬之技術領域】 本發明係有關於n雜換ϋ,制是指—種電轉漏之電源電 路。 【先前技術】 。凊參閱第-圖’其為習用電源供應||之電路圖。如圖所示,電源供應 器用於將-線電壓(line voltage) VAC轉換為—調整電壓Vz。一整流電路 1〇 ’其耗接於線電壓vAe並整流以產生—輸人電壓Vin。—電容u,其輕 • 接於紐祕1G而魏該輸人賴%並_-餘I5,以產生調整電壓 vz。-稽納二極體16 ’其耦接於電容15與接地端以用於調整。一電阻12, 其用於對電容η放電。此種型式之電賴絲已被廣泛顧於家庭裝置, 例如。加啡機、冷卻風扇以及遙控m細,此郷式之電驗應器具有 南功率損耗之缺點’特別是在輕負载與無負載狀態下吐述之電阻12與稽 納二極體16會產生顯著之電源祕,所以為了節省電源係必須降低功率損 因此 ,本發•針對上述_而提供—種高鱗之電職應器,以在 輕負載與無負載狀態下可降低電源損耗,以有效解決上述問題。 • 【發明内容】 本發敗主要目的,在於提供_種鶴電路,其可降低轉損耗 嗜電源,進而提高效率。 :壯本發明之電源電路,其包含有一輸入電晶體,輸入電晶體為-負臨界 •=並接收-電壓源;-第-電晶體,其串聯於輸人電晶體以提供_;供應 壓至電源電路之輸出端;-輸人制電路,其減於龍源 ==壓準位產生-控制訊號;一第二電晶體,餘接於輸 = 依據控制訊贼止輸人電晶雜第―電晶體;_輸出伽,m路, 供應電壓並鎌做《之電群域生m錢與致能訊 ⑴25591322559 弄月95, IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to n-type switching, and refers to a power supply circuit for electric leakage. [Prior Art].凊 Refer to Figure _, which is a circuit diagram of the conventional power supply ||. As shown, the power supply is used to convert the line voltage VAC to the adjustment voltage Vz. A rectifier circuit 1 〇 ' is consuming the line voltage vAe and rectifying to generate - the input voltage Vin. - Capacitor u, which is light • Connected to the secret 1G and Wei should lose the % and _- remaining I5 to generate the adjustment voltage vz. The -gener diode 16' is coupled to the capacitor 15 and ground for adjustment. A resistor 12 for discharging the capacitance η. This type of electric wire has been widely considered for home devices, for example. With the addition of a compositing machine, a cooling fan and a remote control, the electric detector of this type has the disadvantage of the south power loss, especially in the light load and no load state, the resistor 12 and the genus diode 16 are generated. Significant power supply secret, so in order to save power, it is necessary to reduce power loss. Therefore, this is a high-grade electric service for the above-mentioned _ to reduce power loss under light load and no load conditions, so as to effectively Solve the above problem. • [Invention] The main purpose of this failure is to provide a _ type of crane circuit that can reduce the loss of power and increase the efficiency. The power circuit of the invention comprises an input transistor, the input transistor is a -negative criticality == and a receiving-voltage source; - a first transistor, which is connected in series to the input transistor to provide _; The output of the power circuit; - the input circuit, which is reduced by the Longyuan == pressure level generation - control signal; a second transistor, the remainder is connected to the transmission = according to the control signal thief to lose the power of the crystal - Transistor; _ output gamma, m-channel, supply voltage and do the "electric group domain m money and enable information (1) 2559
號;一阻抗裝置,其耦接於輸入電晶體與第一電晶體,以提供偏壓而導通 輪入電晶體與第一電晶體。第一致能訊號在供應電壓之電壓準位高於一高 輸出電壓準位時鍰止輸入電晶體與第一電晶體;第二致能訊號用於在供應 電壓之電壓準位低於一低輸出電壓準位時截止電源電路之輸出。 兹為使貴審查委員對本發明之結構特徵及所達成之功效更有進一步 之瞭解與認識’謹佐以較佳之實施例圖及配合詳細之說明,說明如後。 【實施方式】 請參閱第二圖’其為本發明之電源供應器的電路圖。如圖所示,整流 電路10,其耦接於一供應電路2〇之一輸入端取並接收線電壓VAC ,以產 生輸入電壓V!N。輸入電壓ViN為一電壓源且經由整流電路10整流。供應 電路20將在一第一輸出端sw產生一供應電壓Vc,以及在一第二輸出端 out產生一輸出電壓Vc^供應電路20之一接地端GND耦接至接地。一 電容50,其耦接於第一輸出端sw。此外,更有一電容55耦接於第二輸出 端OUT以保持能量。供應電路2〇可為電源電路、電源供應電路、電源碉 整電路或為電源來源電路。 «月參閱第二圖,其為電源供應器之供應電路2〇之一較佳實施例的電路 圖。供應電路20包含有一輸入電晶體60。輸入電晶體6〇耦接於輸入端取 而接收輸入電壓Vin,以提供該供應電壓Vc至第一輸出端sw。輸入電晶 體60為一負臨界裝置,例如接面場效電晶體(JFET)。因此零偏壓將導通 輸入電晶體60,此外僅可藉由一負偏壓截止輸入電晶體6〇。 輸出谓測電路1GG ’其輕接於第—輸出端sw,用於偵測供應電壓 Vc,以依據供應電壓Vc之電壓準位而在輸出偵測電路1〇〇之一第一致能 端0V產生H能訊號SGV。-阻抗裝置7〇,其祕於輸人電晶體6〇, 以提供偏壓至輸人電晶體60,_導通輸人電晶體⑹。阻抗裝置7〇可為 電阻或為電晶n致能訊號、翻於在纖電壓Ve之電壓準位高於 -高輸出電壓準位時截止輸人電壓6G。—低瓣(LGwDiOp 〇ut,ld〇) 穩壓器3GG,其祕於帛二輸出端〇υχ並產生該輸出電壓%。此外,輸 1322559And an impedance device coupled to the input transistor and the first transistor to provide a bias voltage to conduct the transistor and the first transistor. The first uniform signal stops the input transistor and the first transistor when the voltage level of the supply voltage is higher than a high output voltage level; and the second enable signal is used to lower the voltage level of the supply voltage to a lower level The output of the power supply circuit is cut off when the output voltage level is output. Further understanding and understanding of the structural features and the efficacies of the present invention will be made by the reviewing committees, and the description of the preferred embodiments and the detailed description will be given below. [Embodiment] Please refer to the second figure, which is a circuit diagram of the power supply of the present invention. As shown, the rectifier circuit 10 is coupled to one of the input terminals of a supply circuit 2 to receive and receive the line voltage VAC to generate an input voltage V!N. The input voltage ViN is a voltage source and is rectified via the rectifier circuit 10. The supply circuit 20 generates a supply voltage Vc at a first output terminal sw, and generates an output voltage Vc at a second output terminal. The ground terminal GND of the supply circuit 20 is coupled to ground. A capacitor 50 is coupled to the first output end sw. In addition, a capacitor 55 is coupled to the second output terminal OUT to maintain energy. The supply circuit 2 can be a power supply circuit, a power supply circuit, a power supply regulation circuit, or a power source circuit. «Month Referring to the second figure, which is a circuit diagram of a preferred embodiment of a supply circuit 2 of a power supply. Supply circuit 20 includes an input transistor 60. The input transistor 6 is coupled to the input terminal to receive the input voltage Vin to provide the supply voltage Vc to the first output terminal sw. The input transistor 60 is a negative critical device such as a junction field effect transistor (JFET). Therefore, the zero bias voltage will turn on the input transistor 60, and the input transistor 6 can only be turned off by a negative bias. The output pre-measure circuit 1GG' is lightly connected to the first output terminal sw for detecting the supply voltage Vc to be at the first enable end of the output detection circuit 1 according to the voltage level of the supply voltage Vc. Generate H energy signal SGV. The impedance device 7 is secreted by the input transistor 6 〇 to provide a bias voltage to the input transistor 60, which turns on the input transistor (6). The impedance device 7〇 can be a resistor or an electron-induced n-signal, turning off the input voltage 6G when the voltage level of the fiber voltage Ve is higher than the high output voltage level. - Low-lobe (LGwDiOp 〇ut, ld〇) Regulator 3GG, which is secreted at the output of 帛2 and produces the output voltage %. In addition, lose 1322559
' 年月日修正替沒A 出偵測電路100更依據供應電壓乂(:之電壓準位,在輸出偵測電路1〇〇之一 第二致能端EN產生一第二致能訊號Sen。第二致能訊號Sen傳送至低壓降 穩壓器300 ’以在供應電壓vc之電壓準位低於一低輸出電壓準位時,截止 . 供應電路20之輸出電壓V〇。 . 請參閱第四圖,其為輸出偵測電路100之一較佳實施例的電路圖。如 圖所示’稽納二極體110、112係串聯。稽納二極體112更耦接於第一輸出 端sw,以偵測供應電壓V(^稽納二極體110另耦接於一電阻115,電阻 更耦接於一電晶體120。電阻115用於在供應電壓Vc之電壓準位高於 稽納二極體110以及112之電壓時導通電晶體12〇。一電晶體125,其並聯 • 於稽納二極體112。當電晶體120導通時,電晶體125·將短路稽納二極體 112 ’以達到遲滞(hysteresis)的目的,以用於偵測供應電壓Vc是否過高。 稽、’内一極體no以及112之電壓決定該高輸出電壓準位。稽納二極體η〗 之電壓則決定該遲滯目的之一遲滯準位。當供應電壓Vc之電壓準位低於遲 滯準位時,第一致能訊號s0v將導通輸入電晶體60。 一電晶體140,其耦接於電晶體12〇以及第一輸出端Sw。電晶體14〇 依據電晶體120之導通狀態而導通。一電阻116,其耦接於第一輸出端sw、 電晶體125 ' 140 ’進而提供一偏壓至電晶體125、140 〇 —電阻117,其耦 接於電晶體140,以用於在電晶體12〇導通時導通一電晶體129。電晶體 籲129更耦接於電晶體140。此外,電晶體129更耦接於輸入電晶體6〇,以 在供應電壓Vc之電壓準位高於該高輸出電壓準位時,產生第一致能訊號 Sov而截止輸入電晶體60。 : 一稽納一極體’其亦麵接於第一輸出端sw以摘測供應電壓vc β 一電阻155,其耦接於稽納二極體150以及一電晶體165,一旦供應電壓 • Vc之電壓準位高於該低輸出電壓準位時則導通電晶體165。稽納二極體15〇 之稽納電壓係決定該低輸出電壓準位。一電阻156,其耦接於第一輸出端 SW以及一電晶體Γ70。電晶體170更耦接於第一輸出端SW以及電晶體 165。電晶體170在供應電壓Vc之電壓準位低於低輸出電壓準位時產生第 二致能訊號SEN » 請參閱第五圖,其為供應電路20之另一较佳實施例的電路圖。如圖所 示,此實施例之一第一電晶體80係串聯於輸入電晶體60,以提供該供應 電壓Vc至第一輸出端SW。第一電晶體80為一正臨界裝置。阻抗裝置7〇 耦接於輸入電晶體60以及第一電晶體80以提供偏壓,進而導通輸入電晶 體60以及第一電晶體80。當供應電壓Vc之電壓準位高於高輸出電壓準位 時,第一致能訊號Sov截止輸入電晶體60以及第一電晶體80。第一電晶 體80係被用來對供應電路20提供保護。當供應電壓Vc被短路時,第一電 晶體80將截止以保護輸入電晶體60。 請參閱第六圖,其為本發明之電源供應器之另一較佳實施例的電路 圖。此實施例耦接於整流電路10之一供應電路30的導通與截止係同步於 線電壓VAC。此供應電路30可為電源電路、電源供應電路、電源調整電路 或電源來源電路。供應電路30僅能在輸入電壓Vjn低於一輸入臨界電壓時 被導通,如此可降低輸入電晶體60之切換損耗,以及增進供應電路3〇之. 效率。請參閱第七圖,其為輸入電壓Vrw之波形圖。當輸入電壓VlN低於一 臨界電壓VT時,輸入電壓Vm之電源可以傳送至第一輸出端sw。其中臨 界電壓VT係與輸入臨界電壓相關。供應電路30包括有一偵測端DET,其, 經由一分墨電路40而耦接輸入電壓γΙΝ。分壓電路4〇耦接於輸入電壓Vm 以及偵測端DET。分壓電路40包括有電阻41、42。電阻41、42係相互串 聯0 请參閱第八圖’其為第六圖電源供應器之供應電路3〇之一較佳實施例 的電路圖。如圖所示,供應電路3〇包含有輸入電晶體⑼,輸入電晶體沉 減於輸入端IN而接收輸入電屋Vm,以在第—輸出端sw提供該供應電 壓Vc。上述之輸入電壓\^為電麼源。一輸入债測電路乃,其一正輸入端 耗接於供應電路30之侧端DET’錄由分壓電路⑽侧輸人電壓^, 並且依據輸人賴之電鮮位產生—㈣峨。控制減在輸入電塵 ^之電壓準位高於臨界電壓Vt時截止輸入電晶體6〇。控制減係經由相 =輸入_電路75與歓f晶體綠&截止輸入電 輸入細1:路75包括有細界電壓%。料電壓%與輸入臨界 1322559 電壓相關。臨界賴vT祕於輸人細電路75之—貞輸人端^ 輪出偵測電路100,其輕接於第-輸出端SW以债測供應電壓Vc,進 而依據供應電壓vc之電壓準位而在第一致能端ov產生第—致能訊號 sov。此實施例之輸出偵測電路100之電路係可一第四圖之電路來實現。阻 抗裝置70耦接於輸入電晶體6〇,以提供偏壓,進而導通輸入電晶體幼。The year/month correction is performed by the detection circuit 100 to generate a second enable signal Sen according to the voltage level of the supply voltage : (the second enable terminal EN of the output detection circuit 1). The second enable signal Sen is sent to the low dropout regulator 300' to turn off the output voltage V of the supply circuit 20 when the voltage level of the supply voltage vc is lower than a low output voltage level. . The figure is a circuit diagram of a preferred embodiment of the output detection circuit 100. As shown in the figure, the 'signal diodes 110 and 112 are connected in series. The gate diode 112 is further coupled to the first output terminal sw. In order to detect the supply voltage V, the resistor 110 is further coupled to a resistor 115. The resistor is further coupled to a transistor 120. The resistor 115 is used for the voltage level of the supply voltage Vc to be higher than the second pole. The voltages of the bodies 110 and 112 are electrically connected to the transistor 12. A transistor 125 is connected in parallel to the diode 112. When the transistor 120 is turned on, the transistor 125 is short-circuited to the diode 112'. The purpose of hysteresis is reached to detect whether the supply voltage Vc is too high. The voltage of 112 determines the high output voltage level. The voltage of the inductor η〗 determines the hysteresis level of the hysteresis purpose. When the voltage level of the supply voltage Vc is lower than the hysteresis level, the first enable The signal s0v will turn on the input transistor 60. A transistor 140 is coupled to the transistor 12A and the first output terminal Sw. The transistor 14 is turned on according to the conduction state of the transistor 120. A resistor 116 is coupled The first output terminal sw, the transistor 125' 140', further provides a bias voltage to the transistor 125, 140 电阻-resistor 117, which is coupled to the transistor 140 for conducting an electricity when the transistor 12 is turned on. The crystal 129 is further coupled to the transistor 140. In addition, the transistor 129 is further coupled to the input transistor 6〇 to generate when the voltage level of the supply voltage Vc is higher than the high output voltage level. The first coincidence signal Sov is turned off and the input transistor 60 is turned off. The first transistor is connected to the first output terminal sw to extract the supply voltage vc β - a resistor 155 coupled to the second pole. Body 150 and a transistor 165, once the voltage supply voltage Vc is high The low output voltage level conducts the transistor 165. The subsense voltage of the dipole 15 determines the low output voltage level. A resistor 156 is coupled to the first output terminal SW and a transistor. The transistor 170 is further coupled to the first output terminal SW and the transistor 165. The transistor 170 generates the second enable signal SEN when the voltage level of the supply voltage Vc is lower than the low output voltage level. The figure is a circuit diagram of another preferred embodiment of the supply circuit 20. As shown, one of the first transistors 80 of this embodiment is connected in series with the input transistor 60 to provide the supply voltage Vc to the first output. End SW. The first transistor 80 is a positive critical device. The impedance device 7 is coupled to the input transistor 60 and the first transistor 80 to provide a bias voltage to turn on the input transistor 60 and the first transistor 80. When the voltage level of the supply voltage Vc is higher than the high output voltage level, the first enable signal Sov turns off the input transistor 60 and the first transistor 80. The first transistor 80 is used to provide protection to the supply circuit 20. When the supply voltage Vc is shorted, the first transistor 80 will be turned off to protect the input transistor 60. Please refer to the sixth drawing, which is a circuit diagram of another preferred embodiment of the power supply of the present invention. This embodiment is coupled to the turn-on and turn-off lines of one of the supply circuits 30 of the rectifier circuit 10 in synchronization with the line voltage VAC. The supply circuit 30 can be a power supply circuit, a power supply circuit, a power supply adjustment circuit, or a power source circuit. The supply circuit 30 can only be turned on when the input voltage Vjn is lower than an input threshold voltage, which can reduce the switching loss of the input transistor 60 and improve the efficiency of the supply circuit 3. Please refer to the seventh figure, which is a waveform diagram of the input voltage Vrw. When the input voltage VlN is lower than a threshold voltage VT, the power source of the input voltage Vm can be transmitted to the first output terminal sw. The critical voltage VT is related to the input threshold voltage. The supply circuit 30 includes a detection terminal DET coupled to the input voltage γΙΝ via an ink separation circuit 40. The voltage dividing circuit 4 is coupled to the input voltage Vm and the detecting end DET. The voltage dividing circuit 40 includes resistors 41, 42. The resistors 41, 42 are connected in series with each other. See Fig. 8', which is a circuit diagram of a preferred embodiment of the supply circuit 3 of the power supply of Fig. 6. As shown, the supply circuit 3A includes an input transistor (9) which sinks to the input terminal IN to receive the input house Vm to supply the supply voltage Vc at the first output terminal sw. The above input voltage \^ is the source of electricity. An input debt measuring circuit is characterized in that a positive input terminal is connected to the side terminal DET' of the supply circuit 30 to record the input voltage ^ from the voltage dividing circuit (10) side, and is generated according to the input power of the input terminal (4). The control reduces the input transistor 6〇 when the voltage level of the input electric dust is higher than the threshold voltage Vt. The control subtraction is via phase = input_circuit 75 and 歓f crystal green & cut-in input power input fine 1: way 75 includes fine boundary voltage %. The material voltage % is related to the input threshold 1322559 voltage. The critical value of the VT is the secret input circuit of the input circuit of the input circuit, which is connected to the first output terminal SW to measure the supply voltage Vc, and then according to the voltage level of the supply voltage vc. The first enable signal sov is generated at the first enable terminal ov. The circuit of the output detection circuit 100 of this embodiment can be implemented by a circuit of the fourth figure. The impedance device 70 is coupled to the input transistor 6A to provide a bias voltage to turn on the input transistor.
上述之第一致能訊號Sov係耦接於輸入電晶體60,以在供應電壓Vc之電 壓準位南於該局輪出電壓準位時截止輸入電晶體6〇。此外,輸出侦测電路 100更在第二致能端EN產生第二致能訊號Sen。第二致能訊號傳送至 低壓降穩壓器300 ’以在供應電壓Vc之電壓準位低於該低輸出電壓準位時 截止供應電路30之輸出電壓v〇。低壓降穩壓器300耦接於第二輸出端 OUT〇 而The first enable signal Sov is coupled to the input transistor 60 to turn off the input transistor 6〇 when the voltage level of the supply voltage Vc is at the local voltage level. In addition, the output detection circuit 100 further generates a second enable signal Sen at the second enable terminal EN. The second enable signal is transmitted to the low dropout regulator 300' to turn off the output voltage v of the supply circuit 30 when the voltage level of the supply voltage Vc is lower than the low output voltage level. The low dropout regulator 300 is coupled to the second output terminal OUT〇
請參閱第九圖,其為第六圖電源供應器之供應電路30之另一較佳實施 例的電路圖。如圖所示,供應電路30包括有輸入電晶體6〇,其耦接於輸 入端IN以接收輸入電壓\^。第一電晶體80,其串聯於輸入電晶體邰以 提供該供應電壓Vc至第一輸出端SW。輸入偵測電路75 ’其正輸入端耦接 於供應電路30之偵測端DET,以偵測輸入電壓vm進而依據輸入電壓% 之電壓準位產生控制訊號。輸入偵測電路75包括有臨界電壓ντ,其耦接 於輸入偵測電路75之負輸入端。第二電晶體65,其耦接於輸入偵測電路 75、輸入電晶體60以及第一電晶體80,以依據控制訊號截止輸入電晶體 60與第一電晶體80。當輸入電壓Vin之電壓準位高於臨界電壓乂丁時,輸 入電晶體60以及第一電晶體80將被截止。第一電晶體80與第二電晶體 65為正臨界裝置。 輸出偵測電路100,其耦接於供應電壓Vc,以依據供應電壓Vc之電 壓準位產生第一致能訊號Sov與第二致能訊號SEN。阻抗裝置70,其輕接 於輸入電晶體60與第一電晶體80,以提供偏壓,進而導通輸入電晶體6〇 與第一電晶體80。第一致能訊號Sov傳送至輸入電晶體60與第一電晶體 80,以在供應電壓Vc之電壓準位高於該高輸出電壓準位時截止輸入電晶體 60以及第一電晶體80。第二致能訊號SEN傳送至低壓降穩壓器300,以導 9Please refer to the ninth drawing, which is a circuit diagram of another preferred embodiment of the supply circuit 30 of the power supply of the sixth diagram. As shown, the supply circuit 30 includes an input transistor 6A coupled to the input terminal IN for receiving an input voltage. A first transistor 80 is coupled in series with the input transistor 邰 to provide the supply voltage Vc to the first output terminal SW. The positive input terminal of the input detection circuit 75' is coupled to the detection terminal DET of the supply circuit 30 to detect the input voltage vm and generate a control signal according to the voltage level of the input voltage %. The input detection circuit 75 includes a threshold voltage ντ coupled to the negative input terminal of the input detection circuit 75. The second transistor 65 is coupled to the input detecting circuit 75, the input transistor 60, and the first transistor 80 to turn off the input transistor 60 and the first transistor 80 according to the control signal. When the voltage level of the input voltage Vin is higher than the threshold voltage, the input transistor 60 and the first transistor 80 will be turned off. The first transistor 80 and the second transistor 65 are positive critical devices. The output detection circuit 100 is coupled to the supply voltage Vc to generate a first enable signal Sov and a second enable signal SEN according to the voltage level of the supply voltage Vc. The impedance device 70 is lightly coupled to the input transistor 60 and the first transistor 80 to provide a bias voltage to conduct the input transistor 6A and the first transistor 80. The first coincidence signal Sov is transmitted to the input transistor 60 and the first transistor 80 to turn off the input transistor 60 and the first transistor 80 when the voltage level of the supply voltage Vc is higher than the high output voltage level. The second enable signal SEN is transmitted to the low dropout regulator 300 to guide
I322S5S 年月日修正ί·I322S5S year, month and day correction ί·
通/截止供應電路30之輸出電壓ν〇。當供應電壓%之電壓準位低於低輸 出電壓準位時,輸出電壓V〇將被截止。 °月參閱第十圖,其為本發明之低壓降穩壓器300之電路圊。如圖所示, ”匕括有運算放大器31〇 ' 一傳輸元件eiement) 320與電阻325、 351、.3^。運算放大器310,其包括有一參考電壓Vref。參考電壓Vref耦 接於運算放大器31〇之一負輸入端。電阻352,其麵接於運算放大器3⑴ 之一正致能喊Sen傳送至運算歧11 31G’以提供電源至運 ^放大器31〇讓運算放大器31〇運作。傳輸元件no,其耗接於運算放大 =〇、第-輸出端sw以及第二輸出端ουτ。—旦,第二致能訊號Sen 月色f運算放大器31〇與傳輸元件32〇亦隨之禁能。電阻hi,其耗接 ;運算放大器31G之正輸入端、傳輸元件32()以及第二輸出端⑻^。電阻 25,其耦接於傳輸元件320,傳輸元件320可為電晶體。 故本發明實為-具有新雛、進步性及可供產業上彻者,應符合我 2利法專利申請要件無疑,妥依法提出發明專利申請,祈釣局早曰賜 准專利,至感為禱。 訾^ X上所述者僅為本發明一較佳實施例而已,並非用來限定本發明 圍’故舉凡依本拥中請專利顧職之形狀、構造、特徵及精 甲所為之解變化與修飾,均應包括於本發批申請專利範圍内。 1322559The output voltage ν〇 of the supply/disconnection circuit 30 is turned on/off. When the voltage level of the supply voltage % is lower than the low output voltage level, the output voltage V 〇 will be cut off. Referring to the tenth figure, it is the circuit block of the low dropout regulator 300 of the present invention. As shown in the figure, "the operational amplifier 31" is a transmission element eiement 320 and the resistors 325, 351, .3. The operational amplifier 310 includes a reference voltage Vref. The reference voltage Vref is coupled to the operational amplifier 31. One of the negative input terminals, the resistor 352, which is connected to one of the operational amplifiers 3(1), is called to send Sen to the operational reference 11 31G' to provide power to the amplifier 31, and the operational amplifier 31 is operated. It is consumed by the operational amplification = 〇, the first output terminal sw and the second output terminal ουτ. Once the second enable signal Sen moon color f operational amplifier 31 〇 and the transmission component 32 〇 are also disabled. Hi, its consumption; the positive input terminal of the operational amplifier 31G, the transmission element 32 () and the second output terminal (8) ^. The resistor 25 is coupled to the transmission element 320, and the transmission element 320 can be a transistor. For - with new chicks, progressive and available for industry, it should be in line with my 2 patent application requirements, and the invention patent application should be filed in accordance with the law. The Prayer Bureau will grant patents as soon as possible. The above is only a better example of the present invention. The examples are not intended to limit the invention. The changes, modifications and modifications of the shape, structure, characteristics and precision of the patent-seeking patents should be included in the scope of this patent application. 1322559
【圖式簡單說明】 第一圖為傳統電源供應器之電路圖; 第二圖為本發明之電源供應器之一較佳實施例的電路圖; 第二圖為本發明之電源供應器之供應電路之一較佳實施例的電路圖; 第四圖為本發明之供應電路之輸出偵測電路之一較佳實施例的電路圖; 第五圖為本發明之電源供應器之供應電路之另一較佳實施例的電路圖; 第六圖為本發明之電源供應器之另一較佳實施例的電路圖; 第七圖為本發明第六圖之電源供應器之輸入電壓的波形圖; 第八圖為本發明第六圖之電源供應器之供應電路之—較佳實施例的電路 圃, 第九圖為本發明第六圖之電源供應器之供應電路之另一較佳實施例的電路 圖;以及 第十圖為本發明之低壓降穩壓器之一較佳實施例的電路圖。 【主要元件符號說明】 10 整流電路 11 電容 12 電阻 15 電容 16 稽納二極體 20 供應電路 30 供應電路 40 分壓電路 41 電阻 42 電阻 50 電容 55 電容 11 1322559 年月曰修正替換κ 98. 12. θθ- 60 輸入電晶體 65 第二電晶體 70 阻抗裝置 75 輸入偵測電路 80 第一電晶體 100 輸出偵測電路 110 稽納二極體 112 稽納二極體 115 電阻 116 電阻 117 電阻 120 電晶體 125 電晶體 129 電晶體 140 電晶體 150 稽納二極體 155 電阻 156 電阻 165 電晶體 170 電晶體 300 低壓降穩壓器 310 運算放大器 320 傳輸元件 325 電阻 351 電阻 352 電阻 DET 偵測端 ΕΝ 第二致能端 1322559 - ,. ,叙Vff換頁丨 GND 接地端 IN 輸入端 Vac 線電壓 Vc 供應電壓 vIN 輸入電壓 V〇 輸出電壓 Vref 參考電壓 Vt 臨界電壓 Vz 調整電壓 OUT 第二輸出端 ov 第一致能端 sw 第一輸出端 Sen 第二致能訊號 S〇v 第一致能訊號 13BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a circuit diagram of a conventional power supply; the second figure is a circuit diagram of a preferred embodiment of the power supply of the present invention; the second figure is a supply circuit of the power supply of the present invention. The circuit diagram of a preferred embodiment of the present invention; the fifth diagram is a circuit diagram of a preferred embodiment of the power supply circuit of the present invention; FIG. 6 is a circuit diagram of another preferred embodiment of the power supply of the present invention; FIG. 7 is a waveform diagram of an input voltage of the power supply of the sixth embodiment of the present invention; The circuit of the power supply of the sixth embodiment, the circuit of the preferred embodiment, and the ninth is a circuit diagram of another preferred embodiment of the supply circuit of the power supply of the sixth embodiment of the present invention; and the tenth A circuit diagram of a preferred embodiment of a low dropout regulator of the present invention. [Main component symbol description] 10 Rectifier circuit 11 Capacitor 12 Resistor 15 Capacitor 16 Sense diode 20 Supply circuit 30 Supply circuit 40 Voltage divider circuit 41 Resistor 42 Resistor 50 Capacitor 55 Capacitor 11 1322559 曰 曰 替换 替换 98 98 98. 12. θθ- 60 Input Transistor 65 Second Transistor 70 Impedance Device 75 Input Detection Circuit 80 First Transistor 100 Output Detection Circuit 110 Sense Dipole 112 Sense Dipole 115 Resistor 116 Resistor 117 Resistor 120 Transistor 125 Transistor 129 Transistor 140 Transistor 150 Sense Diode 155 Resistor 156 Resistor 165 Transistor 170 Transistor 300 Low-Dropout Regulator 310 Operational Amplifier 320 Transmitter 325 Resistor 351 Resistor 352 Resistor DET Detecting End ΕΝ The second enabler terminal 1322559 - , . , Vv page change 丨 GND ground terminal IN input terminal Vac line voltage Vc supply voltage vIN input voltage V 〇 output voltage Vref reference voltage Vt threshold voltage Vz adjustment voltage OUT second output terminal ov first Enable end sw first output terminal Sen second enable signal S〇v consistent Signal 13
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