TWI321839B - Multi-chip stacked structure - Google Patents

Description

II. Violation number: TW2042PA Nine, invention description: [Technical field of invention] The invention relates to a multi-wafer stacked package structure, and in particular, the type can be purely for two or more stacks to reduce the overall stack Multi-wafer stacked package with increased chip package density and integration: [Prior Art] Due to the miniaturization and versatility of electronic devices, the demand for the influence of packaging on the appearance is gradually increasing. Semi-i body: degree. At present, it can satisfy such a heart. The bull-conductor granules or cymbals are packaged by stacking each other in a multi-chip package technology which is used in the package two-package unit to make a single Feng Meng set, " "The eve of the cattle conductor crystal volume storage capacity. For example, note 2::: can provide more functional material packaging methods so that a single mind "quote: the memory of the chip" is to use hair, in order to provide more data storage capabilities. One of the wire frame chains and the other f roads are connected to each other. The guide chain includes a series of lead frames connected to each other, for example, the die connection ratio s of the + standard lead frame standard lead frame. The secondary water is connected in a row. The wire is connected to the socket and the socket is connected to the wire (4) of the center of the work. Then, the protective layer is covered by the (4) or the fine Ming Feng and the part of the lead frame that the grain is in contact with, so that the other crystal/lead frame in the wire carrier chain is replaced by the resin material. ',?, handle. Retouching 1321839

ί达号: TW2042PA In the operation, the (4) connecting materials are separated and will be in the desired form. J Guided Acoustic - The problem often encountered in multi-chip packaging, especially when using the wire mounting method, the internal electrical connection, the inter-die signal conduction package, the A/input terminal signal (4) will restricted. In the = order, these points contain the leads of the lead frame, which are relatively less than the ::= on the die. Therefore, in the multi-chip package form on the lead frame, the connection of the die-disk wires is generally affected. Limited to the use of simple fanout (fan, t), and the connection between the die and signal transmission is also very limited. Multi-die packages requiring inter-granular connections and signal transfer capabilities can already be completed in a more expensive package, such as a spherical array package 〇^11耵1%%; 8(5々. Other general polycrystalline The problem that the grain package will encounter, especially the package in the form of lead frame, is the limitation of the available area of the die connection and the height of the overall package. Therefore, it is necessary to provide a multi-wafer stacked package structure capable of providing two or more stacks. The wafer is used to reduce the thickness of the stack, thereby increasing the density of the package and the whole humanity. α [Abstract] According to the object of the present invention, a multi-wafer stacked package structure including at least one first wafer is proposed and widely described. Having a first active surface and a first back surface, the first active surface includes a central region and a peripheral region having a plurality of first interfaces on a peripheral region of the first active surface; a lead frame includes a plurality of wires and a a wafer holder having at least a first bonding surface and a second bonding surface, the first bonding surface being bonded to the first active surface, Exposing the first pad to the outer edge of the wafer seat which comprises a plurality of first conductor lines and a plurality of second conductive wires, the first wires and second wires are positioned in the wafer seat 7

Sanda number: TW2042PA opposite sides or adjacent sides; at least one second wafer 'haves a second active surface and a first surface, the second active surface includes a central area and a peripheral area, and the second active surface There are a plurality of second pads on the peripheral area. The second active surface is adhered to the second bonding surface of the lead frame and exposes the second pad outside the edge of the wafer holder; and a plurality of gold wires, wherein some of the gold wires are electrically connected to the first pad and the first a wire, and a part of the gold wire is electrically connected to the second pad and the second wire. According to an object of the present invention, a multi-wafer stacked package structure is further provided, comprising: at least a first wafer stack set comprising at least two crystals [first wafer stack I, 'and including a first wafer having a first The active surface and a first back surface, the first active surface includes a central region and a peripheral region, the peripheral region of the first active surface has a plurality of first interfaces; a second wafer having a second active surface and a The first back surface 'the second active surface includes a central area and a peripheral area, and the peripheral area of the second active surface has a plurality of second ports. The second back=bonds the first active surface and exposes the first contact; the lead frame includes a plurality of wires and the wafer carrier has a first bonding surface and a j-th junction The bonding surface is adhered to the second active surface of the second wafer, and the exposed pad = a = and the second pad is outside the edge of the wafer holder. The wire comprises a plurality of wires and a plurality of second wires, wherein the first wire and the second wire are respectively located on opposite sides or adjacent sides of the crystal moon socket; a third wafer having a -third_perimeter and a second moon surface, the third active surface comprising - a central region and a region, the peripheral region of the third active surface having a plurality of fourth wafers having a fourth main narration The red surface of the dough spoon and the fourth back surface, the fourth active table includes a central area and a peripheral area, and the peripheral area of the fourth active surface is provided with a fourth mat. The fourth back system is the second sister who vomits and drinks the surface of the king, and exposes the first pad. The fourth active surface is adhered to the second bonding surface of the lead frame, and the 8 13 13839 is exposed.

No. 3: TW2042PA three pads and fourth pads are outside the edge of the wafer holder; and a plurality of gold wires, wherein some of the gold wires are electrically connected to the first pads and at least part of the first wires, and some of the gold wires are electrically connected The second pad is electrically connected to the at least part of the first wire, the part of the gold wire is electrically connected to the third pad and the at least part of the second wire, and the part of the gold wire is electrically connected to the fourth part of the second wire. The features and advantages of the present invention will be more apparent from the following description of the embodiments of the invention. The object and other advantages of the invention will be realized and attained by the description and the appended claims. It is to be understood that the following general description and the following detailed description of the present invention are intended to provide an explanation of the scope of the present invention.实施 [Embodiment] For a detailed indication of the embodiments of the present invention, please refer to the attached example. Its. Where the same or similar parts are indicated in all the figures, the same or similar

In the embodiment of the present invention, a lead frame thin package structure of a wafer stack structure of a plurality of layers is provided. The package structure of the present invention reduces stack thickness by stacking two or more wafers in the area of a thin, small-sized package. The present invention is applied to the processing of chip package density and integration (4) functions in a package, such as a domain card technology. 1 is a cross-sectional view of a multi-wafer stacked package structure 100 of an embodiment of the present invention. The multi-wafer stacked package structure 1 includes at least a 110th. The first wafer 11 has a first day and a second active surface 115 and the first-back first-active surface 115 includes a central area, and a plurality of first

Sanda number: TW2042PA The area around the art 125. The guest package 100 also includes a wire guide 130. The lead frame 130 includes a plurality of wires 134 and a wafer carrier, and the wafer holder 140 has at least one flute-filial adhesive surface 145 and a second adhesive surface 15A. The first bonding surface 145 is bonded to the first active surface u5 and exposes the first interface 125 outside the edge of the wafer holder 140. The wire includes a first wire "5 and a second wire 136. The first wire 135 and the second wire 136 are respectively located on opposite sides or adjacent sides of the wafer holder 140. In the first drawing, the first wire 135 and the second wire 136 are respectively located on the wafer holder 14〇. Explain the opposite sides. - Referring again to Figure 1, the multi-wafer stacked package structure 1 includes at least one second sheet 155, the first sheet 155 has a second active surface 160 and a second back surface 165, and the second active surface (10) includes a central area, and a peripheral area having a first pad 170. The second active surface 16 〇 is bonded to the second bonding surface 15 上 on the wafer holder 140 , and exposes the second interface 17 to be outside the edge of the wafer holder M0. The line 175 is connected to the first (four) 125 and The second interface 170 is electrically connected to the first via 125 and the first conductive line 135, and the partial gold wire 175 is electrically connected to the second pad 17 and the second wire 136. Repeatedly refer to the first! The first bonding surface 145, the first active surface ΐ5, the first bonding surface 150, and the first active surface are 16 〇, and can be bonded to a non-conductive solid body or a liquid body. Typically, liquid colloids are used, such as non-conductive silver hulls; or solid colloids, such as non-conductive films. Alternatively, a polysilicon stacked package structure 100 may be coated with a #18, covering the lead frame 13A, the first wafer 11A, the second wafer 155', and a plurality of gold wires 175. The sealant 18 can be a plastic or resin material. Figure 2 is a cross-sectional view showing another multi-wafer stacked package structure in accordance with an embodiment of the present invention. The multi-wafer stacked package structure 2 of the present invention includes at least a first wafer 210. The first wafer 210 has a first active surface 215 and a first

The three-sided number: TW2042PA, negative 220, the first active surface 215 includes a central area and a peripheral area, and the peripheral area of the first active surface 215 has a plurality of first pads 225. The multi-schip stack ^: package structure 2 〇〇 also includes a lead frame 23 〇. The lead frame 23 includes a plurality of wires 234 and a wafer holder 24, and the wafer holder 24 has at least a first bonding surface 245 and a second bonding surface 25A. The first bonding surface 245 is adhered to the first active surface 215 and exposes the first pad 225 outside the edge of the wafer holder 24. The wire includes a first wire 235 and a second wire 236. The first wire 235 and the second wire 236 are respectively located on opposite sides of the wafer holder 24 或 or adjacent sides of the φ. In the second figure, the first wire 235 and the second wire 236 are respectively located on the wafer holder 240. The opposite sides are explained. Referring again to FIG. 2, the multi-wafer stacked package structure 2 includes at least one second wafer 255. The second wafer 255 has a second active surface 26A and a second back surface 265. The second active surface 26 includes a central region and a peripheral region. The peripheral region of the second active surface 260 has a plurality of second pads. 270, the second active surface 260 is adhered to the second bonding surface 25A of the wafer holder 24, and exposes the second pad 270 outside the edge of the wafer holder 24. A plurality of gold wires 275 are connected to the first pads 225 and the second pads 27A, wherein a portion of the gold wires 275 are electrically connected to the first port 225 and the first wires 235, and a portion of the gold wires 275 are electrically connected to the second portion. The pad 27〇 and the second wire 236. Referring again to Fig. 2, the first bonding surface 245, the first active surface 215, the first bonding surface 250, and the second active surface 26A may be bonded by a solid colloid or a liquid colloid. The multi-wafer stacked package structure 2 can cover the multi-wafer stacked package structure 200 with a glue 28, covering the lead frame 23〇, a portion of the first wafer 21〇, a portion of the second wafer 255, and a plurality of gold lines 275. And exposing at least a portion 285 of the first back surface 22 and a portion 290 of the second back surface 265. FIG. 3A is a diagram showing the multi-wafer stacked package structure in FIG. 1

Sanda number: TW2042PA. More specifically, FIG. 3A shows that the first wafer 11 is located under the lead frame 13'. The first wafer 110 is surrounded by the plurality of first wires 135 and the second wires 136, and the second wafer 15 is removed. According to the present embodiment, the first pads 125 on the left side of the lead frame 13 图示 in the illustration may be distributed only at one edge of the peripheral region of the first active surface Π 5 of the first wafer 11 . This design allows the other wires 335 to have spatial contact with the second wafer 155 without interfering (structuralally or electrically) the second pads 170. According to the above embodiment, when the second wafer 155 is disposed on the lead frame 13 and

Above a wafer 110 (as shown in Fig. 3B), a multi-chip stacked package structure 100 as in Fig. i or a multi-wafer stacked package structure 200 in Fig. 2 can be produced. As shown in Fig. 3B, the two edges of the second wafer 155 are aligned with the two edges of the first wafer 11'. The resulting multi-wafer stacked package structure has the advantage of having a smaller total thickness than conventional structures, and is suitable for standard lead frame and surface mount technology (SMT) processes. The first wire 135 and the second wire 136 are respectively located on opposite sides of the wafer holder 14A. 3C is a plan view of a portion of the multi-wafer stacked package structure in FIG. 1. More specifically, FIG. 3C shows that the first wafer is located under the lead frame I%, and the first wafer 11 is 多A wire 135 and a second wire 136 are surrounded, and the second wafer 155 is removed. According to this embodiment, the first pads 125 may be disposed on two adjacent edges of the peripheral region of the first active surface 115 of the first wafer 11G. This design allows the wire 335 (on the diagonal of the first lens 11〇 in Figure 3) to spatially contact the first wafer m without interfering (mechanically or electrically) to the first crystal# The first of the two adjacent edges of the first active surface ιΐ5 is the first, 125. Similarly, the second wafer 155, as in the third, may have a second pad 170 (shown below the second chip 5 in FIG. 3D), and the second pad 17 is located on the second wafer 155. 12 1321839

Sanda number: TW2042PA Two adjacent edges of the peripheral area of the second active surface 16〇. This design allows the other wires 355 to have room to contact the second wafer 155 without interfering with (secondarily or electrically) the second pads 170. According to the above embodiment, when the second wafer 155 is disposed on the lead frame 130 and the first wafer 110 (as shown in FIG. 3D), the multi-wafer stacked package structure 100 or the second one in FIG. 1 can be produced. The multi-wafer stacked package structure 200 in the figure. As shown in Fig. 3D, the diagonal lines of the first wafer 11 and the second wafer 155 are aligned such that the second wafer 155 is relatively translated along the diagonal of the first wafer 11''. The resulting multi-wafer stacked package structure also has the advantage of less than the total thickness of the conventional structure 'suitable for standard lead frame and surface adhesion technology (where the first wire 135 and the second wire 136 are respectively located on the wafer) The opposite sides or adjacent sides of the socket _. Referring to FIG. 3E, a plan view of a portion of the multi-wafer stacked package structure 100 of the i-th diagram is further illustrated. More specifically, FIG. 3D shows the third The cymbal sheet HO is located under the lead frame 130, and the first wafer 11 is surrounded by a plurality of first lead wires. According to the embodiment, the first lands 125 may be distributed around the first active surface 115 of the first wafer ιι. On the opposite edges of the region, for convenience of drawing, a portion of the gold wire 175 in the first portion is connected to the first interface 125 and the first wire 135. This design allows the other wires 335 (located in the second wafer (5) in Figure 3f) The diagonal space can contact the second wafer (5) without interfering with (structure = or electrical) the second pad 17A. As shown in FIG. 3F, the first wire 135 and the first wire 136 are respectively located Adjacent sides of the wafer holder 14〇. According to the above embodiment, when the second wafer 155 is disposed on the lead frame (10) on the surface of the wafer U (as shown in FIG. 3F), a wafer stacked package structure as shown in FIG. The multi-wafer stacked package 2GG is shown in Fig. 2. The resulting multi-wafer package structure also has a structure similar to the conventional structure 13 for standard lead frame and surface adhesion technology (SMT) in any of the structures of Figures 3A to 3F. The resulting multi-wafer stack structure can be covered by a glue 18 〇 (as shown in Figure 1), or - a cover (as shown in Figure 2) covering 'and exposing the first back 12 如And a portion 290 of the second back surface 165. Other alternative sealing structures 4 〇〇 '41 〇 '42 〇 and 43 本 according to the present invention are shown in Figures A to 4D. These structures are similar to those in Figures 1 and 2 The structure is such that the wires can be located on the opposite edges of the any-wafer as shown in the third and fourth (fourth). Therefore, each of the structures 400, 410, 42 and 43 includes at least one first wafer, At least one of the two wafers 434' and the lead frame 436 are disposed between the first wafer 432 and the second wafer 434. In the fourth drawing And in FIG. 4D, the first wafer 432 has a first active surface 438. The first active surface 438 includes a plurality of first pads 44. In the fourth and second circles, the second wafer has a second The active surface 442, the second active surface 442 includes a plurality of second pads 44. The lead frame 436 includes a plurality of first wires 446 or second wires 447, and the first pads 440 and the second wires are respectively connected by a gold wire cap. Pad 444. ❿ Sanda number: TW2042PA The process of the total thickness is less. Figure 5 is a cross-sectional view of the multi-wafer stacked package structure of the present invention. The multi-chip stacked package structure 500 includes at least - A wafer stack group 51, the first wafer stack 51 includes at least two wafers, and at least two wafers include a third wafer 515. The first wafer 515 has a first active surface 516 and a first back surface 517. The first active surface 516 includes a central region and a peripheral region. The peripheral region of the first active surface 516 has a plurality of first pads 518. The b-th stack stack 510 also includes a second wafer 520 having a second active surface 521 and a second back surface 522. The second active surface 521 includes a central area and a peripheral area, and the peripheral area of the second active surface 521 is 1321839 'j-t · •

Sanda number: The TW2042PA domain has multiple second pads 523. Under the condition of the embodiment, the second back surface 522 can be adhered to the first active surface 516 and expose the first pad. Referring to FIG. 5, the multi-wafer stacked package structure 5 also includes a lead frame 530. The lead frame 530 includes a plurality of wires 535 and a wafer holder 532. The first substrate 532 has a first bonding surface 533 and a second bonding surface 544. The first bonding surface 533 is adhered to the second active surface 521 of the second wafer 52, and the first pad 518 is exposed. The second pad 523 is outside the edge of the wafer holder 532. The plurality of wires 535 include a first wire 531 and a second wire 534 which are respectively located on adjacent sides or opposite sides of the wafer holder 532. In Fig. 5, the first wire 531 and the second wire 534 are respectively located on opposite sides of the wafer holder 532. The multi-wafer stacked package structure 500 further includes at least one second wafer stack 540, the second wafer stack 540 includes at least two wafers, and at least two wafers include a third wafer 545. The third wafer 5 bucket 5 has a third active surface 546 and a third back surface 547. The third active surface 546 includes a central region and a peripheral region. The peripheral region of the third active surface 546 has a plurality of third connections. Pad 548. The second wafer stack 540 further includes a fourth wafer 550 having a fourth active surface 551 and a fourth back surface 552. The fourth active surface 551 φ can be adhered to the second adhesive of the wafer holder 532. The junction 544 is exposed, and the third interface 548 and the fourth pad 553 are exposed outside the edge of the wafer holder 532. In FIG. 5, there are a plurality of gold wires 560, wherein a portion of the gold wires 560 are electrically connected to the first pads 518 and at least a portion of the first wires 531. The portion of the gold wires 560 are electrically connected to the first pads 523 and at least partially first. Wire 53 1. A portion of the gold wire 560 is electrically connected to the third pad 548 and a portion of the second wire 534, and a portion of the gold wire 560 is electrically connected to the fourth pad 553 and at least a portion of the second wire 534. Referring again to FIG. 5, the first bonding surface 533, the first active surface 516, the second bonding surface 544, and the second active surface 521 may be solid colloid or liquid glue. The number is TW2042PA. 1 stack of $-package structure 5〇. It can be coated with polystyrene 58 多, and a number of gold wires 56 〇. The cross-sectional view is a cross-section of another multi-wafer stacked package structure of the present invention. The BaBa chip stacked package structure includes at least a first wafer stack and the 曰 first wafer stack 61 includes at least two wafers, and at least two wafers include a ruthenium 615. The first wafer 615 has a first active surface (four) and a first active surface 616 including a central region and a perimeter

The peripheral region of the region 'the first active surface 616 has a plurality of first pads 618. The first wafer stack 610 further includes a second wafer 62, the second crystal "2" has a second active surface 621 and a second back surface 622, and the second active surface 621

Including a central region and a peripheral region, the peripheral region of the second active surface 621 has a plurality of second pads 623. The second back surface 622 can be adhered to the first active surface 616 and exposed before conforming to the embodiment. The first pad 618. Referring again to Fig. 6, the multi-wafer stacked package structure 6A also includes a lead frame 630 including a plurality of wires 635 and a wafer holder 632. The wafer holder 632 has a first bonding surface 633 and a second bonding surface 644. The first bonding surface 633 is adhered to the second active surface 621 of the second wafer 620, and the first connection 618 and the first surface are exposed. The pad 623 is outside the edge of the wafer holder 632. The plurality of wires 635 include a first wire 631 and a second wire 634 which are respectively located on adjacent sides or opposite sides of the wafer holder 632. In Fig. 6, the first wire 631 and the first wire 634 are respectively located on opposite sides of the wafer holder 632. The multi-wafer stacked package structure 600 further includes at least one second wafer stack 640' including at least two wafers, and at least two wafers including a third wafer 645. The third wafer 645 has a third active surface 646 and a third back surface 647. The third active surface 646 includes a central region and a peripheral region, and the third active surface is 646 16 1321839

The three-numbered area: the peripheral area of the TW2042PA has a plurality of third pads 648. The second wafer stack 640 further includes a fourth wafer 650 having a fourth active surface 651 and a fourth back surface 052. The fourth active surface 651 includes a central region and a peripheral region, and the fourth active surface The peripheral area of 651 has a plurality of fourth pads 653. The fourth back surface 652 can also be bonded to the third main surface 646 and expose the third pad 648 before being conformed to the present embodiment. The fourth active surface 651 can be adhered to the second bonding surface 644 of the wafer holder 632 and expose the third pad 6 牝 and the fourth pad 653 outside the edge of the wafer holder 632. In Fig. 6, there are also a plurality of gold wires 66, some of which are electrically connected to the pads 618 and at least a portion of the first wires 63A. A portion of the gold wire 66 electrically connects the second pad 623 and at least a portion of the first wire 631. A portion of the gold wire 66 is electrically connected to the third pad 648 and at least a portion of the second wire 634. And a portion of the gold wire 660 is electrically connected to the fourth pad 653 and at least a portion of the second wire 634. Referring to FIG. 6, the first bonding surface 633, the first active surface 616, the first bonding surface 644, and the second active surface 621 may be bonded to each other in a solid colloid or a liquid state. The multi-wafer stacked package structure can be a glue-coated multi-wafer stacked package structure 600, covering the lead frame 63〇, a portion of the first wafer stack group 610, a portion of the second wafer stack group 64〇, and a plurality of gold The line ^ exposes a portion 685 of the first back side 617 and a portion 690 of the third back side 647. A seventh drawing shows a plan view of a portion of the multi-wafer stacked package structure of the fifth circle. More specifically, the first wafer stack is shown under the lead frame 530 =, the first wafer stack The 510 is surrounded by a plurality of first wires 531, and the first wafer stack 54 is removed. According to the present embodiment, the first pads 518 and the second pads (2), which are shown on the left side of the lead frame 530-1, may be distributed only on the first active surface 516 and the second wafer 52 of the second die. One of the peripheral regions of the active surface 521 is an edge. This design allows other wires to be 731 17 1321839

三赖号=TW2042PA

There is a space to contact either of the first wafer 515 and the second wafer 520, or both, without interfering (structuralally or electrically) the first pads 518 and the second interfaces 523. Similarly, the second wafer stack 54 〇 in FIG. 7B may have a third pad 548 and a fourth pad 553 on the right side of the lead frame 530 (the third wafer 545 and the first in FIG. 7B respectively) The undersides of the four wafers 550 are also only distributed on one of the peripheral regions of the third active surface 546 of the third wafer 545 and the fourth active surface 551 of the fourth wafer 550. This design allows the other wires 731 to have spatial contact with any or all of the first wafer 515, the second wafer 520, the third wafer 545, and the fourth wafer 550 without interfering with (structural or electrical) Three pads 548 and fourth pads 553. According to the above embodiment, when the second wafer stack 54 is disposed on the lead frame 530 and the first wafer stack 51 (as shown in FIG. 7), a wafer stack as in the fifth stack can be generated. The package structure 500 or the multi-wafer stacked package structure 600β of FIG. 6 is as shown in FIG. 7 , and the two edges of the second wafer stack 54 are aligned with the two edges of the first wafer stack 51 . The resulting multi-wafer = stacked package structure also has the advantage of less than the total thickness of the conventional structure, which is suitable for the use of the wire and the surface adhesive technology is also called techn〇i〇gy, sMT) process ', medium' The first wire 531 and the second wire 534 are respectively located on opposite sides of the wafer holder 532. A schematic view of the multi-wafer stacked package structure 500 (shown in the drawing) is shown in FIG. More specifically, FIG. 7C illustrates that the first wafer stack is under the lead frame 530, surrounded by a plurality of wires 531, and the second wafers 523, 540, and 540 are removed. According to the present invention, the first pad 518 and the second connection may be distributed on the adjacent two edges of the first active surface 516 of the second main snippet 510 and the peripheral area of the surface 521 of the second wafer 520. on. This design 18 1321839 1 ,

Sanda number: TW2042PA allows other wires 731 (on the diagonal of the first wafer stack 51 〇 as shown in FIG. 7C) to have spatial contact with either of the first wafer 515 and the second wafer 520, or both At the same time 'without interference (physical or electrical) first pad 518 and second pad 523. Similarly, the second pad stack 54 〇, the third pad 548 and the fourth pad 553 in FIG. 7D may be respectively distributed on the second active surface 546 of the third wafer 545 and the fourth wafer 550. Two adjacent edges of the peripheral region of the active surface 551. Similarly, this design allows other conductors to have spatial contact with any or all of the first wafer 515, the second wafer 52, the third wafer 545, and the fourth wafer 550 without interference (structural aspects) Or electrical aspects) W third pad 548 and fourth pad 553.

According to the above embodiment, when the second wafer stack 54 is disposed on the lead frame 530 and the first wafer stack 51 (as shown in FIG. 7D), the wafer stacking pattern as shown in FIG. 5 can be generated. The package structure or the multi-wafer stacked package (4) 600 in FIG. As shown in Fig. 7D, the second wafer stack 540 is aligned with the diagonal of the first wafer stack 51, such that the second wafer stack 540 is translated diagonally relative to the first wafer stack. The resulting multi-slice stacked package structure also has the advantage of less total thickness than the known structure, and is suitable for the standard lead frame and surface mount technology Cface _nt technology SMT) process. As shown in Fig. 7D, the first wire 53i and the second wire are located on opposite sides or adjacent sides of the wafer holder 532, respectively. (d) 2 7A ~ 7D diagram of the "quote" structure, the resulting multi-stack stacking is covered with - sealant 580 (as shown in Figure 5), or a glue m 6 figure) cover ' A portion 685 of the first back surface 617 and a second portion 69 of the surface 647 are exposed. 19 1321839

No. 3: The number of wafers above and below the TW2042PA rack does not need to be the same. In view of the above, the present invention has been described above in terms of a preferred embodiment, and is not intended to limit the invention, and various modifications may be made without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. 20 Fees ^ Sanda Number: TW2042PA [Simple Description of the Drawings] The attached graphic contains & 4··^ content, which is used to describe this book' and is also part of the invention's features, advantages, and ^ BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a multi-wafer stacked package structure according to an embodiment of the present invention.

3A to 3B are plan views of the first to the stacked package structure; 3C to 3D are plan views of the first stacked package structure; and 3E to 3F are plan views of the first to 12th package structure; 2, FIG. 4A to 4D of a polycrystalline wafer wafer stack of an embodiment of the present invention in a plurality of drawings of an embodiment of the present invention, showing another embodiment of the present invention. Structures; FIG. 6 is a cross-sectional view showing a multi-wafer stacked package structure according to a further embodiment of the present invention;

Multi-wafer stacked package Nos. 7A to 7B are plan views showing a multi-wafer stacked package structure of an embodiment of the present invention in FIGS. 5 to 6; and FIGS. 7C to 7D are diagrams showing the present invention in FIGS. 5 to 6 A plan view of a multi-wafer stacked package structure of an embodiment. [Major component symbol description] 100, 200, 400, 410, 420, 430, 500, 600: multi-wafer stacked package structure 110, 210, 432, 515, 615: first wafer 115, 215, 438, 516, 616 : First active surface 21 1321839

Sanda number: TW2042PA 120, 220, 517, 617: first back surface 125, 225, 440, 518, 618: first pads 130, 230, 436, 530, 630: lead frame 134, 234, 335, 535, 635, 731: wires 135, 235, 446, 531, 631: first wires 136, 236, 447, 534, 634: second wires 140, 240, 532, 632: wafer holders 145, 245, 533, 633: First bonding surface 150, 250, 544, 644: second bonding surface 155, 255, 434, 520, 620: second wafer 160, 260, 521, 621: second active surface 165, 265, 522, 622 : second back surface 170, 270, 444, 523, 623: second pads 175, 275, 448, 560: gold wires 180, 280, 580, 680: sealant 285, 685: portions 290, 690 of the first back face The second back portion 510, 610: the first wafer stack 540, 640: the second wafer stack 545, 645: the third wafer 546, 646: the third active surface 547, 647: the third back 548, 648: Third pads 550, 650: fourth wafer 551, 651: fourth active surface 552, 652: fourth back surface 22 1321839

Sanda number: TW2〇42PA 553 '653: fourth pad 23

Claims (1)

Sanda number: TW2042PA *---- X. Patent application scope: 月 曰 repair (gas) original 1. A multi-wafer stacked sealing structure, comprising: at least a first wafer having a first active surface and a first back surface, the first active surface includes a central area and a peripheral area, the peripheral area of the first active surface has a plurality of first pads; a lead frame comprising a plurality of wires and a wafer holder The wafer holder has at least one first bonding surface and a second bonding surface. The first bonding surface is adhered to the first active surface, and the first pads are exposed on the edge of the wafer holder. The wire includes a plurality of first wires and a plurality of second wires, the first wires and the second wires are respectively located on opposite sides or adjacent sides of the wafer holder; / at least one The second wafer has a second active surface and a second back surface, the first active surface includes a central area and a peripheral area, and the peripheral area of the second active surface has a plurality of second pads thereon. The active surface is adhered to the second bonding surface of the lead frame, and the second pads are exposed outside the edge of the wafer holder; the MI plurality of gold wires, wherein some of the gold wires are electrically connected The first pads are connected to the s-wires, and some of the gold wires are connected to the second wires; and the 蛩 封 ' cover covers the lead frames. The structure of claim 1, wherein the first bonding surface, the first active surface, the second bonding surface, and the second active non-conductive solid colloid or liquid colloid are bonded. . μ 3· Please refer to the structure described in the scope of the patent, which has == less, the circumference of the first active surface of the first wafer on the first wafer. The structure of claim 1, wherein the second interfaces are distributed on the peripheral region of the second active surface on at least one of the second wafers One of the edges. 5. The structure of claim 1, wherein the first pads are disposed on two adjacent edges of the peripheral region of the first active surface on at least one of the first wafers. 6. The structure of claim 1, wherein the second knives are disposed on at least two adjacent edges of the peripheral region of the second active surface on the second wafer. 7. The structure of claim 1, wherein the plurality of linings are disposed on opposite edges of the peripheral region of the first active surface on at least one of the first wafers. 8. The structure of claim i, wherein the second pads are disposed on opposite edges of the peripheral region of the second active surface on the second wafer. 9. The structure of claim 2, wherein the sealant is coated; to the first wafer, at least one of the second wafer, and the gold wires. The structure of the first aspect of the invention, wherein the sealant covers at least one of the first starter, the at least one of the second wafer, and the wires are exposed At least a portion of the horse's first back and at least a portion of the second back. The multi-wafer stacked package structure comprises: at least one first wafer stack stack comprising: to; comprising two wafers, the first wafer stacking day, having a first active surface and a first active surface comprising a central region and a peripheral region, the first peripheral region having a plurality of first pads; 25 1321839 Sanda number: TW2042PA a second wafer 'having a second active surface and a second back surface' The surface includes a central region and a peripheral region, the peripheral region of the second active surface having a plurality of second pads; wherein the second back surface is adhered to the first active surface, and the first pads are exposed a lead frame comprising a plurality of wires and a wafer holder having: a first bonding layer and a second bonding surface, wherein the first bonding surface is adhered to the second wafer The second active surface ′ and exposing the plurality of first contacts and the second pads outside the edge of the wafer holder, wherein the wires comprise a plurality of first wires, and the plurality of second wires are - the wire and the second wire are respectively located on opposite sides or adjacent sides of the wafer holder; at least one second wafer stack group comprising at least two wafers, the second wafer stack group comprising: a second wafer having a third active surface and a third back surface, the second active surface comprising a central region and a peripheral region, the peripheral region of the third active surface having a plurality of third pads; a fourth wafer having a fourth The active surface and a fourth back surface 'the fourth active 纟© includes a central area $ and a peripheral area _, the peripheral area of the fourth active surface having a plurality of fourth pads; = - wherein the fourth back side Bonding the third active surface and exposing the third pads, the fourth active surface is adhered to the second bonding surface of the lead frame, and the third pads and the fourth connections are exposed Padded on the outside of the wafer holder; a plurality of gold wires, wherein some of the gold wires are electrically connected to the first pads and to the first wires, and some of the gold wires are electrically connected The second pads /, the evening Dividing the first wires, the plurality of gold wires electrically connecting the third wires 26 1321839 « ♦ Sanda number: TW2042PA 塾 and at least some of the second wires, and some of the gold wires are electrically connected to the wires a fourth pad and at least a portion of the second wires; and an adhesive layer covering the lead frame. 12. The structure of claim 5, wherein the first bonding surface, the second active surface, the second back surface, the first active surface, the first bonding surface, and the fourth active The surface, the fourth back surface, and the third active surface are bonded by a non-conductive solid colloid or liquid colloid. 13. The structure of claim 5, wherein the first pads are distributed over at least one edge of the peripheral region of the first active surface on the first wafer. 14. The structure of claim 5, wherein the second interfaces are distributed over one edge of the i-side region of the second active surface on at least one of the second wafers. 15. The structure of claim 5, wherein the third junctions are distributed over at least one edge of the perimeter region of the third active surface on the third wafer. 16. The structure of claim 5, wherein the fourth knives are disposed on an edge of the peripheral region of the fourth active surface on the J-fourth wafer. 17. The structure of claim 5, wherein the first pads are distributed on at least two adjacent edges of the peripheral region of the first active surface on the first wafer. 18. The structure of claim 5, wherein the second interfaces are distributed on two adjacent edges of the peripheral region of the second active surface on at least one of the second wafers. 19. The structure of claim 5, wherein the third 27 1321839 Sanda number: TW2042PA pads are distributed over the peripheral region of the third active surface on at least one of the third wafers Two adjacent edges. 20. The structure of claim 5, wherein the fourth interface is distributed over at least one of the four sg μ###. + _ the fourth active surface of the fourth day of the dynasty Two adjacent edges on the peripheral region. 2 1. The patent application scope 11 covers at least one of the first wafer stack and the gold wires. The structure of the item, wherein the sealant is at least one of the second wafer stacking group, and the scope of the patent application is covered by at least the first wafer stack „ which is illegal and coughing, and ^ - the first wafer stack and the second wire and at least a portion of the third back. The first back of the knife and at least part of the 28