TWI320260B - Primary-side controlled switching regulator - Google Patents

Description

-1320260 IX. Invention Description: [Invention Name]: - Switching Regulator Replacement Page for Secondary Side Control [Technical Field of the Invention] The present invention relates to a switching regulator, more specifically, the present invention relates to an isolated type Switching adjustment

[Prior Art] Various switching adjustments H have been widely used to provide regulated voltages and currents. The off-line switching regulator must provide its isolation between the secondary side and the secondary side for safety reasons. Therefore, the control circuit is switched on the secondary side of the regulator, and an optical-coupler and a secondary side circuit are required for adjusting the output voltage and an output current of the switching regulator. In order to reduce the size and cost of the ϋ adjuster, the switching regulators of the f-free optical and secondary circuits are currently in the trend.

In the recent development, many primary side control schemes have been proposed, such as U.S. Patent No. 6,721, entitled "PWM Controller Regulating Output Voltage and Output Current in Primary Side", which was developed by Yang Dayong (τν%η§γ & ηδ). U.S. Patent No. 6,836,415, entitled "Primary_side Regulated Pulse Width Modulation Controller with Improved Load Regulation", which was invented by Yang Dayong et al., and the invention entitled "Flyback Power Converter Having a Constant Voltage and a" U.S. Patent No. 6,862,194 to Constant Current Output under Primary-side PWM Control. However, a disadvantage of the prior art primary side control scheme is that it is less precise in controlling the output voltage and output current. Daily repair | replacement

I 98-5-22 [Invention] The 1-second-side switching regulator includes a switching element for switching (4) to transfer energy from, to the same (4) long side to its secondary side, a control circuit is reduced. Transformer, used to generate everything, ', knife change switch and adjust the output of the regulator. The control circuit includes a 1-circuit of the market-to-beauty device for generating a reflection signal through the measuring transformer - a __ signal and a timing signal, a sequence of signal sizing pressure (four) - a discharge _... a second road and The third circuit generates a _second signal by integrating a motor wave pure number and a timing signal, and the towel electric form signal indicates a side switching current of the transformer. Furthermore, the time constant of the 'third circuit is associated with the switching period of the switching signal. A first error amplifier having a first reference signal is used to generate a first-reverse age number according to the first letter. In order to improve, the load regulation h reference h is increased according to the increase of the second signal. A second feedback signal is generated by a second error amplifier having a second reference signal. Therefore, the kill signal is generated by the -switch control circuit based on the first feedback signal and the second inverse noise. When the signal is switched, the switching signal has a minimum on-time (on_time;), and a minimum value of the discharge time is read for multi-sampling the reflected signal. The above and other objects, features and advantages of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; -1320260 98-5-22 A t [Embodiment] Fig. 1 illustrates a conventional switching regulator for primary side control. The switching regulator includes - "1", which has -__A, _-secondary winding Np, and - secondary winding, _s. The regulator's output voltage V〇 and the wheel current] [a control lightning L 电路 circuit 70 generates a switching signal VpWM to a transistor 2〇 for switching the transformer 10. Fig. 2 is a view showing a plurality of key signal waveforms of the conventional switching regulator shown in Fig. 1. When the switching signal 乂_ is high (1Ggie_high), it can be correspondingly enchanted: Nathana P. - A peak Ipi of the secondary side switching current 1P can be expressed by the following equation: T VlN ^ (1) fri = — xTon Lp where VIN is the input voltage applied to the transformer (4), and Lp is the transformer _ The inductance value of the secondary scale and the conduction time of the T〇N疋 switching signal γ·ρννΜ.

The one-blade 5ffevPWM is reduced to a low potential (logic l〇w), and the energy stored in the transformer 1〇 is transferred to the secondary side of the drain (10) and transmitted via the rectification (10) to the output of the switching regulator. Correspondingly, the _ under-side switching current Is is also generated. The secondary side switching current knows a ^ can be expressed by the following equation: I-^&gt;xTDS ^ ^ ...一-----------.........------...-( 2) ', V 〇 is the output voltage of the switching regulator, Vf is a forward voltage drop of the rectifier 4 ,, and Ls is one of the C ί ο ο ο ο ο ο ο ο The secondary side switches a discharge time of the current ls. A reflection signal Vaux is generated at the auxiliary winding Na of the transformer 10. The reflected signal VAUX can be expressed by the following equation: (3)

Vaux = I^x(V〇 + Vf) 98-5-22

Ι3&amp;· ! Jane Page I where 'TNA and TNS are the winding turns of the auxiliary winding NA and the secondary winding |i_Ns of the transformer 10, respectively. When the secondary side switching current Is drops to zero, the reflected signal VAUX level begins to decrease. It also means that the energy of the transformer 10 is completely released at this moment. Therefore, the discharge time Tds in the equation (2), as shown in Fig. 2, can be measured from the falling edge of the switching signal VPWM to the point at which the reflected signal νΑϋΧ starts to fall. The secondary side switching current Is is determined by the number of winding turns of the primary side switching current transformer 1〇. It can be obtained from the following gas tables:

Is =

Tnp Tns xIp - (4) where TNp is the number of winding turns of the primary winding np of the transformer 10. Referring to FIG. 1, the control circuit 70 includes a power supply terminal να: ίσ_ground GND for receiving power. - The sub-shoes connected between the transformers 变α and the ground reference potential are formed by a resistor 5G and -f. The control (f) of the resistor-to-end (4) resistors and the resistors 51 are generated at the DET detection terminal DET.

Vdet —

Rsi R50H-R51 x Vaux --(5) where Rm and Rsi are the resistance values of resistors 5〇 and 51. The power reflection signal V charges the capacitor 65 through the transmission-rectification_ to provide the control circuit %. The current sensing resistor Wei is a current sensing element. The current sense resistor 3q is connected from the transistor _ source to the reference potential, so that the transistor current is determined as - _ signal %. The control circuit _- 嫩 峨 _, just the butterfly signal ^ control circuit 70 - the round-out end guess produces a switching signal νρ_ to switch (four) ❼. One electric charge, the current compensation end «c〇 stomach-like Peng, _ make the fiber to solve the compensation. The first complement U-channel can be connected to a capacitor connected to the ground reference potential, such as a capacitor ^. A '1320260 dJ. ^98-5^22------&lt; COMI is connected to the second compensation network for frequency compensation of a second error amplifier. The second compensation network can also be connected to the _ capacitor, such as capacitor Wei. _ can be programmed (4) c〇mr is connected to the resistor 33 connected to the ground to adjust the voltage feedback loop according to the output current 1〇 to the control circuit 7〇-reference money Vref. The avoidance of the reference signal Vref is to compensate for the voltage drop of the output Wei cup to achieve better load regulation. Figure 3 illustrates a control circuit 7A in accordance with an embodiment of the present invention. A first circuit is resampled by the voltage vDET to generate - (4) Vv and timing signals &amp; The timing signal Sds represents the discharge time TDS of the secondary side switching current Is. A second circuit 3 (9) generates a current waveform signal vw by measuring the current sensing signal Vcs. The oscillator 200 generates a dial signal PLS for determining the switching frequency of the switching signal VPWM. - The third circuit 4 〇〇 generates a second signal V1 through the integrated current waveform signal ^ and the timing signal &amp; An operational amplifier Ή and a reference signal form a first error amplifier for amplifying the first signal Vv and providing a first feedback loop circuit for the turn-off voltage control. An operational amplifier 72 and a reference signal vREF2 form a first error amplifier for amplifying the second signal % and providing a second feedback loop circuit for output current control. An adjustment circuit 7 is connected to the programmable terminal (3) factory to base the -reference signal vREF 々 second health Vl. reference (four) Vref. The pulse width modulation circuit 5A and the comparators 73, 75 form a switching control circuit to generate the switching signal VpwM, and control the pulse width of the switching signal ¥_ according to the outputs of the first error amplifier and the second error amplifier . The operational amplifiers 72 have a transconductance (t Yanyun). The operational amplifier ·-wheel (4) is connected to the voltage compensation terminal C0MV and the positive input terminal of the comparator 73. The output of the operational amplifier coffee is connected to the current compensation terminal C0MI and the positive wheel input terminal of the comparator 75. A negative input of comparator 73 is coupled to the - wheel terminal of an adder 600. Comparison | A negative wheel input of §75 is supplied with a ramp signal RMP 〇9 132 from the oscillating device 2 )) M ifim ------- ——&gt; 98-5-22 . Adder 600 adds the current sense signal Vcs to the ramp signal RMP to generate a slope signal, and the positive input terminal of the VsLP° comparator 74 is supplied with a reference signal EV_. The negative input of the comparator 74 is connected to the sensing terminal cs' to achieve periodic (eyde_by_eyde) current limiting... and an input of the closing 79: & and connected to the comparator 73, respectively? The outputs of 4 and 75. A reset signal rst is generated by the turn-off of the anti-free 79. The reset signal RST is supplied to the pulse width modulation circuit 5 (10) for controlling the duty cycle of the switching signal VPWM. A current-controlled lion road system switches the current from the opposite side to the secondary side. The city is inspected and the signal is switched. The signal is changed. The pulse is changed. The reference is changed. The reference signal is static. The beginning of the current is ^! (4) No, the secondary side switching current secret-secondary switching current is proportional. According to the figure A, the L-wire 'switches the turn-out current χ. It is the average value of the secondary _ commutating current &amp; It can be as follows: Thus, the output current of the switching regulator is adjusted. The first circuit 300 detects the current sensing signal &amp; and generates a current waveform signal Vw accordingly. The third circuit side transmits the integrated current waveform signal Vw and the discharge time &amp; and further generates the second signal %. The second mirror Vi can be expressed by the following equation: (7) Λ7 Vw Tds Vi =——- 2 Τι where the current waveform signal 可由 can be expressed by the following equation

Vw=SxRsxIs where Τι is the time constant of the third circuit 4〇〇 (8) ~--*- A L98 98-5-22 ----------- 1320260 V. • Refer to the equation ( 6)-(8), the second signal can be re-displayed as follows to see the ratio of the output current to the second signal V1 and the switching regulator. The second signal Vi increases as the output current 1〇 increases. However, the maximum value of the second signal % will be limited to the value of JUUVREF2 through the adjustment of the current control loop. Under the feedback control of the current control loop, the maximum output current of 1 〇 (coffee) will be expressed by the following equation:

I〇(max)

GaxGsW X Vr£F2

Tns

1 + (GaxG ~ swx·?^) (10) where κ is a constant equal to Tl/T, Ga is a gain of the second error amplifier, and G is the switching circuit - gain m control 瞒 _ 増 很High (GaxGsw>&gt; 〇, the maximum output current I〇(max) can be briefly defined as follows: (11)

The Tns Rs thus adjusts the maximum output of the switching regulator to a constant current according to the reference signal V.

In addition, the face-making pendulum shoots the sampling rhyme and rushes the letter _ to carry out the pulse width adjustment (four) 侃, and its reference signal vref(7;) controls the pure value of the reflection signal. As shown in equation (3), the domain trust is equal to the output voltage %. The reflected money Vaux is further attenuated to a voltage VDET as shown in the equation (5). The first circuit 1 多重 multisamples the voltage I to generate a first signal Vv. Through the adjustment of the voltage control loop, the value of the first signal Vv is controlled in accordance with the value of the reference signal v. The first-error amplifier and the city circuit provide voltage-controlled gamma-path gain. Therefore, the output voltage V〇 is briefly defined as the following equation: 11 98-5-22 1320&amp;h!

Vo = :^±5!1XI^XVREF)-VF Rso Tna (12) The first circuit 100 multisamples the reflected signal VAUX. The voltage is sampled and measured immediately before the secondary side switching current drop is zero. Therefore, the change in the secondary side switching current Is will not affect the value of the forward voltage drop VF of the rectifier 40. However, when the output current changes by 1 ,, the voltage drop of the output power thin 46 also changes. The adjustment circuit 700 is for compensating for the voltage drop variation of the output power thin 46. Resistor 33 is used to program a slope ' to determine the change in reference signal VREF based on the change in the second signal. Therefore, the voltage drop is compensated in proportion to the output current of 1 。. Using resistors 33 of different values, the various compensation effects of the various outputs can be programmed. Figure 4 illustrates a first circuit 1A in accordance with an embodiment of the present invention. A sample pulse generator produces a sample pulse signal for multiple sampling. A threshold voltage 156 is added to the reflected signal VAUX to generate a level-shift reflected signal. The first signal generator includes a counter 171 and a gate 165. .166 for generating a plurality of sampled signals VSP1·. ySPN. The second signal generator includes a flip-flop l7, a reverse gate 163, a gate 164 and a comparator I% for generating a timing signal SDS. A time delay circuit includes an inverter 162, a current source 180, a transistor 181, and a valley state 182' for generating a delay time when the switching signal VPWM is disabled. An input terminal of the inverter 161 is supplied with a switching signal VPWM. An output of the inverter 161 is coupled to an input of the inverter 162, a first input of the gate 164, and a clock input of the D-type flip-flop 170. The signal at the output of the inverter 162 is used to turn on/off the transistor 181»the capacitor 182 is connected in parallel with the transistor 181. Current source 180 is used to charge capacitor 182. Therefore, the current of the current source 18 和 and the capacitance of the capacitor 182 will determine the delay time of the time delay circuit! ^. The output of the time delay circuit is obtained on capacitor 182. A D input of the D-type flip-flop 170 is pulled to a high potential by a supply voltage Vcc. 〇 type flip-flop 17 〇 input 12 1320260 任.': L.i lr·; * ::. ^ \ 98. 5. 98-5-22 The end is connected to a second wheel of the gate 164. The gate 164 outputs a timing signal SDS. Therefore, when the switching signal VPWM is disabled, the timing signal SDS is enabled. An output of the anti-gate 163 is coupled to a reset input of the 正-type flip-flop 170. The two inputs of the NAND gate 163 are connected to an output of the time delay circuit and an output of the comparator 155, respectively. A negative input of comparator 155 is provided by a displacement reflected signal. A positive input terminal of comparator 155 is supplied with a holding voltage Vhd. Therefore, after a few delays, once the displacement reflection signal is lower than the hold voltage VHD, the timing signal Sds is disabled. In addition, the timing signal sDS will also be disabled once the switching signal VpWM is enabled.

The sampling pulse signal is supplied to the third input of the counter 171 and the gate 165·.166. The plurality of outputs of the counter 171 are respectively connected to the second input of the gate 165. The first input of the gate 165_.166 is supplied with a timing signal SDS. The fourth input of the gate 165·.166 is connected to the wheel terminal of the time delay circuit. Therefore, a plurality of sampling signals vSP1..vSPN are generated based on the sampling pulse signal. Further, a plurality of sampling signals VSP1·_VSPN are alternately generated during the enable period of the timing signal sDS. However, the delay time 1\| is inserted before the timing signal sDS is enabled, so that the plurality of sampling signals vspi..VspN are disabled during the period of the delay time·^.

The plurality of sampling signals VSP1··VSPN are used to sequentially sample the reflection/^ 乂 乂 经 obtained by the detection terminal det and the voltage divider. A plurality of sampling signals 1 1 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州 州The switch 123·.124 is connected in parallel with the capacitor 110..111 for discharging the capacitor 110..111. A buffer circuit includes an operational amplifier 150. _151, a diode 130.131, and a current source 135 for generating a holding voltage yHD. The positive wheel terminals of the operational amplifiers 15 〇 . . .151 are respectively connected to the capacitor 110. .m. The negative input of the operational amplifier 150_151 is connected to an output of the buffer circuit. The diode 130·131 is connected from the output of the operational amplifier 150.151 to the output of the buffer circuit. Therefore, the holding voltage VHD is obtained from a higher voltage of a plurality of holding voltages. Oscillation letter 13

The PLS switch No. 98-5-22 periodically turns on/off the switch 125 to conduct the holding voltage v to the capacitor plus. The switch 125 is turned on/off via the oscillation signal PLS. After the delay time ^, the plurality of sampling signals HR start to generate a plurality of holding voltages. Therefore, the surge interference of the reflected signal V is eliminated (printing of the interference), wherein the surge interference of the reflected signal may occur when the switching signal % plane is disabled and the transistor is turned off. When the secondary side switching current 1s falls to the material, the reflected signal VAUX begins to decrease. When the comparator I% detects the aforementioned state, the pulse width of the timing signal Sds is associated with the discharge time TDS of the under-side switching current Is. Meanwhile, when the timing signal Sds is disabled, the plurality of sampling signals Vspi·.Vspn are disabled and the multi-sampling is stopped. At this time, the holding voltage VHD generated at the output of the snubber circuit will be correlated with the reflected signal 取样 sampled when the secondary side switching current 15 is reduced to zero. The holding voltage Vhd is obtained from a plurality of higher voltages of the holding voltage, and if the reflected signal Vaux&amp; starts to decrease, the sampled voltage is ignored. Figure 5 illustrates an oscillator 2 in accordance with an embodiment of the present invention. A first voltage to current converter is formed by an operational amplifier 201, a resistor 21A, and a transistor 250. The first voltage to current converter generates a reference current of 125 根 according to a reference \. A current mirror is formed by a plurality of transistors, such as transistors 251, 252, 253, 254, and 255 'for generating from a reference current 125 — - a recharger charging current and an oscillator discharge current I 255 » a transistor 253 One of the drains flows out of the oscillator charging current l2S3. A drain of transistor 255 flows into the oscillator discharge current. A switch 23 is connected between the drain of the transistor 253 and a capacitor 215. The ramp signal RMP is taken from capacitor 215. A positive input of a comparator 205 is coupled to capacitor 215. The comparator 205 outputs an oscillation signal PLS. The switching frequency of the switching signal VPWM is determined by the oscillation signal PLS. A first terminal of a switch 232 is supplied with a high threshold voltage vH. A first end of a switch 233 is supplied with a low threshold voltage VL. a second end of the switch 232 and a second end of the switch 233 14

'1320260 is connected to a negative input of comparator 205. An input of an inverter 260 is coupled to an output of the comparator 2〇5 to generate an inverted run-up signal /PLS. A switch 231 and a switch 233 are turned on/off by the oscillation signal PLS. The switch 230 and the switch 232 are turned on/off by the inverted oscillation signal /PLS. A resistance value R2 of the resistor 210 and a capacitance value C2!5 of the capacitor 215 will determine the switching period τ of the switching frequency: T =

C215X V〇SC

Vr/ R210 where V〇sc = Vh-Vl 0

=Raiox C215X

Vosc &quot;vT (13) Figure 6 illustrates a second circuit 300 in accordance with an embodiment of the present invention. A fourth circuit includes a comparator 310, a current source 320, switches 330, 340, and a capacitor 361. The peak value of the current sense signal Vcs is sampled to produce a quaternion. A positive input terminal of the comparator 31 is supplied with a current sensing signal. A negative input of comparator 310 is coupled to capacitor 361. Switch 33 is connected between current source 32A and capacitor 361. Switch 330 is turned on/off by a signal at an output of comparator 310. The switch 34A is connected in parallel with the capacitor 361 to discharge the capacitor 361. A switch 35 〇 periodically conducts the fourth signal to the capacitor 362 to generate a current waveform signal Vw. Is the switch 35 swayed by an oscillating signal? 1^ On/Off. Figure 7 illustrates a third circuit 4A in accordance with an embodiment of the present invention. A second voltage-to-current converter includes an operational amplifier 41A, a resistor 450, and a transistor 42A, 421, 422, an operational amplifier 41A, a positive input terminal for a current waveform. Operational amplification _- negative input connected to the resistor benefit 450. A signal at an output of operational amplifier 410 drives a gate of transistor 42A. The gamma-source side of the transistor is connected to a resistor 45 〇. Through the recording of the transistor 42A, a current "generated by the second voltage-to-current conversion is generated according to the current waveform signal Vw. The transistors 421 and 422 form a current mirror having a ratio of 2: ^. Via the transistor 422 - no Pole 'current! secret current mirror to generate - programmable charging current IPRG. Programmable charging current 1 (; can be expressed by the following equation: 15 1320268^13⁄4 98-5-22 where R4S0 is a resistor of resistor 450 The electric grid 471 is used to generate an - integral nickname. The switch 46 〇 is connected between the pole of the transistor 422 and a battery 471. The switch 46 导 is turned "off" by the timing signal s 〇 s. The capacitor is connected in parallel with the capacitor c1 to discharge the capacitor 471. The switch 461 periodically conducts the integrated signal to the capacitor 472 to generate the second signal V!. -_461 is turned on/drum by the MEPLS. 0 This second signal can be Obtained on capacitor 472 as follows:

Vi =

-X R450 X C47I

Vw 2 x Tds (15) According to an embodiment of the invention illustrated in Figs. 4 to 7, the second signal % is associated with the secondary side switching current 1s and the wheeling current 1〇 of the switching regulator. Therefore, equation (9) can be re-expressed as follows: where m is a constant, which is determined by the following equation:

_R210XC215 V〇SC m = R450XC471X~Vr .............................(17) Resistor 450 The resistance value is 5 〇 associated with the resistance value of the resistor 210. An electrical value (: 471) of the capacitor 47ι is associated with the capacitance c215 of the capacitor 215. Therefore, the second signal % is proportional to the wheel current 10 of the switching regulator. Figure 8 illustrates an embodiment of the invention. The schematic diagram of the circuit of the pulse width modulation circuit 5 。. The pulse width modulation circuit 500 includes a reverse-and-close S11, a 正-type flip-flop 515, a system 519, an occlusion circuit 52 〇, and an inversion. The -D input of the 512, 518»D-type flip-flop 515 is driven by the supply voltage V (X is pulled to _ high potential. The - input of the inverter 512 is driven by the oscillation signal PLS. One round of the inverter 512 The output is connected to d-type 16 1320260, .^'· . * _ '·; ;% r-ί ^^8-5*-22 ^ ^

A clock-in terminal of the flip-flop 515 is connected to the -th input terminal of the AND gate 519 to enable an output terminal of the switching signal VpwmdD type flip-flop 5ΐ5. The second input of the AND gate 519 is lightly coupled to the output of the inverter 512. The gate 519 rotates the switching signal VpwM ' to switch the transformer 1 〇. A reset input ^6 of the 正-type flip-flop 515 is connected to an output of the anti-gate 511. A first input of the NAND gate 511 is supplied with a reset signal RST to periodically disable the switching signal VpwM. A second wheel-in terminal of the NAND gate 511 is coupled to an output of the occlusion circuit 520 to ensure a minimum on-time of the switching signal VpwM when the switching signal VpWM is enabled. The minimum on-time of the switching signal VPWM ensures a minimum of the discharge time tds which ensures proper multi-sampling of the reflected signal Vaux in the first circuit 100. The discharge time TDS is associated with an on time τ 切换 of the switching signal vpwM. Referring to the secondary side inductance values ls shown in equations (1), (2) and (4)' and equation (18), the discharge time TDS is expressed by the following equation (19):

Ls = (Tns/Tnp)2xLp

Tds =

VlN , TNS π 77-rr-) x − xTon Vo + Vf Tnp (18) (19) where T 〇 jv is the on-time of the switching signal Vpwm.

An input of the blanking circuit 520 is supplied with a switching signal vpwM. When the switching signal VpWM is enabled, the blanking circuit 520 will generate an occlusion signal VBLK to suppress the reset of the D-type flip-flop 515. The occlusion circuit 520 further includes a reverse gate 523, a current source 525, a capacitor 527, a transistor 526, and inverters 521, 522. The input terminal of the inverter 521 and a first input of the inverse gate 523 supply a switching signal VPWm. Current source 525 is used to charge capacitor 527. The transistor 526 is connected in parallel with the capacitor 527. The transistor 526 is turned on/off by the signal at the output of the inverter 521. An input of inverter 522 is coupled to capacitor 527. An output of inverter 522 is coupled to a second input of anti-gate 523. An output of the inverse gate 523 outputs an occlusion signal Vblk. The pulse width of the blanking signal Vblk is determined by the current value of the current source 525 and the capacitance of the capacitor 172. An input of inverter 518 is coupled to the output of anti-gate 523. An output of inverter 518 generates a clear signal CLR to turn on/off switches 123, 124, 34 〇 and 462 β

Figure 9 illustrates a circuit diagram of adder 6 (9) in accordance with an embodiment of the present invention. A third voltage to current converter is formed by an operational amplifier 610, transistors 620, 621, 622, and a resistor 650 for generating a current In2 in accordance with the ramp signal RMP. A positive wheel input terminal of an operational amplifier 611 is supplied with a current sensing signal Vcs. The -negative input of operational amplifier 611 is coupled to its -output to cause operational amplifier 611 to act as a buffer. A drain of the transistor 622 is connected to an output of the operational amplifier 611 via a resistor 651. The slope believer is obtained from the poles of the transistor 622. Therefore, the slope k number VSLp is associated with the ramp signal RMP and the current sense signal \^.

Figure 10 illustrates a circuit diagram of an adjustment circuit 7A in accordance with an embodiment of the present invention. A voltage-to-current converter-operational amplifier 71A, transistors 711, 714, 715, and a resistor 712 are formed for generating a current I"5 according to the second signal V!. Operational Amplifier 7 - Positive Loss The human terminal is supplied with a second reed. The current 1715 is output to the programmable terminal c〇MR. The current &amp; combines the resistor to generate a voltage VCOMR and is lightly connected to the operational amplifier 720. The other is the voltage to current converter. An operational amplifier can, transistor 721, 724, 725' and - resistor 722 are formed for generating a current - 1725 at the pole of the transistor according to the voltage. The __ negative input of the operational amplifier 75 () The human terminal is connected to its output terminal to make the operational amplifier 750 act as a buffer. A positive wheel terminal of the operational amplifier 75A is connected to the reference signal VRm. The pole of the f crystal 725 is connected via the resistor 76〇. To the output of the operational amplifier %❶. The reference signal VREF is taken from the transistor 725. Based on the reference signal _, the reference signal ~ is adjusted by the second signal Vi and programmed by the resistor 33. 18 1320260 π

Any cooked 'thus, although this day's coffee is difficult to make a real thing, as above, but it is rumored to set the invention, this artist, in the Juxian 剌 骑 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Turning gamma 0 material fiber _ private for. [Simple diagram]

The accompanying drawings are included to clearly illustrate the present invention, and reference to the embodiment of the present invention, and the embodiment of the present invention, and the detailed description of the present invention. Fig. 1 is a circuit diagram showing a switching regulator of a conventional-secondary control. Figure 2 illustrates the key signal waveforms of the conventional switching regulator. Figure 3 illustrates a control circuit in accordance with an embodiment of the present invention. Figure 4 illustrates a first circuit in accordance with an embodiment of the present invention. Figure 5 illustrates a vibratory vessel in accordance with an embodiment of the present invention. Figure 6 illustrates a second circuit in accordance with an embodiment of the present invention. Figure 7 illustrates a third circuit in accordance with an embodiment of the present invention. Figure 8 illustrates a pulse width modulation circuit in accordance with an embodiment of the present invention. Figure 9 is a circuit diagram showing an adder in accordance with an embodiment of the present invention. Figure 10 illustrates an adjustment circuit for programming a reference signal in accordance with an embodiment of the present invention. 19 &lt;-98, 9. 23⁄4 98-9-24 [Explanation of main component symbols] 1❶: Transformers 20, 181, 250, 251, 252, 253, 254, 255, 420, 421, 422, 526, 620, 621 , 622, 711, 714, 715, 721, 724, 725: transistor 30: current sensing resistors 31, 32, 65, 110, 111, 115, 182, 215, 361, 362, 471, 472, 527: capacitor 33, 50, 51, 210, 450, 650, 651, 712, 722, 760: resistors 40, 60: rectifier 46: output cable, 70: control circuits 71, 72, 150, 151, 201, 410, 610, 611, 710, 720, 750: operational amplifiers 73, 74, 75, 155, 205, 310: comparators 79, 163, 511, 523: inverse gate 100: first circuits 121, 122, 123, 124, 125, 230, 231, 232, 233: switches 130, 131: diodes, 135, 180, 320, 525: current source 156: threshold voltages 161, 162, 260, 512, 518, 521, 522: inverter 164, 165, 166, 519: and gates 170, 515: D-type flip-flop 171: counter 20 1320260 g|· ΟΙ 躲 2 98-5-22 190: sampling pulse generator '200: oscillator' 300: second Circuit. 330, 340, 350, 460, 46 1, 462: switch 400: third circuit 500: pulse width modulation circuit 520: blanking circuit 600: adder

700: adjustment circuit CLR: clear signal COMI: current compensation terminal COMR: programmable terminal COMV: voltage compensation terminal CS: sensing terminal DET: detection terminal GND: ground terminal # OUT: output terminal PLS: oscillation signal _ / PLS : inverting Oscillation signal RMP: Ramp signal VCC: Power supply terminal 1250: Reference current [253: Inverter charging current 255: Vibration/discharge current 21 98-5-22 moM) rMtm ' 1622 : Current. I〇: Output current

Ip : — secondary side switching current Ιρί : peak

Is : secondary side switching current Isi : peak value Na : auxiliary winding ΝΡ : - secondary winding Ns : secondary winding SDS : timing signal T 〇 s : discharge time T 〇 n · conduction time Vaux : reflected signal Vblk : blanking signal Vcc : power supply voltage Vcs : current sense signal Vdet *• voltage VH : high threshold voltage VHD : hold voltage Vr : second signal VIN : input voltage VL : low threshold voltage V 〇 : output voltage Vp \ VM : switching signal 22 1320260 9i 1 98-5-22

Vr, Vref, VreFI, VreF2, VreF3: Reference signal VSLP: Slope signal VSP1_ ‘Vspn: Sampled signal

Vv: first signal Vw: current waveform signal

twenty three

Claims (1)

Year, month and day correction replacement page 98-5-22 coffee" Ten, the scope of patent application: 1. A primary side control switching regulator, which comprises: - Transforming 'for the energy from the transformer - the secondary side Passing its secondary side; a switching element for switching the converter; and - a control circuit 'remaining to the transformer for generating a switching signal for switching the switching element and adjusting the switching adjustment One round of the device, wherein the control circuit comprises: a first circuit coupled to the transformer, measuring a reflected signal of the transformer to generate a -first signal and a timing signal' and wherein the timing signal indicates the transformer - the discharge time; - the second circuit and the - third circuit, which pass the integral __f stream signal and the timing signal to generate - the -1⁄2 number, and the towel of the current signal wire indicates the change of the shoe - Wei Switching current; - a first error - a signal having a ____ reference signal for generating a -th feedback signal according to the first signal, and wherein the first reference signal is increased according to the second signal And increase; - the first error And having a second reference signal for generating a first; feedback signal according to the second signal; and - switching control weaving path, which is generated according to the first and second age numbers The switching signal. 2. The switching regulator of the secondary side control according to claim 1, wherein the control circuit further comprises: a power terminal and a ground terminal for receiving power; and a detecting terminal for transmitting - a resistor of 1 is connected to the suspension; 24 -1320260 a sensing end for connecting the second circuit to the _ current sensing element to receive the current signal and the current sensing element is switched to the current signal by the touch-to-field switching; a component for generating the switching signal to switch the transformer; - a voltage compensation terminal, a connected-first compensation network for frequency compensation of the first error amplifier; - a current compensation terminal 'connected to - a second compensation network for frequency compensation of the second error amplifier: and - Programmable terminal 'connected - resistor to - grounded to determine - slope, wherein the slope represents a change in the first reference signal versus a change in the second signal. 3. The secondary side control switching controller of claim 1, wherein a time constant of the third circuit is associated with a switching period of the switching signal. 4. The first circuit of the switch includes: a threshold voltage, wherein the threshold voltage is added to the reflected signal to generate a displacement reflection signal; Capacitor L; produces a plurality of sampled signals, wherein the sampled signals are used to sample the reflected sigma, and do not generate a voltage on the capacitors, and in the scale The sampling signals are sequentially generated during an enable period of the signal; a buffer circuit that generates a hold signal from the secret radiation high voltage of the capacitors; and the capacitor 用于 is used to generate the signal according to the hold signal The first signal and the 25 98-5-22 I320^^¥#Mi n product m is used to generate the timing signal, and the timing signal is enabled when the switching signal is disabled, and when the displacement is reflected When the hold signal is lower than this hold signal, the timing signal is forbidden. 5. The switching regulator of the primary side control of claim 1, wherein the first circuit resamples the reflection number to generate the first signal, and the j__ The first signal is obtained when the discharge current drops to zero. 6. The switching regulator of the secondary side control as described in claim 1, wherein the second circuit comprises: a fourth circuit that generates a fourth signal by sampling the current signal: a second An electrical benefit that maintains the fourth signal; a second output capacitor 'which produces a current waveform signal; and a switch that conducts the fourth signal to the second output capacitor. The switching regulator of the primary side control according to claim 1, wherein the third circuit comprises: a voltage to current converter, which generates a charging current according to the current waveform signal; a sequenced electric current device coupled to the charging current via a first switch to generate an integrated signal according to the timing signal; a second switch coupled in parallel with the timing capacitor to perform the timing capacitor Discharge; a third output capacitor that generates the second signal; and a third switch that conducts the integrated signal to the third output capacitor. 26 .1320260 Μ ft Α Α Α 驳 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. 8. — A value used to multisample the reflected signal. a small switching regulator comprising: a transformer for transmitting the secondary side of the transformer to a secondary side; the switching element '帛 correcting the transformer; and a control circuit 'to the transformer, for generating a - switching signal for switching the switching element and adjusting the output of the switching regulator, wherein the control circuit comprises: the first circuit 'the contact device 'Transducing the reflected-reflected signal of the transformer to generate a first-signal and-timing signal' and the timing signal represents a discharge time of the transformer; - a second circuit that generates a flow through the integral 1 and generates the timing signal a second signal, and the current money represents the -_ times_changing current of the Wei n; a first feedback circuit 'for generating a first feedback 唬 according to the first signal and the __ first reference signal, The first reference signal is changed according to the change of the second signal; - the second feedback circuit 'for generating a second feedback signal according to the second signal; and - the switching control circuit 'the lion's first feedback signal And the switching signal according to claim 9, wherein the control circuit further comprises: a power terminal and a ground terminal for receiving power; End, for connecting the first circuit to the transformer; 27 98-5-22 132 Ming Jie replacement page || a sensing end for coupling the second circuit to a current sensing element to receive the a current signal, wherein the current sensing element is configured to convert the secondary side switching current into the current signal; an output end is configured to generate the switching signal to switch the transformer through the switching element; and a voltage compensation terminal is used The frequency compensation of the first feedback circuit; and a current compensation terminal for frequency compensation of the second feedback circuit. 11. The switching regulator of claim 9, wherein the first circuit comprises: a boundary voltage, wherein the threshold voltage is added to the reflected signal to generate a displacement reflection signal; a plurality of capacitors; a - money generator that generates a plurality of turn signals to sample the anti-alias and maintains the reflected signal in the capacitors 其 'there are in-service f-containers respectively generating a multi-reward voltage, and according to the timing Activating the signal to generate a sampling signal; - a buffer circuit 'which generates the first signal according to the holding voltages; and a second signal generating H' which generates the timing signal according to the touch wire and the touch shot. When the age class is enabled, the timing signal is enabled, and when the #touch reflection signal is lower than the guaranteed voltages, the timing signal is disabled. 12. The switching regulator of claim 9, wherein the first circuit multi-samples the reflected signal to generate the first signal, and records the transformer (four)-discharge current_zero to obtain the The first signal. 13. The switching regulator of claim 9, wherein the second circuit comprises: a stream generator that generates a charging current by sampling the current signal; and an electric grid The charging current is used to generate the second signal 28.1320260 5. a : according to the timing signal. The switching regulator described in the ninth aspect of the patent, wherein when the switching signal is enabled, the cut-numbered-minimum conduction phase ensures that the __-most is used for multi-sampling the reflected signal . 15. A switching power converter comprising: a voltage transformer for transmitting the energy from a _-second side of the transformer to a secondary side; a switching component 'for switching the transformer; a control circuit '__ the transformer for generating a switching signal to switch the switching element and adjusting an output of the switching power converter, wherein the control circuit comprises: a first circuit 'which is connected to the transformer, A first signal is generated by measuring a reflected signal of the transformer; the first circuit 'generates a second signal according to the current signal, wherein the current signal represents the ~~ under-current of the variable_; a first feedback circuit, which generates a first feedback number according to the first signal and a first reference signal. The first reference signal changes according to the change of the second signal. The first feedback circuit is according to the second The signal generates a second feedback signal; and a switching control circuit that generates the switching signal according to the first feedback signal and the second feedback signal. 16_ The switching power converter of claim 15 wherein the control circuit further comprises: a power terminal and a ground terminal for receiving power; and a detecting terminal for transmitting through a voltage divider a resistor connecting the first circuit to the transformer; 29 98-5-22 • an inductive terminal for connecting the second circuit to the current sensing element to receive the current signal, wherein the current sensing element And configured to convert the current-side switching current into the current signal output end, and configured to generate the switching signal to switch the transformer through the switching component-first compensation terminal for frequency compensation of the first feedback circuit; And - the second compensation terminal ' is used for frequency compensation of the second feedback circuit. The switching power converter of claim 15, wherein the first circuit comprises: a plurality of capacitors; a first-signal surname H, which generates a plurality of miscellaneous pieces of the rib signal for sampling and maintaining the reflected signal in the capacitors, and the plurality of capacitors are hard to generate a plurality of holding voltages, and according to a timing signal Enabled to generate a plurality of sampling signals; a buffer circuit that generates the first signal according to the holding voltages; and a second signal generator that generates the timing record according to the holdings, wherein when the switching signal is disabled 'The timing signal is used' and the timing signal is disabled when the reflected signal is below the hold signal. 18. If the applicant applies for the care of the electric power meter as described in item 15, the towel-circuit circuit multi-samples the reflected signal to generate the first-signal, and the _discharge current of the surface device The first signal is obtained by zero. 19. The secret f-switch as recited in claim 15 of the patent application, wherein the switching signal has a minimum on-time when the switching signal is enabled, which further ensures a minimum value of the discharging time for Reflected signal for multi-sampling 20. A switching regulator, which contains: 30 1320260 year old beam replacement page Ω only .h2---* 98-5-22 meaning [for the energy from the transformer - - the secondary side is transmitted to the secondary side; - the switching 7 element 'for switching the transformer; and the control circuit' is connected to the transformer for generating a switching signal for switching the switching element and adjusting the switching regulator An output circuit, wherein the control circuit comprises: a first circuit coupled to the transformer to generate a first signal by measuring a reflected signal of the transformer; the first circuit 'which generates a measurement-current signal to generate ― a second subtraction, wherein the current signal is associated with an output current of the switching regulator; the feedback circuit 'includes a reference money for generating an anti-aliasing number according to the first signal and the reference signal and The age test is changed by the second signal; and - the switching control f path 'the root feedback signal produces the switching signal. 21. The switching regulator of claim 2, wherein the first circuit comprises: a plurality of capacitors; - the first-signal m generates a plurality of sampling signals for sampling and maintaining the reflected signals The reflected signal generates a plurality of holding voltages on the capacitors respectively, and generates a plurality of sampling signals according to activation of a timing signal; a buffer circuit that generates the first signal according to the holding voltage And a second signal generator that generates the timing signal according to the holding voltages, wherein the timing signal is enabled when the switching signal is disabled; and when the reflected signal is significantly lower than a holding signal The signal system is disabled. 31 U2m〇n (1) &amp; stone replacement page -- 98-5-22 22 · The switching regulator described in claim 20, wherein the _ _ _ _ hai hai reflection number is multi-sampled to generate The first signal, and once the transformer is placed. - Go to zero and choose. Get the first signal. X- 23. The switching regulator of claim 20, wherein the second circuit comprises: a current generator that generates a charging current according to the current signal; and a 'capacitor' The charging current is generated by the second signal according to the lining signal. It is recognized that if the secret signal is turned over, the material is turned over, and when the secret signal is enabled, the switching signal has a minimum conduction time, which further ensures a minimum value of the discharge time, and is used for the reflection signal. Perform multiple sampling. 32