1315〇87 九、發明說明： , 【發明所屬之技術領域】 本發明係關於金屬氧化物介電膜的形成方法及半導體記憶裝 置的製造方法，尤有關於適合用來形成dram (動態隨機存取記 憶體）的電容絕緣膜的金屬氧化物介電膜的形成方法及採用該方 . 法的半導體記憶裝置的製造方法。 【先前技術】 *以往’氧化组（TaO)、五氧化二鈕（Ta2〇5)、二氧化鈦（Ti〇2) 等金屬氧化物介電體受喜好而被採用作爲DRAM的電容絕緣膜。 此f絕緣膜通常藉由使用金屬有機物的熱化學蒸鍍方式，堆積成 ，晶質狀態，但若使用金屬有機物前驅物，則碳元素會進入金屬 =化物内。過剩的碳元素會在金屬氧化物介電膜内I生較大的漏 電流，使絕緣膜的功能降低，此為其存在的問題。 法(爲參ΐΪΠ巧有)研究出下述金屬氧化物介電膜的形成方 氧化物介1膜，接著在,·氣體環 f約60〜⑽秒’除去非晶質金屬氧化物介電膜中加， 再在惰性_魏刊高於金觀化齡電素’ =環境下以高於結晶溫度的溫度（例如日日， 止形成二氧化矽層。 电犋中的氧空位’同時防 ^另)有與本發明相關的其他各種先前技術已公開（參照專利文獻 專利文獻1特表2〇〇2 —527904號公報 專利文獻2特開2001 —53253號公報 6 1315087 專利文獻3特開2001 —24169號公報 專利文獻4特許第3211747號 ， 專利文獻5特許第3296307號 【發明内容】 登盟所欲解決之卩1靡 -使更新速率越低，：以保長’可 可提供高性能的記憶裝置。 此適a於移動式製品， • 雖然專利文獻1揭露的方法可一定程度地抽ρ •介麵峨漏電流（電容職屬氣化物 由於DRAM的資訊保持時間（_)不僅受電 因此如果不同時充&低接面漏電流）的影響， -DRAM的資訊保持=低電4電&和接祕電流，就難以提高 w fff由在下部電極的表面上職被舰（半球狀矽II 凸，來增大電容ϋ的容量，但在其上形 ί的等微小缺陷，即使形成了正常的介電膜，也會在後1315〇87 IX. Description of the Invention: [Technical Field] The present invention relates to a method for forming a metal oxide dielectric film and a method for fabricating a semiconductor memory device, and more particularly to a method for forming a dram (dynamic random access) A method of forming a metal oxide dielectric film of a capacitor insulating film of a memory and a method of manufacturing a semiconductor memory device using the method. [Prior Art] * Conventional metal oxide dielectrics such as an oxide group (TaO), a pentoxide oxide (Ta2〇5), and a titanium dioxide (Ti2) have been used as capacitor insulating films for DRAMs. The f-insulating film is usually deposited in a crystalline state by a thermochemical vapor deposition method using a metal organic substance, but if a metal organic precursor is used, the carbon element enters the metal = compound. The excess carbon element causes a large leakage current in the metal oxide dielectric film to lower the function of the insulating film, which is a problem. The method (for the ginseng) has been developed to form a cermet oxide dielectric film of the following metal oxide dielectric film, followed by a gas ring f of about 60 to 10 seconds to remove the amorphous metal oxide dielectric film. Sino-Canada, and then in the inertia _Wei magazine is higher than the Jinguan aging electrons' = environment at a temperature higher than the crystallization temperature (for example, day to day, the formation of cerium oxide layer. Oxygen vacancies in the electric raft) simultaneously prevent ^ In addition, there are other various prior art related to the present invention. (Patent Document 1 Patent Publication No. 2 〇〇 2 - 527 904, Patent Document 2, JP-A-2001-53253, No. 6 1315087 Patent Document 3, JP-A-2001- Patent No. 24169 Patent Document 4, No. 3211747, Patent Document 5, Patent No. 3296307 [Summary of the Invention] 登 1 欲 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡 靡This is suitable for mobile products, • Although the method disclosed in Patent Document 1 can extract a certain amount of interface leakage current (capacitor duty vaporization due to DRAM information retention time (_) is not only charged, so if not Charge & low junction The effect of the current, - DRAM information retention = low power 4 electric & and the secret current, it is difficult to improve w fff by the surface of the lower electrode on the surface of the ship (hemispherical 矽 II convex, to increase the capacitance ϋ Capacity, but tiny defects such as ί on it, even if a normal dielectric film is formed, it will be
m 產生介電膜品質惡化的問題。因此，需^在唯持雷A »絕緣膜的可靠性的同時，能匕S在維持電谷 (卿特性）的新技術。b進妹同0罐的資訊保持特性 的金】Ϊ化J充分降低漏電流的高品質 •的製造方法。賴的士成方法及採用該方法的半導體記憶裝置 般決問題的方法 =HSF 二種===== 介電膜_溫度的;驟溫 7 1315087 ’以高於該金屬氧化物介電膜的結晶溫度的第二溫度 •驟:加熱至低於該金屬氧化物介電膜=晶溫= ίϊϋΐΐ”緩冷經過比該第—及第二熱處理步驟長的時間 至亥苐二溫度的規定溫度爲止的第三熱處理步驟。 -法，ί半料導體記憶裝置的製造方 i-费—獎二=裝置匕3皁兀電晶體和與該單元電晶體連接的 造方法包括形成覆蓋該單元電容器的下部電極 ，介電膜形成步驟，該介電膜形成步驟包含 • ίί:在??下部電極的非晶質金屬氧化物介電膜的成 氧化物介電結晶溫度的第—溫度加熱該金屬 ，㈣—度加熱錢屬氧化物介電膜，從*使m A problem of deterioration in the quality of the dielectric film. Therefore, it is necessary to maintain the reliability of the A-insulating film while maintaining the reliability of the electric film. b The information retention characteristic of the sister and the 0 cans] The high quality of the leakage current is fully reduced. The method of using the taxi and the method of solving the problem with the semiconductor memory device using the method=HSF two kinds===== dielectric film_temperature; the temperature of the temperature is 7 1315087' is higher than the metal oxide dielectric film a second temperature of the crystallization temperature: a step of heating until the metal oxide dielectric film = crystal temperature = ϊϋΐΐ ϊϋΐΐ 缓 缓 缓 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过 经过a third heat treatment step. - Method, ί half-material conductor memory device manufacturing method i-fee - award two = device 匕 3 saponin crystal and connection with the unit transistor includes forming a lower portion covering the unit capacitor An electrode, a dielectric film forming step, the dielectric film forming step comprising: • heating the metal at a temperature of an oxide metal crystallization temperature of the amorphous metal oxide dielectric film of the lower electrode, (4) - Degree heating money is an oxide dielectric film, from *
Hi 步驟、將該金屬氧化物介電膜加熱= 3二後’再Μ緩冷經過比該第—及第二熱處 理ί‘Ξ 低於該第三溫度的規定溫度爲止的第三熱處 巧明中，該第三熱處理步驟宜在氧氣環境下進行。 180 ί二中」ίΖ及ί二熱處理步驟中的加熱宜進行60至 ^該苐二熱處理步驟中的緩冷宜進行6〇至1〇〇分 t，iT月 一熱處理步驟中的該第一溫度宜爲600至㈣ 熱處理步驟中的該第三溫度宜編= 爲=至_〇,邊第三 ίί=，Ϊ金屬氧化物介電膜宜由氧她巾⑴構成。 的步ί 成膜步驟之前宜更包含對該基體進行熱氮化 本發明中，第二熱處理步驟宜是用快速熱處理 第三熱處理步驟宜是職散爐進行加熱^驟。σ”、、 8 1315087 =金屬乳化物介電臈，同時可降低接面漏電流;^的=品質 膜的可#性’同時可提高DRAM _“特=(= 【實施方式】 下面^照關詳細制本發_較佳實施 圖1是表示半導體記憶裝置製 發明較佳實施分，即本 圖2〜圖5 A干咅Ii-闽ΛΓ Γ 膜的形成順序的流程圖。 = 2Ϊί: 的各步驟中的基體構成的剖面圖。 用的基:包二式所用的基體200 *製造dram時採 單元ί六哭用法形成的記憶單元主要部分201，還帶有 早兀電谷為用下部電極21〇。記憶單元主|邱八 疋" 板202、設在P型石夕基板2〇2的裏處1刀^ iLnf 2〇2a'^^p ir i成rPwJT其 1=tion:淺槽絕緣）203及N型紐區域綱、 =塞:二層t、由料高熔點金屬製成的位元線 205、門雷分201中’N型擴散區域2〇4、間絕緣膜 在兮二：一 ± j冓成早凡電晶體。單元電容器用下部電極21〇設 201的上層，下㈣極藉由接觸插塞 域204連接。爲了盡可能地增大電容器的容量， 邛電極21G由HSG構成’形成在單元電容器用深孔211内。 圖I和3所示’本實施方式中的最初步驟是對基體200進 =鼠化處理’在下部電極21〇上形成薄魏化膜212的熱氮化 〔驟（气驟sioi)。該步驟也稱爲RTN(Rapid Thermal馳—： 、，速熱氮化）’在750°C的氨環境下對基體進行][分鐘左右的退 、，在基體200表面上形成lnm左右的矽氮化膜（si3N4)。在後 9 上315087 述的電漿氧化過程中，矽氦化 離膜的作用。 〜、有防止下部電極210氧化的隔 如圖4所示，下一個㈣ 膜的非晶質金屬氧化物介電膜2lf ==上形成構成電容絕緣 實施方式中，利用CVD法=成膜步驟（步驟麗）。本 物介電膜213a。作爲此時的二^化作爲金屬氧化 鈕（PET)，在43(rc左右 ^採用金屬有機物五乙氧基 右的非晶質氧化紐臈。 度條件下堆積，形成厚5〜2〇贈左 度的溫度(ί驟=====電獏213a的結晶溫 的第-熱處理步驟（步驟間）加熱基體2〇0 Plasma Oxidation :遠端電將4各、以二驟且知用处0 ( Rem〇te 經遠端生成的賴活化彳&能級氧錢縣體置於 氧化賴在含氧的環境下退火時ϋ中’從而使非晶質的 中進入碳質，這成爲漏電流ί成、因^;f晶質氧她膜 該雜質，可改善氧化_的質量。成®由於藉由氧化除去 晶溫度的溫度 =)速熱=在==處理裝置心= 秒左右，使i日:C左右的含氧環境下退火60〜180 鐘就夠了，“數十分$。…曰化。另外’此時的加熱時間1分 (第:溫:於金屬氧化物介電臈的結晶溫度的溫度 處理步驟ΐ的時“i°二:驟予步緩 第二熱 付夕的_使▲度逐漸下降，_加熱基體。因此，制與= 1315087 的加關構，在第二減畔聽鱗，從快速 'rH置中取出基體，放人緩冷用擴散爐，執行新的埶。、 * %的緩冷時間應爲6〇〜廳分鐘，宜爲80分鐘 ’、，、了。 始溫度（第三溫度）宜爲680〜73(TC，更宜爲700。，。 以1.5°C/分鐘的比率從7〇〇〇c下降到6〇〇〇c :、 、表、令時且 ’宜在氧氣環境下進行第三熱處理步驟 2ιΓ的雜辟了，辟私^膜 環二、L -ill 士傷亥膜的質量會惡化’與此相對，在含氧 Ϊ境下封該步驟時，既能維持介賴的質量，又能提高tREF ί 圖6是更詳細地表示第三熱處理步驟的順序圖。 如圖6所示，在第三熱處理步驟中，首先將 預熱到300度的擴散爐内（職）二過Hi step, heating the metal oxide dielectric film = 3 and then 're-smoothing through the third heat than the first and second heat treatments ί' 低于 lower than the specified temperature of the third temperature The third heat treatment step is preferably carried out under an oxygen atmosphere. The heating in the heat treatment step of 180 ί 中 ί ί ί 宜 宜 宜 宜 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 缓 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理 热处理Preferably, the third temperature in the heat treatment step of 600 to (4) is == _ 〇, and the third ί ί Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ Ϊ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The step ί before the film forming step preferably includes thermally nitriding the substrate. In the present invention, the second heat treatment step is preferably a rapid heat treatment. The third heat treatment step is preferably a furnace. σ",, 8 1315087 = metal emulsion dielectric enthalpy, at the same time can reduce the junction leakage current; ^ = quality film can be used to improve DRAM _ "special = (= [implementation] below ^ 照 off DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is a flow chart showing a preferred embodiment of a semiconductor memory device, that is, a flow chart of the formation of a dry Ii-闽ΛΓ film of FIGS. 2 to 5; = 2Ϊί: A cross-sectional view of the substrate in the step. The base used is: the base 200 used for the package type 2 * The main part 201 of the memory unit formed by the use of the unit is formed by the rushing unit, and the lower electrode 21 is also used for the early electrode. 〇. Memory unit main|Qiu Baqi" board 202, set in the P-type Shixi substrate 2〇2 in the 1 knife ^ iLnf 2〇2a'^^p ir i into rPwJT its 1 =tion: shallow slot insulation 203 and N-type New Zealand area, = plug: two layers t, the bit line 205 made of high-melting-point metal, the 'N-type diffusion area 2〇4, and the interlayer insulating film in the gate group 201. A ± j 冓 into an early crystal. The unit capacitor lower electrode 21 is provided with an upper layer 201, and the lower (four) pole is connected by a contact plug field 204. In order to increase the capacity of the capacitor as much as possible, the ytterbium electrode 21G is formed of HSG' formed in the deep hole 211 for the unit capacitor. The first step in the present embodiment shown in Figs. 1 and 3 is the thermal nitridation of the thin-dimension film 212 formed on the lower electrode 21 of the substrate 200. This step is also called RTN (Rapid Thermal-:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Film (si3N4). In the plasma oxidation process described in the last 9 of 315,087, the effect of deuteration is removed. 〜 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成Step Li). The dielectric film 213a. As a metal oxide button (PET) at this time, an amorphous oxidized neodymium with a metal organic compound pentaethoxy right is used at 43 (circle rc), and it is deposited under a condition to form a thickness of 5 to 2 〇. The temperature of the temperature (the temperature of the crystallization temperature of the electrode 213a) - heat treatment step (between steps) heating the substrate 2 〇 0 Plasma Oxidation: the remote power will be 4, with two steps and know 0 (Rem 〇te is generated by the remotely-developed yttrium-activated yttrium-energy-level oxygen-doped body. The oxidized lanthanum is oxidized in an oxygen-containing environment, thereby causing amorphous into the carbonaceous material, which becomes a leakage current. Because of the crystallized oxygen, the impurity of the film can improve the quality of the oxidation _. The temperature of the crystallization is removed by oxidation. =) The rapid heat = at the == treatment device heart = seconds, so that i: Annealing 60 to 180 minutes in an oxygen-containing environment around C is enough, "a few ten dollars.... 曰化. In addition, the heating time at this time is 1 minute (the temperature: the crystallization temperature of the metal oxide dielectric enthalpy) The temperature processing step ΐ "i ° two: the second step is to delay the second heat payment _ to make the ▲ degree gradually decrease, _ heat the substrate. Therefore, with the = 1315087 plus Closed, in the second reduction, listen to the scales, take out the base from the fast 'rH center, let the slow cooling use the diffusion furnace, and execute the new 埶. * * The slow cooling time should be 6 〇 ~ hall minutes, preferably 80 minutes ',,,. The starting temperature (third temperature) should be 680~73 (TC, more preferably 700., drop from 7〇〇〇c to 6〇〇〇 at a rate of 1.5°C/min. c :, , table, order and 'the third heat treatment step 2 Γ 宜 氧气 氧气 氧气 氧气 氧气 氧气 氧气 氧气 氧气 氧气 氧气 氧气 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三In the oxygen-containing atmosphere, the step of sealing the step can maintain the quality of the intervening and increase the tREF. Figure 6 is a sequence diagram showing the third heat treatment step in more detail. As shown in Fig. 6, in the third heat treatment step. First, preheating to 300 degrees in the diffusion furnace
擴的預熱溫度穩定在靴_)，並使擴H =的溫度反覆過衝及下衝，逐漸 而 止放置10分鐘（S604)，椎又至700C爲 基體200約暴露5分鐘# (S6〇 f疋在700 C的溫度條件下，使 緩A是以丨VP /後（S⑹5 ’開始實際的緩冷（S606)。 敎好從7〇〇°C降至_而進行加 後（S6〇8) ’取出基體綱（_)，第三熱處理 在第二熱處理步驟後進行緩冷處理， 使存在於接面周邊的重金屬奸塑 處理’ 雜物吸附在包含多個結晶«活化’可使該 面漏電流，提高卿雜 ^ 00场紙上’因此可降低接 程序最i麵找成轉败絲㈣製造處理 串熱處理後的金屬氧化物 1315087 S綾C(TiN)或氮化鎢(WN)那樣的金屬膜堆積在電 . 上，再藉由光微影及钱刻對金屬膜進行圖案化。此 ί造極214的表面上形成卿_215,完成二連串的The expanded preheating temperature is stabilized in the shoe _), and the temperature of the expanded H = is overshooted and undershooted, and gradually placed for 10 minutes (S604), and the vertebra is again exposed to the substrate 200 for about 5 minutes. # (S6〇 f疋 Under the temperature condition of 700 C, let the slow A start the actual slow cooling with 丨 VP / after (S(6) 5 ' (S606). 敎 从 从 〇〇 〇〇 〇〇 〇〇 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ) 'Remove the matrix (_), the third heat treatment is subjected to a slow cooling treatment after the second heat treatment step, so that the heavy metal is present in the periphery of the joint, and the debris is adsorbed in the inclusion of a plurality of crystals «activation" to make the surface leak The current is increased on the 00 field paper. Therefore, the most unfinished surface of the process can be reduced. (4) The metal oxide 1315087 S绫C (TiN) or tungsten nitride (WN) after the heat treatment is processed. The film is deposited on the electricity, and the metal film is patterned by photolithography and money. The surface of the electrode 214 is formed into a _215, which completes a series of
V 用本實施方式，可改善非晶f金_«^| 再經過結晶化後’在含氧環境下緩冷而加敎，因 金屬氧化物介電膜的可靠性’又能降低漏電流。特別 介電臈結晶化後，實施緩冷處理，因此不會 =if物介電膜和產生結晶缺陷所導致的膜質量低下 性因此既可維持電容絕賴的可靠性，又能提高dra& 進行ίίϊϊ限Γΐ實施对，在不脫離本發明宗旨的範圍内可 ，不用說，廷些改變也包含在本發明的範圍内。 行實施方式中，雖係就处〇 (遠端電漿氧化）下執 步驟的情況說明之’但本發明不限於此，也可以例 σ，、第一熱處理步驟同樣地於RTO下進行。 實施例1 的準^00個作爲金屬氧化物介電臈的採用氧化组(Ta〇) 至第一^己品#1。經過該熱氮化步驟、成膜步驟、第一 膜tiff f 的介電㈣氮化 ίϊί ί，’金屬氧化物介電朗厚度爲川邮。第一熱處理 中'在78(ΓΓ^°^^，環境下加熱基體60秒，第二熱處^步驟 在1 加絲體120秒，第三熱處理步驟卜 在4¼境下加熱基體i小時2〇分鐘 從700t至600t均勻地變化。 …犯使加熱孤度 樣。較別準備與佩以記憶單元樣品#1相同數量的 = ^單元樣品#2除了在第三熱處理步驟中採 用氮_境這-點以外，以與DRAM記憶單元樣品#1同樣的條件 12 1315087 ^成，dram記憶單元樣品# 有的處理程序形成介電膜。 Γ弟二熱處理步驟，僅藉由現 接者測定該DRAM記情置^ 4装V With this embodiment, it is possible to improve the amorphous f gold _«^| after crystallization, and then slowly cool in an oxygen-containing atmosphere to increase the leakage current due to the reliability of the metal oxide dielectric film. After the special dielectric crystallization, the slow cooling treatment is carried out, so that the film quality is not reduced due to the dielectric film and the occurrence of crystal defects, so that the reliability of the capacitor can be maintained, and the dra& It is to be understood that the scope of the present invention is not limited, and it is needless to say that modifications are also included in the scope of the present invention. In the embodiment, the description is made in the case where the step is performed (distal plasma oxidation). However, the present invention is not limited thereto, and σ may be exemplified, and the first heat treatment step is similarly performed under RTO. The 00 of the first embodiment as the metal oxide dielectric enthalpy is used in the oxidation group (Ta〇) to the first product #1. After the thermal nitridation step, the film formation step, and the dielectric (tetra) nitriding of the first film tiff f, the metal oxide dielectric thickness is Chuan Mail. In the first heat treatment, the substrate is heated at 78 (ΓΓ^°^^, environment for 60 seconds, the second heat is stepped at 1 wire for 120 seconds, and the third heat treatment step is heated at 41⁄4 for 1 hour. The minute changes uniformly from 700t to 600t. ...the heating isolating sample. It is prepared to be the same amount as the memory unit sample #1 = ^ unit sample #2 except that in the third heat treatment step, nitrogen is used. In addition to the point, in the same condition as the DRAM memory cell sample #1, 12 1315087, the dram memory cell sample # has a processing procedure to form a dielectric film. In the second heat treatment step, the DRAM is only measured by the presenter. Set ^ 4
持特性。“1，’ f訊保持特性表示將至#3各自的“1’’資訊保 後，該資訊消減了多少。換士^寫ADRAM記憶單元中 特性。 、^ 卩表示DRAM記憶單元的iREF 性的測定結表。^的T資訊保持特 不是實際的時間，是標準化的值訊保持時間t (但是 品的良品率（％)。 、，軸表示DRAM記憶單元樣 由圖7可知，满足〇 5的样〇 & A 妁至#3越過（夕,,7 )卜〇 5 的良品率為綱％，全部樣品 t=4.5^ ^tREF^ 了 1口口口#1至#3的良品率為〇%。 處理的樣跳，當t=2.5時°，^目行緩冷 環㈣行緩= 意，在氧氣品率爲約32%。特別應該注 品。乳m鼠乳狄下進仃緩冷處理時，存在t最大長1〇的樣 是在結果可知，結晶化步驟後進行緩冷處理，無論 理===是機棘了輯，卿進行緩冷處 姓面測‘定該DRAM記憶單元樣品#1至#3各自的“G”資訊保 =性。“0”資訊保持特性也被稱爲ACL (All Cell Low)特性， 表不由電料電触起的記鮮元的;ϊ；良品產生數，是構成電容 絕^的可靠性的指標。測定“G，，資訊保持特性時，改變施加在 ^部電極上的電壓，同時在形成有規定數量的DRAM記憶單元的 晶片上的所有記憶單元中進行零寫入，此後確認各記憶單元的動 13 1315087 作，求出一個晶片上的記憶單元的不良品產生數。 圖8是表示DRAM記憶單元樣品#1細的“ ===的量平均另::圖表中的標繪點‘片; 由圖8可知’ DRAM記憶單元樣品#1至#3都 小時’記憶單元的不良品產生數二=著 ΐΚΪίίΐίΐ的樣品#2與不進行緩冷處理的樣跳^ 產生數大巾自增加。另—方面，在魏環境下進行緩冷 的樣品#1的不Μ產生數只❹量增加 處 品#3相比，不良品產生數減少。 候攸冷處理的樣 根據酬定結果，在氮氣環境獨行緩冷處料與 ίί緩ΐ處理時相比’不良記憶單元增加’電容絕緣膜的ΐί性 ΐ 口Hi目氣環境下進行緩冷處理時，可形成比現有 生un的m質更好的電减緣膜，提高電容絕緣麟可靠性。 下面測定該DRAM記憶單元樣品#1至#3各自的ΜΒτ iM〇nit〇red Bum_in Test :監視老化測試）特性。MBT特性是一 測試，即在-定加速條件τ暴露DRAM#^的結果，測試 產生夕外良^。岐MBT特性時，在腦。⑽溫度條件下，對 ^絕緣酿加14MV/em _場爐2辦後，顧DRAM記 ’二单元樣品的各記憶單元的動作，求出不良品產生數。對此時正 ¥的樣品再進行MBT測試，反覆進行多次ΜβΤ測試，求出各次 測試時的不良品產生數。 圖^9表不DRAM記憶單元樣品#1至#3的MBT特性的測定結 ，:在該圖表中’橫轴表示ΜΒτ測試的反覆次數，縱軸表示記憶 早元的不良品產生數。 由圖9可知’第一次mbt測試時，樣品#1至#3的不良品產 14 1315087 生數4乎相同’但第二次以後，樣品#1的不良品 °μβτ ,,,--f-ί =都冷二進 在早期不收斂 収而逐_少，不良品產生數 根據以上測定結果，在氧氣環境 緩冷處理時、完全不進行緩冷處丁;a=時 生數可在彻伙，製成的dram轉少，可。不良°°產 【圖式簡單說明】 圖1係顯示半導體記憶裝置的製造處 圖2係不思顯不基體構成的剖面圖。 ^係示意顯示減化步射的基體構成的剖面 成严步驟中的第一基體構成的剖面圖。 體構顯示半導體記憶裝置的製造處理完成後得到的基 圖6係顯示第三熱處理步驟的詳細情況的順序 性記憶單元的“rf訊保持特性_特 性記憶單元的“0”資訊保持特性⑽特 圖9係表示DRAM記憶單元的Mbt特性的測定結果的圖表。 【主要元件符號說明】 200基體 201記憶單元主要部分 15 1315087 202 P型矽基板 202a多晶矽層 203 STI (淺槽絕緣） 204 N型擴散區域 205 閘絕緣膜 206 閘電極 207 接觸插塞 208 層間絕緣膜 209 位元線 210 下部電極 211 單元電容器用深孔 212 薄矽氮化膜 213 電容絕緣膜 213a非晶質金屬氧化物介電膜 214 上部電極 215 層間絕緣膜Holding characteristics. The “1,’ f message retention feature indicates how much the information will be reduced after the “1’’ information of #3 is maintained. Change the character of the ADRAM memory unit. , ^ 卩 indicates the measurement table of the iREF of the DRAM memory unit. ^T information retention is not the actual time, it is the standardized value retention time t (but the product yield rate (%).,, the axis indicates the DRAM memory unit sample. As can be seen from Figure 7, the sample 〇5 is satisfied & A 妁 to #3 crossed (X,, 7) The yield of the 〇5 was as follows, all samples t=4.5^ ^tREF^ The yield of the mouth 1# to #3 was 〇%. Jump, when t = 2.5 °, ^ eye line slow cooling ring (four) line slow = meaning, the oxygen rate is about 32%. In particular, should be injected. Milk m mouse milk Ding into the 仃 slow cooling treatment, there is t The maximum length of 1 是 is that the results show that the crystallization step is followed by slow cooling treatment, regardless of the rationality === is the machine spine, the Qing is in the slow-cooling place name test 'determine the DRAM memory unit sample #1 to #3 The respective “G” information guarantees the sex. The “0” information retention feature is also called the ACL (All Cell Low) feature, which is not recorded by the electric material; ϊ; the number of good products is the capacitance An indicator of the reliability of the device. When measuring "G, the information retention characteristic, the voltage applied to the electrode is changed, and a predetermined number of DRAM memory cells are formed. Zero writing is performed in all the memory cells on the wafer, and thereafter, the movement 13 1315087 of each memory cell is confirmed, and the number of defective products in the memory cell on one wafer is obtained. Fig. 8 is a view showing that the DRAM memory cell sample #1 is thin. The average of === is another:: the plot point in the graph is 'chip; from Fig. 8, the 'DRAM memory unit sample #1 to #3 are all hours' memory unit defective product generation number two = ΐΚΪ ίίΐίΐ sample #2 Compared with the sample which does not perform the slow cooling treatment, the number of large towels is increased. On the other hand, the number of samples that are slowly cooled in the Wei environment is increased by only the amount of the product #3, and the defective product is produced. According to the reward result, the sample of the cold treatment in the nitrogen environment is slower than the ' ΐ ' ' 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 不良 Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi Hi In the cold treatment, an electric reducing film is formed which is better than the existing mass, and the reliability of the capacitor insulating lining is improved. Next, the ΜΒτ iM〇nit〇red Bum_in Test of the DRAM memory cell samples #1 to #3 is measured: Monitor aging test) characteristics. The MBT characteristic is a test, that is, the result of exposing DRAM#^ in the -set acceleration condition τ, and the test produces a good evening. When the MBT characteristics are in the brain. (10) Under temperature conditions, after the 14 MV/em _ field furnace 2 was insulated, the number of defective products was determined by the operation of each memory cell of the DRAM. At this time, the sample of the ¥ was subjected to the MBT test, and the ΜβΤ test was repeated several times to determine the number of defective products at each test. Fig. 9 shows the measurement of the MBT characteristics of the DRAM memory cell samples #1 to #3. In the graph, the horizontal axis represents the number of times the ΜΒτ test is repeated, and the vertical axis represents the number of defective products in which the memory is early. It can be seen from Fig. 9 that in the first mbt test, the number of defective products 14 1315087 of samples #1 to #3 is the same as the same 'but after the second time, the defective product of sample #1°μβτ , ,, --f -ί = Both cold and cold in the early stage do not converge and _ less, the number of defective products is based on the above measurement results, in the oxygen environment slow cooling treatment, no slow cooling at all; a = hourly number can be in the group , made dram turn less, can.不良 ° ° 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 。 。 。 。 。 。 。 。 。 。 。 ^ is a cross-sectional view of the first substrate formed in the step of forming the substrate of the reduced step. The base map 6 obtained after the manufacturing process of the semiconductor memory device is completed shows the "rf signal retention characteristic _ characteristic information retention unit "0" information retention characteristic (10) of the sequential memory unit showing the details of the third heat treatment step. 9 is a graph showing the measurement results of the Mbt characteristics of the DRAM memory cell. [Description of main component symbols] 200 substrate 201 Memory cell main portion 15 1315087 202 P-type germanium substrate 202a polysilicon layer 203 STI (shallow trench insulation) 204 N-type diffusion region 205 gate insulating film 206 gate electrode 207 contact plug 208 interlayer insulating film 209 bit line 210 lower electrode 211 deep hole of unit capacitor 212 thin germanium nitride film 213 capacitor insulating film 213a amorphous metal oxide dielectric film 214 upper Electrode 215 interlayer insulating film
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