CN1862778A - Forming method of metal oxide testa film and producing method of semiconductor storage - Google Patents
Forming method of metal oxide testa film and producing method of semiconductor storage Download PDFInfo
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- CN1862778A CN1862778A CN200610079953.7A CN200610079953A CN1862778A CN 1862778 A CN1862778 A CN 1862778A CN 200610079953 A CN200610079953 A CN 200610079953A CN 1862778 A CN1862778 A CN 1862778A
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 68
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 78
- 238000002425 crystallisation Methods 0.000 claims abstract description 29
- 230000008025 crystallization Effects 0.000 claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 230000008569 process Effects 0.000 claims abstract description 19
- 238000010583 slow cooling Methods 0.000 claims description 35
- 239000011159 matrix material Substances 0.000 claims description 30
- 239000012298 atmosphere Substances 0.000 claims description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 28
- 239000001301 oxygen Substances 0.000 claims description 28
- 229910052760 oxygen Inorganic materials 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 13
- JMOHEPRYPIIZQU-UHFFFAOYSA-N oxygen(2-);tantalum(2+) Chemical compound [O-2].[Ta+2] JMOHEPRYPIIZQU-UHFFFAOYSA-N 0.000 claims description 6
- 238000009825 accumulation Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 91
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 3
- 229910007991 Si-N Inorganic materials 0.000 abstract 1
- 229910006294 Si—N Inorganic materials 0.000 abstract 1
- 238000001816 cooling Methods 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 22
- 230000014759 maintenance of location Effects 0.000 description 16
- 238000012360 testing method Methods 0.000 description 11
- 239000012299 nitrogen atmosphere Substances 0.000 description 10
- 238000012545 processing Methods 0.000 description 10
- 238000012797 qualification Methods 0.000 description 9
- 238000005259 measurement Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910001936 tantalum oxide Inorganic materials 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- DJCDXWHFUVBGLR-UHFFFAOYSA-N CCO[Ta] Chemical compound CCO[Ta] DJCDXWHFUVBGLR-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000005300 metallic glass Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
The related manufacture process for metal-oxide dielectric thin film comprises: forming thin Si-N film (212) on lower electrode (210), sedimenting amorphous metal-oxide dielectric film (213a) on the substrate (200) by metal organic predecessor, heating the substrate at temperature less/more than crystallization temperature of (213a) as the first/second heat treatment process, cooling at some third temperature, heating, and finally completing the manufacture.
Description
Technical field
The present invention relates to the formation method of metal oxide testa film and the manufacture method of semiconductor storage, particularly be suitable for forming DRAM (dynamic random access memory) capacitor insulating film metal oxide testa film the formation method and adopt the manufacture method of the semiconductor storage of this method.
Background technology
Preferred tantalum oxide (TaO), the tantalum pentoxide (Ta of adopting
2O
5), titanium dioxide (TiO
2) wait the capacitor insulating film of metal oxide dielectric as DRAM.Generally, by using the heat chemistry evaporation of metallorganic, pile up above-mentioned dielectric film with amorphous state, if use the metallorganic predecessor, then carbon can enter in the metal oxide.Superfluous carbon produces bigger leakage current in metal oxide testa film, have the problem of the function that has reduced dielectric film.
For addressing the above problem, work out the formation method (with reference to patent documentation 1) of following metal oxide testa film.This method is used the metallorganic predecessor, on matrix, pile up amorphous metal oxide testa film, then the temperature (for example 700～750 ℃) with the crystallization temperature that is lower than metal oxide testa film added hot basal body about 60～180 seconds in inert atmosphere, remove carbon superfluous in the noncrystalline metal oxide testa film, temperature (for example 750～850 ℃) with the crystallization temperature that is higher than metal oxide testa film added hot basal body about 60～180 seconds in inert atmosphere again, make its crystallization, and then in oxygen atmosphere, added hot basal body about 30～60 seconds with the temperature (for example 750～850 ℃) that is higher than crystallization temperature, to fill the oxygen room in the polycrystalline metal oxide testa film, prevent to form silicon dioxide layer simultaneously.
Various prior aries related to the present invention (with reference to patent documentation 2～5) are disclosed in addition.
No. the 3211747th, patent documentation 4 special permissions
No. the 3296307th, patent documentation 5 special permissions
Because key property-information retention time (tREF) of DRAM is long more, then refresh rate is low more, can reduce the electric power of consumption, therefore is suitable for portable goods, and high performance memory device can be provided.
Produce leakage current (capacitor leakage current) in the metal oxide testa film though patent documentation 1 disclosed method can be suppressed to a certain extent, can not reduce the joint leakage current.Because the information retention time (tREF) of DRAM not only is subjected to the influence of capacitor leakage current, and be subjected to the influence of the leakage current (joint leakage current) that pn produces between engaging significantly, if therefore fully do not reduce capacitor leakage current simultaneously and engage leakage current, just be difficult to improve the information retention performance of DRAM.
Recently by on the surface of lower electrode, forming the concavo-convex of the silicon that is called as HSG (hemispherical silicon grain), increase capacitor volume, but when forming dielectric film thereon, be easy to generate tiny flaws such as pin hole, even formed normal dielectric film, also can in the processing of back, produce the problem that the dielectric film quality worsens.Therefore, need when keeping the reliability of capacitor insulating film, can further improve the new technology of the information retention performance (tREF characteristic) of DRAM.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of abundant reduction leakage current high-quality metal oxide testa film the formation method and adopt the manufacture method of the semiconductor storage of this method.
For realizing purpose of the present invention, a kind of method that forms metal oxide testa film on matrix is provided, this method comprises following operation: the film formation process of piling up the noncrystalline metal oxide testa film on above-mentioned matrix, in oxygen atmosphere, heat first heat treatment step of above-mentioned matrix with first temperature of the crystallization temperature that is lower than above-mentioned metal oxide testa film, in oxygen atmosphere, second temperature with the crystallization temperature that is higher than above-mentioned metal oxide testa film heats above-mentioned matrix, thereby make second heat treatment step of above-mentioned metal oxide testa film crystallization, after the 3rd temperature that above-mentioned matrix is heated to the crystallization temperature that is lower than above-mentioned metal oxide testa film, through than the long time of above-mentioned first and second heat treatment step and three heat treatment step of slow cooling till the set point of temperature that is lower than above-mentioned the 3rd temperature.
For realizing purpose of the present invention, a kind of manufacture method of semiconductor storage is provided, this semiconductor storage comprises cell transistor and the cell capaciator that is connected with the said units transistor, above-mentioned manufacture method comprises that the dielectric film of the metal oxide testa film that forms the lower electrode that covers the said units capacitor forms operation, above-mentioned dielectric film forms operation and comprises following operation: the film formation process of piling up the noncrystalline metal oxide testa film that covers above-mentioned lower electrode, in oxygen atmosphere, heat first heat treatment step of above-mentioned metal oxide testa film with first temperature that is lower than crystallization temperature, in oxygen atmosphere, heat above-mentioned metal oxide testa film with second temperature that is higher than crystallization temperature, thereby make second heat treatment step of above-mentioned metal oxide testa film crystallization, after above-mentioned metal oxide testa film is heated to the 3rd temperature that is lower than crystallization temperature, through than the above-mentioned long time of first and second heat treatment step and three heat treatment step of slow cooling till the set point of temperature that is lower than above-mentioned the 3rd temperature.
Among the present invention, preferred above-mentioned the 3rd heat treatment step carries out in oxygen atmosphere.
Among the present invention, preferably the heating in above-mentioned first and second heat treatment step was carried out 60 to 180 seconds, and the slow cooling in above-mentioned the 3rd heat treatment step was carried out 60 to 100 minutes.
Among the present invention, above-mentioned first temperature in preferred above-mentioned first heat treatment step is 600 to 650 ℃, and above-mentioned second temperature in above-mentioned second heat treatment step is 750 to 800 ℃, and above-mentioned the 3rd temperature in above-mentioned the 3rd heat treatment step is 680 to 730 ℃.
Among the present invention, preferred above-mentioned metal oxide testa film is made of tantalum oxide (TaO).
Among the present invention, preferably before above-mentioned film formation process, also comprise the operation of above-mentioned matrix being carried out hot nitrogenize.
Among the present invention, preferred second heat treatment step is the operation that heats with rapid thermal process apparatus, and above-mentioned the 3rd heat treatment step is the operation that heats with diffusion furnace.
Adopt the present invention, with metal oxide testa film as semiconductor storage a kind of, when being the capacitor insulating film of DRAM, can form the high-quality metal oxide testa film of abundant reduction leakage current, the while can be reduced the joint leakage current.Thereby, can guarantee the reliability of capacitor insulating film, can improve the information retention performance (tREF characteristic) of DRAM simultaneously.
Description of drawings
Fig. 1 is the part of the manufacturing process of expression semiconductor storage, the i.e. flow chart of the formation operation of the metal oxide testa film of the preferred embodiment for the present invention.
Fig. 2 is a sectional view of representing that schematically matrix constitutes.
Fig. 3 is a sectional view of representing that schematically the matrix in the hot nitrogenize operation constitutes.
Fig. 4 schematically is expressed as the sectional view that first matrix in the membrane process constitutes.
Fig. 5 is the sectional view that the matrix that obtains after the manufacturing of schematically representing semiconductor storage is finished dealing with constitutes.
Fig. 6 is the precedence diagram of the details of expression the 3rd heat treatment step.
Fig. 7 is the figure of measurement result of " 1 " information retention performance (tREF characteristic) of expression DRAM memory cell.
Fig. 8 is the chart of measurement result of " 0 " information retention performance (ACL characteristic) of expression DRAM memory cell.
Fig. 9 is the chart of measurement result of the MBT characteristic of expression DRAM memory cell.
Embodiment
Describe preferred implementation of the present invention with reference to the accompanying drawings in detail.
Fig. 1 is the part of the manufacturing process of expression semiconductor storage, the i.e. flow chart of the formation operation of the described metal oxide testa film of the preferred embodiment for the present invention.Fig. 2～Fig. 5 is a sectional view of representing that schematically the matrix in each operation shown in Figure 1 constitutes.
As shown in Figure 2, the used matrix 200 of present embodiment is the matrixes that adopt when making DRAM, comprises the memory cell major part 201 that forms with known method, also has cell capaciator lower electrode 210.Memory cell major part 201 comprises P type silicon substrate 202, be located at the polysilicon layer 202a that plays suction unit (ゲ Star サ イ ト) effect of the vicinity, the inside of P type silicon substrate 202, be formed on STI in the P type silicon substrate 202 (shallow trench isolation: shallow trench insulation) 203 and N type diffusion zone 204, be formed on the gate insulating film 205 on the P type silicon substrate 202, constitute the gate electrode 206 of word line, contact plunger 207, interlayer dielectric 208, bit line 209 of making by refractory metals such as tungsten etc.In the memory cell major part 201, N type diffusion zone 204, gate insulating film 205, gate electrode 206 constitute cell transistor.Cell capaciator is located at the upper strata of said memory cells major part 201 with lower electrode 210, and lower electrode 210 is connected with N type diffusion zone 204 by contact plunger 207.In order to increase capacitor volume as much as possible, lower electrode 210 is made of HSG, is formed on cell capaciator with in the deep hole 211.
As shown in figs. 1 and 3, the initial operation in the present embodiment is that matrix 200 is carried out hot nitrogen treatment, forms the hot nitrogenize operation (step S101) of thin silicon nitride film 212 on lower electrode 210.This operation is also referred to as RTN (rapid thermal nitridation: Rapid Thermal Nitrided), in 750 ℃ ammonia atmosphere matrix is carried out annealing about 1 minute, at the silicon nitride film (Si that forms on matrix 200 surfaces about 1nm
3N
4).In plasma oxidation process described later, silicon nitride film plays the effect of the barrier film that prevents lower electrode 210 oxidations.
As shown in Figure 4, next operation is the film formation process (step S102) that forms the noncrystalline metal oxide testa film 213a that constitutes capacitor insulating film on matrix 200.In the present embodiment, utilize the CVD method for example to pile up tantalum oxide (TaO) as metal oxide testa film 213a.As the unstrpped gas of this moment, adopt metallorganic five ethoxy-tantalum (PET), under the temperature conditions about 430 ℃, pile up, form the noncrystalline tantalum-oxide film about thick 5～20nm.
Next operation is first heat treatment step (step S103) that adds hot basal body 200 with the temperature (first temperature) of the crystallization temperature that is lower than noncrystalline metal oxide testa film 213a through the stipulated time (very first time).This operation preferably adopts RPO (remote plasma oxidation: the remote plasma oxidation).The remote plasma oxidation is that matrix is placed the high oxygen atom of energy level behind long-range generation plasma-activated, thereby amorphous tantalum-oxide film is annealed in oxygen containing atmosphere.The heating-up temperature of this moment is preferably 600～700 ℃, is preferably 60～180 seconds heating time.When it forms, in the noncrystalline tantalum-oxide film, enter impurity such as carbon, this becomes the origin cause of formation of leakage current, owing to remove above-mentioned impurity by plasma oxidation, can improve the quality of tantalum-oxide film.
Next operation is that the temperature (second temperature) with the crystallization temperature that is higher than metal oxide testa film adds hot basal body 200 through the stipulated time (second time), makes second heat treatment step (step S104) of metal oxide testa film crystallization.This operation preferably adopts RTO (rapid thermal oxidation).RTO adopts rapid thermal process apparatus (RTP: quick thermal treatment process), make in the oxygen-containing atmosphere of matrix about 780 ℃ and anneal about 60～180 seconds, make noncrystalline tantalum-oxide film crystallization.In addition, 1 minute heating time of this moment is just much of that, need not tens of minutes.
Next operation is after the temperature (the 3rd temperature) with the crystallization temperature that is lower than metal oxide testa film adds hot basal body 200, through than the long time of first and second heat treatment step and the 3rd heat treatment step (step S105) of slow cooling.The difference of this operation and second heat treatment step is: descend gradually through the time chien shih temperature more much longer than first and second heat treatment step, add hot basal body simultaneously.Therefore, adopt the heating arrangements different, when second heat treatment step finishes, from rapid thermal process apparatus, take out matrix, put into the slow cooling diffusion furnace, carry out new heat treatment with second heat treatment step.The slow cooling time of this moment should be 60～100 minutes, is preferably 80 minutes.And heating beginning temperature (the 3rd temperature) is preferably 680～730 ℃, more preferably 700 ℃.During slow cooling preferably the ratio with 1.5 ℃/minute drop to 600 ℃ from 700 ℃.
Preferably in oxygen atmosphere, carry out the 3rd heat treatment step herein.When in nitrogen atmosphere, carrying out the 3rd heat treatment step, though the tREF characteristic has improved, but the dielectric film that contains silicon nitride film 212 can produce damage, the quality of this film can worsen, relative therewith, when in oxygen-containing atmosphere, carrying out this operation, the quality of dielectric film can be kept, the tREF characteristic can be improved again.
Fig. 6 is a precedence diagram of representing the 3rd heat treatment step in more detail.
As shown in Figure 6, in the 3rd heat treatment step, at first matrix 200 is loaded in the diffusion furnace that is preheating to 300 degree (S601), make owing to the preheat temperature of loading in the diffusion furnace that changes is stabilized in 300 ℃ (S602) through certain hour, and make the temperature in the diffusion furnace rise to 700 ℃ (S603) always.At this moment, because from reaching temperature overshoot and the Xia Chong repeatedly in 700 ℃ the diffusion furnace, convergence gradually, thereby arrive to stablize till 700 ℃ and place 10 minutes (S604), and then be stabilized under 700 ℃ the temperature conditions, after making matrix 200 expose 5 minutes approximately (S605), the slow cooling (S606) that beginning is actual.Slow cooling is to make temperature reduce to 600 ℃ and heat from 700 ℃ with 1.5 ℃/minute ratio.After this, in nitrogen atmosphere, clean diffusion furnace (S607), the temperature in the diffusion furnace is cooled to 300 ℃ after (S608), take out matrix 200 (S609), the 3rd heat treatment step finishes.
Carrying out slow cooling behind second heat treatment step handles, promptly during the 3rd heat treatment step, activate being present in the heavy metal that engages periphery or influencing the impurity that engages destruction, on the polysilicon layer 202a that above-mentioned foreign material are adsorbed on comprise a plurality of crystal defects, therefore can reduce the joint leakage current, improve the tREF characteristic.
Finishing operation in the present embodiment is a manufacturing process (step S106) of finishing semiconductor storage.For example shown in Figure 5, upper electrode 214 is formed on the capacitor insulating film 213 that is made of the metal oxide dielectric after a succession of heat treatment.Specifically, titanium nitride (TiN) or the such metal film of tungsten nitride (WN) are deposited on the capacitor insulating film 213, by photoetching and etching metal film are carried out patterning again.After this, on the surface of upper electrode 214, form interlayer dielectric 215, finish a series of manufacturing process.
As mentioned above, adopt present embodiment, can improve the quality of noncrystalline metal oxide testa film, because after passing through crystallization again, therefore slow cooling in oxygen-containing atmosphere and heating both can keep the reliability of metal oxide testa film, can reduce leakage current again.After particularly making the metal oxide testa film crystallization, implement slow cooling and handle, therefore can not produce impurity pick-up metal oxide dielectric film and produce the low problem of film quality that crystal defect caused.When being applicable to the capacitor insulating film that forms DRAM, can suppress to engage the increase of leakage current, therefore both can keep the reliability of capacitor insulating film, can improve the tREF characteristic of DRAM again.
The invention is not restricted to above-mentioned execution mode, can carry out various changes without departing from the spirit and scope of the present invention, much less, these changes are also contained in the scope of the present invention.
For example explanation is carried out the situation of first heat treatment step by RPO (remote plasma oxidation), but be the invention is not restricted to this in the above-described embodiment, also can for example similarly be undertaken by RTO with second heat treatment step.
At first, prepare 600 DRAM memory cell sample # 1 as the employing tantalum oxide (TaO) of metal oxide testa film.Make the dielectric film of DRAM memory cell sample # 1 through above-mentioned hot nitrogenize operation, film formation process, first to the 3rd heat treatment step.The thickness of silicon nitride film is 1nm, and the thickness of metal oxide testa film is 10nm.In first heat treatment step, in 630 ℃ oxygen-containing atmosphere, added hot basal body 60 seconds, in second heat treatment step, in 780 ℃ oxygen-containing atmosphere, added hot basal body 120 seconds, in the 3rd heat treatment step, in oxygen-containing atmosphere, added hot basal body 1 hour 20 minutes, and during heating, heating-up temperature was changed equably from 700 ℃ to 600 ℃.
As a comparative example, prepare sample # 2, #3 respectively with DRAM memory cell sample # 1 equal number, DRAM memory cell sample # 2 is except adopting the nitrogen atmosphere this point in the 3rd heat treatment step, to make with the same condition of DRAM memory cell sample # 1, DRAM memory cell sample # 3 has omitted the 3rd heat treatment step, only forms dielectric film by existing treatment process.
Then measure above-mentioned DRAM memory cell sample # 1 to #3 " 1 " information retention performance separately.After " 1 " information retention performance was represented to write in the DRAM memory cell with " 1 ", how much this information subdued.In other words, the tREF characteristic of promptly representing the DRAM memory cell.
Fig. 7 is the chart of measurement result of " 1 " information retention performance of expression DRAM memory cell sample # 1 to #3.In this chart, transverse axis is represented information retention time t (but whether actual time be standardized value), and the longitudinal axis is represented the qualification rate (%) of DRAM memory cell sample.
As shown in Figure 7, the qualification rate that satisfies the sample of t=0.5 is 100%, and all sample # 1 to #3 crosses the condition of (Network リ ア) t=0.5, but makes the tREF condition strict gradually, and when reaching t=4.5, all the qualification rate of sample # 1 to #3 is 0%.
In not carrying out the sample # 3 that slow cooling handles, during t=2.5, qualification rate is about 90%, during t=3.5, qualification rate is almost 0%, and is relative therewith, carries out the sample # 2 that slow cooling is handled in nitrogen atmosphere, when t=2.5, qualification rate is about 96%, and during t=3.5, qualification rate is about 21%.Carry out in oxygen atmosphere among the sample # 1 that slow cooling handles, when t=2.5, qualification rate is about 97%, and during t=3.5, qualification rate is about 32%.When should be noted that especially carrying out slow cooling in oxygen or nitrogen atmosphere handles, exist t to greatly enhance 1.0 sample most.
No matter according to above measurement result as can be known, carry out slow cooling after the crystallization step and handle, be to carry out in nitrogen atmosphere or in oxygen atmosphere, and all the information retention performance when not carrying out slow cooling and handle is good.
Measure above-mentioned DRAM memory cell sample # 1 to #3 " 0 " information retention performance separately below." 0 " information retention performance is also referred to as ACL (All Cell Low) characteristic, and the bad generation number of the memory cell that expression is caused by capacitor leakage current is the index that constitutes the reliability of capacitor insulating film.When measuring " 0 " information retention performance, change the voltage that is applied on the upper electrode, carrying out zero simultaneously in all memory cell on the wafer of the DRAM memory cell that is formed with specified quantity writes, after this confirm the action of each memory cell, obtain the bad generation number of a memory cell on the wafer.
Fig. 8 is the chart of measurement result of " 0 " information retention performance of expression DRAM memory cell sample # 1 to #3.In this chart, transverse axis represents to be applied to voltage on the upper electrode (but be not actual voltage, but standardized value), and the longitudinal axis is represented the quantity of a bad memory cell in the wafer.In addition, the plot point in the chart is got the mean value of the bad generation number of the memory cell in each wafer.
As shown in Figure 8, DRAM memory cell sample # 1 to #3 all be when be applied on the upper electrode voltage hour, the bad generation number of memory cell also seldom, but along with the increase that applies voltage, the bad generation number of memory cell also increases, the sample # 2 that wherein carries out the slow cooling processing in nitrogen atmosphere compares with the sample # 3 that does not carry out the slow cooling processing, and bad generation number significantly increases.On the other hand, in oxygen atmosphere, carry out just a small amount of the increasing of bad generation number of the sample # 1 of slow cooling processing, compare bad generation number minimizing with the sample # 3 that does not carry out the slow cooling processing.
According to the said determination result, do not compare when slow cooling is handled with existing not carrying out when in nitrogen atmosphere, carrying out the slow cooling processing, bad memory cell increases, the reliability of capacitor insulating film reduces, relative therewith, when in oxygen atmosphere, carrying out the slow cooling processing, can form, improve the reliability of capacitor insulating film than the better capacitor insulating film of the quality of existing product.
Measure above-mentioned DRAM memory cell sample # 1 to #3 MBT (monitoredburn-in test: monitor ageing test) characteristic separately below.The MBT characteristic is a kind of accelerated test, promptly exposes the result of DRAM sample under certain acceleration environment, tests what samples and takes place bad.When measuring the MBT characteristic, under 100 ℃ temperature conditions, the electric field bias that capacitor insulating film is applied 14MV/cm was confirmed the action of each memory cell of DRAM memory cell sample after 2 hours, obtained bad generation number.At this moment normal sample is carried out the MBT test again, carry out repeatedly the MBT test repeatedly, the bad generation number when obtaining each time test.
Fig. 9 represents the measurement result of the MBT characteristic of DRAM memory cell sample # 1 to #3.In this chart, transverse axis is represented the number of occurrence of MBT test, and the longitudinal axis is represented the bad generation number of memory cell.
As shown in Figure 9, during MBT test for the first time, the bad generation number of sample # 1 to #3 much at one, but for the second time, the difference increase between the bad generation number of sample # 1 and the bad generation number of sample # 2, #3.That is, in for the second time later MBT test, the bad generation number that carries out the sample # 1 of slow cooling processing in oxygen atmosphere significantly reduces, and bad generation number has just been restrained in early days.Relative therewith, it all is that MBT tests and minimizing gradually along with repeating that the sample # 2 that carries out the slow cooling processing in nitrogen atmosphere reaches the sample # 3 bad generation number separately that does not carry out the slow cooling processing, and bad generation number is not restrained in early days.
According to above measurement result, when carrying out slow cooling handle in nitrogen atmosphere, do not carry out not comparing when slow cooling is handled fully, bad generation number can be restrained in early days when carrying out slow cooling handling in oxygen atmosphere, and the DRAM that makes is bad few, the reliability height.
Claims (14)
1. the formation method of a metal oxide testa film is the method that forms metal oxide testa film on matrix, it is characterized in that, comprises following operation:
On described matrix, pile up the noncrystalline metal oxide testa film film formation process,
In oxygen atmosphere, with first temperature of the crystallization temperature that is lower than described metal oxide testa film heat described matrix first heat treatment step,
In oxygen atmosphere, heat described matrix with second temperature of the crystallization temperature that is higher than described metal oxide testa film, thereby make described metal oxide testa film crystallization second heat treatment step and
After described matrix is heated to the 3rd temperature of the crystallization temperature that is lower than described metal oxide testa film, through than the described long time of first and second heat treatment step and three heat treatment step of slow cooling till the set point of temperature that is lower than described the 3rd temperature.
2. the formation method of metal oxide testa film as claimed in claim 1 is characterized in that, described the 3rd heat treatment step carries out in oxygen atmosphere.
3. the formation method of metal oxide testa film as claimed in claim 2 is characterized in that, the heating in described first and second heat treatment step was carried out 60 to 180 seconds, and the slow cooling in described the 3rd heat treatment step was carried out 60 to 100 minutes.
4. the formation method of metal oxide testa film as claimed in claim 3, it is characterized in that, described first temperature in described first heat treatment step is 600 to 650 ℃, described second temperature in described second heat treatment step is 750 to 800 ℃, and described the 3rd temperature in described the 3rd heat treatment step is 680 to 730 ℃.
5. the formation method of metal oxide testa film as claimed in claim 4 is characterized in that, described metal oxide testa film is made of tantalum oxide (TaO).
6. as the formation method of each described metal oxide testa film in the claim 1～5, it is characterized in that, before described film formation process, also comprise the operation of described matrix being carried out hot nitrogenize.
7. the formation method of metal oxide testa film as claimed in claim 6 is characterized in that, second heat treatment step is the operation that heats with rapid thermal process apparatus, and described the 3rd heat treatment step is the operation that heats with diffusion furnace.
8. the manufacture method of a semiconductor storage, this semiconductor storage comprises cell transistor and the cell capaciator that is connected with described cell transistor, it is characterized in that, described manufacture method comprises that the dielectric film of the metal oxide testa film that forms the lower electrode that covers described cell capaciator forms operation, and described dielectric film forms operation and comprises following operation:
The film formation process of the noncrystalline metal oxide testa film of the described lower electrode of accumulation covering,
In oxygen atmosphere, with first temperature that is lower than crystallization temperature heat described metal oxide testa film first heat treatment step,
In oxygen atmosphere, heat described metal oxide testa film with second temperature that is higher than crystallization temperature, thereby make described metal oxide testa film crystallization second heat treatment step and
After described metal oxide testa film is heated to the 3rd temperature that is lower than crystallization temperature, through than the described long time of first and second heat treatment step and three heat treatment step of slow cooling till the set point of temperature that is lower than described the 3rd temperature.
9. the manufacture method of semiconductor storage as claimed in claim 8 is characterized in that, described the 3rd heat treatment step carries out in oxygen atmosphere.
10. the manufacture method of semiconductor storage as claimed in claim 9 is characterized in that, the heating in described first and second heat treatment step was carried out 60 to 180 seconds, and the slow cooling in described the 3rd heat treatment step was carried out 60 to 100 minutes.
11. the manufacture method of semiconductor storage as claimed in claim 10, it is characterized in that, described first temperature in described first heat treatment step is 600 to 650 ℃, described second temperature in described second heat treatment step is 750 to 800 ℃, and described the 3rd temperature in described the 3rd heat treatment step is 680 to 730 ℃.
12. the manufacture method of semiconductor storage as claimed in claim 11 is characterized in that, described metal oxide testa film is made of tantalum oxide (TaO).
13. the manufacture method as each described semiconductor storage in the claim 8～12 is characterized in that, also comprises the operation of described matrix being carried out hot nitrogenize before described film formation process.
14. the manufacture method of semiconductor storage as claimed in claim 13 is characterized in that, second heat treatment step is the operation that heats with rapid thermal process apparatus, and described the 3rd heat treatment step is the operation that heats with diffusion furnace.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005139242A JP2006319077A (en) | 2005-05-12 | 2005-05-12 | Method for generating metal-oxide dielectric film, and method for manufacturing semiconductor storage device |
| JP2005139242 | 2005-05-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1862778A true CN1862778A (en) | 2006-11-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200610079953.7A Pending CN1862778A (en) | 2005-05-12 | 2006-05-11 | Forming method of metal oxide testa film and producing method of semiconductor storage |
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| Country | Link |
|---|---|
| JP (1) | JP2006319077A (en) |
| CN (1) | CN1862778A (en) |
| TW (1) | TWI315087B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185696A (en) * | 2015-09-25 | 2015-12-23 | 上海华力微电子有限公司 | Method of reducing white pixels of CMOS image sensor by polysilicon gettering |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000058789A (en) * | 1998-08-13 | 2000-02-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JP2000068265A (en) * | 1998-08-25 | 2000-03-03 | Japan Storage Battery Co Ltd | Method for annealing oxide insulating film |
| JP2000124417A (en) * | 1998-10-14 | 2000-04-28 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| US6204203B1 (en) * | 1998-10-14 | 2001-03-20 | Applied Materials, Inc. | Post deposition treatment of dielectric films for interface control |
| GB2358284B (en) * | 1999-07-02 | 2004-07-14 | Hyundai Electronics Ind | Method of manufacturing capacitor for semiconductor memory device |
-
2005
- 2005-05-12 JP JP2005139242A patent/JP2006319077A/en active Pending
-
2006
- 2006-04-28 TW TW095115276A patent/TWI315087B/en not_active IP Right Cessation
- 2006-05-11 CN CN200610079953.7A patent/CN1862778A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185696A (en) * | 2015-09-25 | 2015-12-23 | 上海华力微电子有限公司 | Method of reducing white pixels of CMOS image sensor by polysilicon gettering |
| CN105185696B (en) * | 2015-09-25 | 2018-04-06 | 上海华力微电子有限公司 | The method that cmos image sensor white pixel is reduced by polysilicon gettering |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2006319077A (en) | 2006-11-24 |
| TWI315087B (en) | 2009-09-21 |
| TW200727361A (en) | 2007-07-16 |
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