1313505 (1) 九、發明說明 相關申請案： 本申請案爲在2002年1月7日所提出申請之美國專利申 請號第10/036,389號案的部分繼續案，該部分繼續案的揭 示內容在此被倂入當做特定的參考資料。 【發明所屬之技術領域】 在此所揭示之實施例係有關於封裝半導體晶粒來製造 積體電路。 【先前技術】 更高的性能、更低的成本、積體電路組件之持續小型 化和積體電路之更大的封裝密度爲電腦工業之不間斷的目 標。隨著這些目標被達成，半導體晶粒也變得更小，且電 力耗損/密度也變得更高。 通常，對大部分的半導體晶粒來說，由主動（active) 表面所提供之表面積對所有的外部接點而言並未提供足夠 的表面，而足夠的表面對某些類型的半導體晶粒來說係接 觸外部裝置所需要的。能夠利用內插板（interposer) ’例如 ，實質爲剛性材料或者實質爲可撓性材料，來提供額外的 表面積。 由較小的半導體晶粒之製造所產生的一個問題爲半導 體晶粒中之積體電路組件之電力耗損的密度已經增高’其 因而增加了晶粒的平均接面溫度。如果半導體晶粒的溫度 -4 -</ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> This is broken down as a specific reference. TECHNICAL FIELD OF THE INVENTION The embodiments disclosed herein relate to packaging semiconductor dies to fabricate integrated circuits. [Prior Art] Higher performance, lower cost, continued miniaturization of integrated circuit components, and greater package density of integrated circuits are uninterrupted goals for the computer industry. As these goals are achieved, the semiconductor grains become smaller and the power consumption/density becomes higher. In general, for most semiconductor dies, the surface area provided by the active surface does not provide sufficient surface for all external contacts, while sufficient surface is available for certain types of semiconductor dies. Said to be required to contact external devices. An additional surface area can be provided by using an interposer', for example, a substantially rigid material or substantially a flexible material. One problem that arises from the fabrication of smaller semiconductor dies is that the density of power dissipation of the integrated circuit components in the semiconductor dies has increased. This increases the average junction temperature of the grains. If the temperature of the semiconductor die -4 -
I (2) 1313505 變得太高，則可能會傷害或破壞半導體晶粒的積體電路 並且晶片的壽命/可靠度明顯下降。此外，對於相同尺 大小的半導體晶粒來說，整體的電力增加，其顯現出所 加之電力密度的相同問題。 已經使用了各種的設備和技術而自半導體晶粒中去 熱，有些技術涉及使用膠封（encapsulation)材料來膠封 導體晶粒於散熱器（heat spreader)上，或者使半導體晶 φ 嵌入（固定）於散熱器內的凹部（空洞）中以供熱散逸。這 技術的使用產生用來製造積體電路封裝組件之額外、複 . 的處理步驟’並且這些組裝方法的熱性能也受限於材料 • 製程。因此，爲積體電路製造發展新的設備和技術將會 有利的’而這些新的設備和技術消除複雜的處理步驟及 板內插板的需要，並且提供改善的熱散逸。 近似晶粒之材料的熱膨脹係數（CTE)也是一個問題 破壞性的應力由於材料特性的固有本質差異而能夠發生 ® 板與晶粒之間（具有2·6 Ppm/C之CTE的Si及具有 Ppm/C之CTE的基板）’當微電子裝置封裝組件產生顯 的熱時’熱/機械應力問題甚至更嚴重，這也限制了爲 性能裝置所需之低介電常數材料的選擇。 【發明內容及實施方式】 .下面的敘述包含僅係用於敘述性目的而不是被建構 限制之術語’例如，上、下、第一、第二等等。在此 之裝置或物件的實施例能夠以許多的位置或方向來予以 寸 增 除 半 粒 些 雜 和 是 基 〇 在 16 著 高 來 述 製 -5- (3) 1313505 造、使用、或出貨。術語”晶粒”及”處理器”通常指的是爲 基本工件的實際物體，而基本工件係藉由各種的製程操作 而被轉變成爲所想要的積體電路裝置。晶粒經常係自晶圓 中獨立出來，並且晶圓可以是由半導體材料、非半導體材 料、或半導體和非半導體材料之組合所做的。 典型上，板爲一絕緣且當作晶粒之安裝基板用的導 體-覆蓋結構，板經常係從一板陣列中被獨立出來。現在 φ 提到附圖，在附圖中，相似的結構係提供有相似的參考命 名指定。爲了最清楚地顯示此結構和製程實施例，在此所 .包含之圖形係實施例的圖形表示。因此，所製造之結構的 .真正外觀，舉例來說，在縮微照相中，可能出現不同，而 同時仍結合實施例之必要結構。況且，圖形僅顯示出了解 本發明所需要的結構。實施例可以指，單獨及/或共同， 在此僅爲了方便而指術語”發明”，而並非想要志願地將此 揭示之範圍限制於任何單一發明或發明槪念，如果事實上 • 一個以上的發明或發明槪念被揭示。並未包含在此技藝中 所已知的其他結構以便保持該等圖形的清楚。 依據所揭示之實施例，連結於平面散熱器之變薄的半 導體晶粒之構成，並且與基板相結合，產生了積體電路封 裝組件的許多特性。實施例之其中一特性包含散熱器可以 是平面的（相反於不規則、非平面的形狀），這使得製造上 更容易。實施例之另一特性包含相較於”晶粒嵌入於散熱 器中”技術’更容易使晶粒連結於散熱器，這是因爲必需 要沉積材料於空洞之底部中的精確控制，而這對自我對準 -6- (4) 1313505 的焊接方式係特別有利的。實施例之另一特性爲如 技術的情況一樣，不需要將晶粒膠封於散熱器。實 另一特性包含在將Si晶粒連結於有機基板上之前 有凸塊（bump)之變薄的晶粒接合於Cu散熱片上。 之另一特性包含使用具有較高之再熔溫度的薄硬焊 變薄的Si晶粒和Cu散熱器連結在一起。 除此之外，變薄的晶粒減少晶粒/散熱器組合 φ ’以改善自晶粒之排熱。變薄的晶粒也更依順而使 散熱器之熱/機械特性一致地膨脹和收縮，因此減: . 晶粒與Cu散熱器間之介面處之應力誘發的破裂。 . Cu散熱器之強烈的耦合來提高Si之有效的CTE， 與有機基板之間的應力也被顯著地減少。 雖然附圖例舉各種實施例，但是這些圖形並非 確詳細地描繪出積體電路（微電子）封裝組件，而是 圖形以更清楚地傳達所列舉之實施例及其等同之物 φ 來例舉積體電路封裝組件。除此之外，在此等圖形 同的元件可以保留相同的數字命名指定。 實施例包含一封裝技術，即，將一或多個變薄 體（微電子）晶粒置於平面的散熱片（heat sink)上’ 由硬的黏著性熱介面材料來將半導體晶粒固定於影 。在一實施例中，晶粒可以使用黏著材料（例如， ’料）而被連結於散熱片’也可以使用形成接合於晶 熱片之間的替換方法。 這些實施例致使積體電路封裝組件能夠被建 同其他 施例之 ，使具 實施例 劑來使 之熱阻 得其與 少在Si 有了與 Si晶粒 打算精 ，這些 的方式 間之共 的半導 並且藉 熱片上 焊劑材 粒與散 :在變薄 -7- (5) 1313505 的半導體晶粒的附近。依據一實施例，當晶粒係非常地薄 且封裝組件需要更小的散熱片，此組態也導致更薄的尺寸 外型（form factor)。 圖1爲依據實施例之晶片封裝組件100的剖面圖。描述 在變薄的晶粒110之正面（主動面）被接合於基板116(例如 ’有機內插板）之前，變薄的晶粒11 0係以熱介面材料 (TIM)112而被接合於散熱片114。互連結構117，係在變薄 φ 的晶粒110之正面上，經由一連串的電凸塊而被耦接至基 板116，電凸塊的其中一個係以參考數字118來予以命名指 ，定。 . 在一實施例中，變薄的晶粒110具有範圍從約20微米 (μπ〇到約150 μιη的厚度120。在一實施例中，變薄的晶粒 1 10具有範圍從約80μηι到約120μιη的厚度120。在一實施 例中’變薄的晶粒1 10具有範圍約ΙΟΟμπι的厚度120。在一 實施例中，變薄的晶粒110具有不超過約1〇〇 μιη的厚度120 φ 。在一實施例中，變薄的晶粒110具有少於約ΙΟΟμιη的厚 度 120。 在一實施例中，TIM 112具有範圍從約Ο.ίμιη到約 50μιη的介面厚度（BLT)122。在一實施例中，TIM 112具有 範圍從約〇·5μπι到約40μιη的 BLT 122。在一實施例中， TIM 1 12具有範圍從約Ιμπι到約30μπι的BLT 122。在一實 " 施例中’ TIM 112具有範圍從約2μηι到約20μπι的BLT 122 '。在一實施例中，TIM 112具有範圍從約5μπι到約ΙΟμιη的 BLT 122。在一實施例中，TIM 112具有約6μιη的BLT 122 1313505 ⑹ 圖1也例舉依據各種實施例，被使用來製造積體電路 封裝組件100的散熱片114，散熱片114包含一實質爲平面（ 平坦）、高度熱傳導材料以去除散逸於變薄的晶粒110中的 熱。 在一實施例中，被使用來製造散熱片114的材料包含 金屬，例如，銅、包含具有鎢之銅合金的銅合金' 銅疊層 ^ 、銅金剛石（copper diamond)、包覆之銅結構、其組合等 等。在一實施例中，被使用來製造散熱片114的材料包含 .鉬、鉬疊層、鉬合金、包覆之鉬結構、其組合等等。在一 .實施例中，被使用來製造散熱片114的材料包含鋁、包含 金屬化之氮化銘的錯合金、銘金剛石（aluminum diamond) 、包覆之鋁結構、其組合等等。氮化鋁可以用鉻/金、鈦/ 金、或鎳/金膜來予以金屬化。在一實施例中，被使用來 製造散熱片114的材料包含氧化鈹等等。在一實施例中， • 被使用來製造散熱片114的材料包含碳纖維、石墨、金剛 石、其組合等等。在一實施例中，被使用來製造散熱片 11 4的材料包含（但並非限定於）熱傳導陶瓷材料，例如， AlSiC, A1N 等等。 選擇散熱片114之材料的熱膨脹係數（CTE)來使在變薄 的晶粒110中之應力誘發的破裂最小化，特別是在晶粒上 ^ 及凸塊118中之互連117處之晶粒112的邊緣。舉例來說， '藉由緊密地使散熱片114材料（例如，AlSiC)之CTE匹配於 矽，可以減少應力誘發的晶粒破裂之事件。舉例來說，藉 -9- (7) 1313505 由使散熱片材料114之CTE與有機內插板116(例如，Cu) 相匹配，可以減少互連117與電凸塊118之間的應力。在用 於變薄的晶粒110之實施例中，散熱片II4係由失配於矽之 較大的CTE但並未導致應力誘發的晶粒破裂之材料（例如 ，銅）所做的。又，散熱片114能夠由具有與基板116緊密 匹配之CTE的材料所做的，而變薄的晶粒110可以被置於 基板116上以供操作（例如，電腦之中央處理單元（CPU))。 變薄的晶粒110之薄度使其與散熱片114之熱誘發的尺寸改 變一致。 在一實施例中，變薄的晶粒110爲形成物件之封裝組 件100的一部分，該物件包含散熱片114，而散熱片114包 含係根據其材料和構造之模式的散熱片-特性CTE。變薄 的晶粒110包含晶粒-特性CTE。TIM 112使變薄的晶粒110 接合於散熱片，並且構成該物件的一個實施例而沒有基板 116。因爲如同在此揭示中所提出之變薄的晶粒11〇之厚度 ，變薄的晶粒11 0包含大於晶粒-特性CTE的晶粒-有效 CTE。換言之，晶粒-有效CTE實質上和散熱片-特性CTE 匹配。 在一實施例中，爲封裝組件100之一部分的該物件包 含比晶粒-特性CTE還大從約2倍的約5倍之範圍中的晶粒-有效CTE。在一實施例中，正確的晶粒-有效CTE實質上 和散熱片-特性C T E匹配。在一實施例中，晶粒-有效C T E 係在從約10 ppm/°C到約17 ppm/°C之範圍中。在一實施例 中，晶粒-有效CTE爲約16.2ppm/°C。 -10- (8) 1313505 圖2A係依據實施例，在處理期間，晶片封裝組件200 的剖面圖。晶片封裝組件200表示在組裝期間的中間結構 。變薄的晶粒210，其包含在此揭示中所提出之薄度實施 例的各者，被描述成係以熱介面材料（TIMs)211而被組裝 於散熱片214。 在晶粒210被接合於散熱片214之前，依據一實施例來 使晶粒210變薄。依據一實施例，根據例如硏磨、化學機 φ 械磨光、電漿蝕刻之各種技術的一或多者、或其他的技術 來使晶粒2 1 0的厚度減小。在一實施例中，使用化學蝕刻 .來使晶粒210的厚度減小。在一實施例中，使用硏磨來使 .晶粒21 0的厚度減小。在一實施例中，使用上述技術的任 何兩個來使晶粒21 0的厚度減小。在一實施例中，使用上 述技術的任何三個來使晶粒210的厚度減小。在一實施例 中，使用所有的上述技術來使晶粒210的厚度減小。 在一實施例中，散熱片2 14實質上爲銅。在一實施例 φ 中，TIMs 211包含一置於散熱片214上的鎳包覆層23〇、一 置於該鎳包覆層230上的金層232、及一置於該金層232上 的錫層2〗4。在一實施例中，TIMs 21 1包含一置於變薄的 晶粒210上之鈦包覆層224、一置於鈦包覆層224上之鎳-釩 層226、及一置於鎳-釩層226上之金底層228。 層厚度的選擇包含考慮和圖1所描述之BLT 122有關 ，的最終BLT。在一實施例中’散熱片214實質上爲銅。在 — —實施例中’鎳包覆層230係在從約〇·〇5μιη到約〇.6μπι的 厚度範圍中。在一實施例中’鎳包覆層230係在從約 -11 - (9) 1313505 到約〇·45μιη的厚度範圍中。在一實施例中，鎳包覆層230 爲約0·3μιη。在一實施例中，金層232係在從約〇·5μπι到約 6μιη的厚度範圍中。在—實施例中，金層232係在從約 1卜111到約4111的厚度範圍中。在一實施例中，金層232爲 約3 μιη。在一實施例中，錫層234係在從約〇.〇5 μιη到約 〇·6μηι的厚度範圍中。在一實施例中，錫層23 4係在從約 Ο.ίμηι到約〇·15μιη的厚度範圍中。在一實施例中，錫層 234 爲約 〇.3μιη。 在一實施例中，鈦包覆層224係在從約〇·〇5μπι到約 0·2μιη的厚度範圍中。在一實施例中，鈦包覆層224係在 從約0.075 μιη到約0.15 μιη的厚度範圍中。在一實施例中， 鈦包覆層224爲約0.1 μιη。在一實施例中，鎳·釩層226係在 從約0.05μιη到約〇.6μιη的厚度範圍中。在一實施例中， 鎳-釩層226係在從約0.1 μιη到約0.1 5 μιη的厚度範圍中。在 一實施例中，鎳-釩層22 6爲約0.3 μιη。在一實施例中，金 底層228係在從約0.05μπι到約0·2μιη的厚度範圍中。在一 實施例中，金底層228係在從約0.075μιη到約0.15μιη的厚 度範圍中。在一實施例中，金底層228爲約Ο.ίμιη。 在一實施例中，散熱片214實質上爲銅，鎳包覆層230 爲約3μιη，金層232爲約3μιη，錫層234爲約3μπι，鈦包覆 層224爲約Ο.ίμηι，鎳-釩層226爲約〇·3μπι，以及金底層228 爲約 0.1 μιη。 圖2Β係依據實施例，在進一步處理期間，圖2Α所描 述之晶片封裝組件200的剖面詳細圖，此剖面詳細圖係取 -12 - 1313505 no) 自圖2A中的選擇線2B，並且已經使圖2A中之晶片封裝組 件200匯集在一起。晶片封裝組件201被描述爲包含TIM 212之接合的物件，圖2例舉以黏著劑（TIM)212而被連結（ 安裝）於散熱片214的單一變薄的晶粒210。在一實施例中 ，熱壓機（例如，熱壓焊接機、回焊爐）被用來使變薄的晶 粒210連結於散熱片214。 有了幾個 TIM實施例，實施無助熔劑接合程序。舉 φ 例來說，以銅散熱片214和實質爲矽之變薄的晶粒210來實 施無助熔劑接合程序，變薄的晶粒210爲約50μιη厚，並且 .當完成接合時，TIM 212爲約6μπι。在無助熔劑接合程序 .中，鈦包覆層224爲約Ο.ΐμπι，鎳-釩層226爲約0.3μιη，且 金底層228爲約Ο.ίμιη。除此之外，在無助熔劑接合程序中 ，鎳包覆層230爲約3μπι，金層232爲約3μιη，且錫層234爲 約3μιη。藉由熔解錫層234於其固相溫度（TSQlidusSn)，並且 進一步加熱來實施接合。在一實施例中，藉由用於，例如 φ 鈦及/或鉻與矽之習於此技藝者一般所知之瞬間晶片連結 程序來實施接合，但是接合程序被應用做爲此揭示之變薄 的晶粒處理實施例的一部分。 TIM 212讓熱藉由傳導而從變薄的晶粒210被轉移至散 熱片214。在一實施例中，TIM 21 2包含一金-錫-鎳區236 ，其係藉由熔合部分的鎳包覆層23 0、金層23 2、錫層23 4 、鎳-釩層226、及金底層228。雖然金-錫-鎳區236在圖2B 中被描述成在鎳包覆層23〇與鎳-釩層226之間有不同的分 界線，但是處理能夠在鎳包覆層230的殘餘處產生明顯接 -13- (11) 1313505 近純鎳之擴散梯度，並且在鎳-釩層226的殘餘處產生鎳- 釩區，包含處理時間和溫度之處理強度能夠改變擴散梯度 〇 在一實施例中，金-錫-鎳區236包含金和錫的比例從 約60 : 40到約80 : 20，在此實施例中，鎳的量係在從約1 PPm到約爲金-錫-鎳之總量的一半之範圍中。在一實施例 中，金和錫係在約70 : 30的比例，在此實施例中’鎳的量 φ 係在從約1 ppm到約爲金-錫-鎳之總量的一半之範圍中。 在金-錫-鎳區23 6中之金和錫的特定比例視開始條件及處 . 理條件而定。 . 在一實施例中，在晶片封裝組件20 1的組裝期間之處 理條件包含將散熱片214及其諸層230, 232,和23 4沿著其諸 層224，226,和230而壓進變薄的晶粒210中。處理也包含在 到達錫層234中之固相溫度（TsclidusSn)條件下的熱接合。當 到達Ts<jlidusSn並且超過時，錫開始熔化並且和不同層（包 φ 含金層232和金底層228)中的金形成共熔。除此之外，部 分的鎳也被拉引而變成在金-錫-鎳區23 6。 在一實施例中，一製程包含使晶粒210變薄，且使晶 粒210接合於散熱片214。在一實施例中，接著接合之後， 變薄的晶粒210展現出大於晶粒-特性 CTE的晶粒-有效 CTE。在此製程中，變薄的晶粒210包含一晶粒-TIM前驅 '物（precursor)，此晶粒-TIM前驅物包含置於變薄的晶粒 210上之鈦包覆層224、置於鈦包覆層224上之鎳-釩層226 、及置於鎳-釩層226上之金底層228。散熱片214包含一散 -14- (12) 1313505 熱片-TIM前驅物，此散熱片-TIM前驅物包含置於散熱片 214上的鎳包覆層230、置於該鎳包覆層230上的金層232、 及置於該金層232上的錫層234。在如同在此所提出的熱接 合之後，TIM 212包含在從約Ο.ίμηι到約50μιη之範圍中的 厚度。 依據一實施例，在接合之後，該製程形成一置於變薄 的晶粒210之上方且在變薄的晶粒210上的鈦區224、一置 φ 於鈦區224之上方且在鈦區224上的鎳-釩區226、該置於 鎳-釩區226之上方且在鎳-釩區226上的金-錫-鎳區236、及 . 一置於金-錫-鎳區236之上方且在金·錫·鎳區236上的鎳區 . 230，其最終係置於散熱片21 4上。 圖3爲依據實施例之晶片封裝組件300的剖面圖。多個 變薄的晶粒310被描述以TIM 312而被接合於散熱片314, 並且在變薄的晶粒310之主動表面處被接合於多個基板（例 如，有機內插板）。變薄的晶粒3 1 0經由一連串的電凸塊而 鲁 被耦接至基板316，電凸塊的其中一個係以參考數字318來 予以命名指定。 在一實施例中，變薄的晶粒310實質上爲相同的微電 子裝置，例如，由加州聖塔克羅拉（Santa Clara)之英特爾 (Intel)公司所製造的平行處理器。在一實施例中，變薄的 晶粒310爲互補的微電子裝置，例如，由英特爾（Intel)公 司所製造之晶片組的至少一部分。 '在一實施例中，變薄的晶粒310各自具有不同的厚度 ’不s命是不问厚度的相同厚度’或者是在此揭示中所提出 -15 - (13) 1313505 之任一實施例之厚度的相同厚度。在—實施例中，TIM 3 1 2的B LT爲具有在此揭示中所提出之任—實施例的厚度 ’和變薄的晶粒310厚度之任一者相結合。因此，依據一 實施例’根據幾個實施例之晶粒-有效CTE係比晶粒-特性 CTE還大至少兩倍。在一實施例中，晶粒-有效CTE係比 晶粒·特性C T E還大至少從約兩倍到約五倍。 圖4爲依據實施例之晶片封裝組件4 0 0的剖面圖。變薄 φ 的晶粒410被描述以TIM 412而被接合於散熱片414，散熱 片414也就是安裝基板416，例如，由金屬層疊之玻璃纖維 •所做的有機板。變薄的晶粒410之主動表面係經由一連串 -的打線接合418而被耦接至散熱片/基板41 4/4 16。散熱片 結構414’依據一實施例而被描述金屬疊層，此金屬疊層被 金屬集中（m e t a 1 - c ο n c e n t r a t e d )於變薄的晶粒4 1 0之下，並 且和散熱片/基板414/416集成在一起。在一實施例中，將 晶片封裝組件400應用於可攜式裝置，例如，手持式裝置 • 或筆記型電腦。 圖5爲依據實施例之製程流程圖500。 在5 10，製程包含在將晶圓切割成許多晶粒之前使晶 圓變薄，或者在晶粒已經從晶圓中碎裂出之後使晶粒變薄 。經由舉出非限制實例，依據在此所提出之變薄製程實施 例或其等同之物的任一者來使晶粒210變薄。 藉由包覆變薄的晶粒來繼續製程流程實施例於5 1 2。 經由舉出非限制實例，變薄的晶粒210(圖2)係包覆有一鈦 包覆層224。此外，此製程流程包含形成鎳-釩層226於鈦 -16 - (14) 1313505 包覆層224上，並且形成金底層228於鎳-釩層226上。在一 實施例中，此製程流程係結束於5 12。 在5 14，製程流程藉由使變薄的晶粒連結於散熱片而 繼續著。經由舉出非限制實例，藉由形成鎳包覆層230於 散熱片214上來製備散熱片214 (圖2A)。在一實施例中’ 形成鎳包覆層230於散熱片214上係藉由分開的商業團體 (business entity)來予以實施，並且不是本發明所主張之 φ 製程實施例的一部分。在任何情況下，金層23 2被形成於 鎳包覆層230上，並且錫層234被形成於金層232上。在一 .實施例中，此製程流程係結束於5 14。 .在520，製程包含使晶粒連結於基板。經由舉出非限 制實例，晶粒3 1 0係連結於基板3 1 6 (例如，內插板）。依據 此製程流程實施例，製程流程係結束於5 20。 在530，製程流程實施例包含在使晶圓變薄之前先將 晶圓切塊（dicing)。在一實施例中，製程流程以晶圓切塊 φ 而開始於53 0 ’接著製程於510，其包含使晶粒變薄。 圖6爲依據實施例之計算系統600的描述。計算系統 600包含變薄的晶粒（例如，變薄的晶粒11〇)以及TIm(例 如’ TIM 112)。同樣地，計算系統600包含散熱片（例如， 散熱片114)。在下文中，依據在此揭示中所提出之各種實 施例’當計算系統600指的是變薄的晶粒時，可以了解到 包含TIM及散熱片。在一計算系統6〇〇(例如，圖6之計算 系統600)中可以利用變薄的晶粒組態之前述實施例的一或 多者。同樣地，依據在此揭示中所提出之物件實施例的任 -17- (15) 1313505I (2) 1313505 becomes too high, which may damage or destroy the integrated circuit of the semiconductor die and the lifetime/reliability of the chip is significantly reduced. In addition, for semiconductor dies of the same size, the overall power is increased, which shows the same problem of the added power density. Various devices and techniques have been used to remove heat from semiconductor dies, some of which involve the use of encapsulation materials to encapsulate conductor dies on heat spreaders, or to embed semiconductor φ (fixed) ) in the recess (cavity) in the heat sink to dissipate heat. The use of this technique creates additional, complex processing steps used to fabricate integrated circuit package components' and the thermal performance of these assembly methods is also limited by the material • process. Therefore, it would be advantageous to develop new devices and techniques for integrated circuit fabrication. These new devices and techniques eliminate the need for complex processing steps and board interposers and provide improved heat dissipation. The coefficient of thermal expansion (CTE) of a material similar to a grain is also a problem. Destructive stress can occur between the plate and the die due to the inherent essential difference in material properties (Si with a CTE of 2·6 Ppm/C and with Ppm) /C CTE substrate) 'The thermal/mechanical stress problem is even more severe when the microelectronic device package assembly produces significant heat, which also limits the choice of low dielectric constant material required for performance devices. SUMMARY OF THE INVENTION The following description contains terms that are merely used for the purpose of description rather than the limitation of construction, such as the above, the first, the second, the second, and the like. Embodiments of the device or article herein can be used in a number of positions or directions to increase the size of the particles and the basis for the production of the device, the use, or the shipment. . The terms "grain" and "processor" generally refer to the actual object that is the basic workpiece, and the basic workpiece is transformed into the desired integrated circuit device by various process operations. The grains are often separated from the wafer and the wafer can be made of a semiconductor material, a non-semiconductor material, or a combination of semiconductor and non-semiconductor materials. Typically, the board is a conductor-covering structure that is insulated and serves as a mounting substrate for the dies, which are often separated from an array of boards. Reference is now made to φ, in which similar structures are provided with similar reference designations. To best illustrate this structure and process embodiment, a graphical representation of an embodiment of the graphics is included herein. Thus, the true appearance of the fabricated structure, for example, may vary in microfilming while still incorporating the necessary structure of the embodiment. Moreover, the figures only show the structure required to understand the present invention. The embodiments may be referred to individually and/or collectively, and the term "invention" is used merely for convenience, and it is not intended to limit the scope of the disclosure to any single invention or inventive concept, if in fact more than one The invention or invention mourning is revealed. Other structures known in the art are not included in order to maintain clarity of the graphics. In accordance with the disclosed embodiment, the formation of thinned semiconductor dies bonded to a planar heat sink, in combination with the substrate, produces many of the characteristics of the integrated circuit package assembly. One of the features of the embodiment that the heat sink can be planar (as opposed to an irregular, non-planar shape) makes it easier to manufacture. Another feature of the embodiment includes that the die is more easily bonded to the heat sink than the "die embedded in the heat sink" technique because precise control of the deposited material in the bottom of the void is necessary, and this pair Self-aligning -6- (4) 1313505 welding methods are particularly advantageous. Another feature of the embodiment is that as in the case of the art, it is not necessary to glue the die to the heat sink. Another feature is that the thinned die having bumps before the Si die is bonded to the organic substrate is bonded to the Cu heat sink. Another feature involves the use of thin brazed thinned Si grains with a higher remelting temperature and a Cu heat sink. In addition, the thinned grains reduce the die/heat sink combination φ ' to improve heat removal from the die. The thinned grains are also more compliant and the thermal/mechanical properties of the heat sink are uniformly expanded and contracted, thus reducing: stress induced cracking at the interface between the grains and the Cu heat sink. The strong coupling of the Cu heat sink to increase the effective CTE of Si, and the stress between the organic substrate and the organic substrate is also significantly reduced. Although the drawings illustrate various embodiments, these figures do not depict the integrated circuit (microelectronic) package components in detail, but rather illustrate the examples to more clearly convey the illustrated embodiments and their equivalents. Body circuit package assembly. In addition to this, the same components in these figures can retain the same numerical naming designation. Embodiments include a packaging technique in which one or more thinned body (microelectronic) grains are placed on a planar heat sink'. The semiconductor die is fixed by a hard adhesive thermal interface material. Shadow. In one embodiment, the dies may be bonded to the heat sink by the use of an adhesive material (e.g., a "material". Alternatively, an alternative method of forming a bond between the heat sinks may be used. These embodiments result in the integrated circuit package assembly being able to be constructed in conjunction with other embodiments to provide an embodiment agent to thermally resist it and less in the Si with the Si die. Semi-conducting and by means of hot-rolled solder particles and dispersion: in the vicinity of thinned -7-(5) 1313505 semiconductor grains. According to an embodiment, this configuration also results in a thinner form factor when the die size is very thin and the package assembly requires a smaller heat sink. 1 is a cross-sectional view of a wafer package assembly 100 in accordance with an embodiment. It is described that before the front side (active surface) of the thinned die 110 is bonded to the substrate 116 (eg, 'organic interposer), the thinned die 110 is bonded to the heat by a thermal interface material (TIM) 112. Slice 114. The interconnect structure 117 is coupled to the substrate 116 via a series of electrical bumps on the front side of the thinned φ die 110. One of the electrical bumps is designated by reference numeral 118. In one embodiment, the thinned die 110 has a thickness 120 ranging from about 20 microns (μπ〇 to about 150 μηη. In one embodiment, the thinned die 1 10 has a range from about 80 μηι to about The thickness 120 of 120 μηη. In one embodiment, the 'thinned die 1 10 has a thickness 120 ranging from about ΙΟΟμπι. In one embodiment, the thinned die 110 has a thickness of no more than about 1 μm. In one embodiment, the thinned die 110 has a thickness 120 of less than about 。μηη. In one embodiment, the TIM 112 has a interface thickness (BLT) 122 ranging from about Ο.ίμιη to about 50 μηη. In an embodiment, TIM 112 has a BLT 122 ranging from about 〇5 μm to about 40 μm. In one embodiment, TIM 1 12 has a BLT 122 ranging from about Ιμπι to about 30 μπι. In a real " The TIM 112 has a BLT 122 ' ranging from about 2 μηι to about 20 μπι. In one embodiment, the TIM 112 has a BLT 122 ranging from about 5 μπι to about 。 μιη. In one embodiment, the TIM 112 has a BLT 122 1313505 of about 6 μm. (6) Figure 1 also illustrates various The embodiment, used to fabricate the heat sink 114 of the integrated circuit package assembly 100, the heat sink 114 includes a substantially planar (flat), highly thermally conductive material to remove heat dissipated in the thinned die 110. In the example, the material used to fabricate the heat sink 114 comprises a metal such as copper, a copper alloy containing a copper alloy of tungsten, a copper laminate, a copper diamond, a coated copper structure, combinations thereof, and the like. Etc. In one embodiment, the material used to fabricate the heat sink 114 comprises a molybdenum, a molybdenum laminate, a molybdenum alloy, a coated molybdenum structure, combinations thereof, and the like. In one embodiment, it is used to make The material of the heat sink 114 comprises aluminum, a metal alloy containing a nitrided alloy, an aluminum diamond, a coated aluminum structure, a combination thereof, etc. The aluminum nitride can be made of chromium/gold, titanium/gold, Or a nickel/gold film for metallization. In one embodiment, the material used to fabricate the heat sink 114 comprises yttria, etc. In one embodiment, • the material used to make the heat sink 114 comprises carbon fiber, Graphite, gold Stone, combinations thereof, etc. In one embodiment, the materials used to fabricate the fins 11 4 include, but are not limited to, thermally conductive ceramic materials, such as AlSiC, A1N, etc. Thermal expansion of the material selected for the fins 114 The coefficient (CTE) is used to minimize stress-induced cracking in the thinned die 110, particularly at the edges of the die 112 at the interconnects 117 in the die and bumps 118. For example, 'by closely matching the CTE of the fin 114 material (e.g., AlSiC) to 矽, the event of stress induced grain rupture can be reduced. For example, by -9-(7) 1313505, the stress between the interconnect 117 and the electrical bumps 118 can be reduced by matching the CTE of the fin material 114 to the organic interposer 116 (e.g., Cu). In the embodiment for the thinned die 110, the fins II4 are made of a material (e.g., copper) that is mismatched to the larger CTE of the crucible but does not cause stress induced grain breakage. Again, the heat sink 114 can be made of a material having a CTE that closely matches the substrate 116, and the thinned die 110 can be placed on the substrate 116 for operation (eg, a central processing unit (CPU) of a computer) . The thinness of the thinned die 110 is such that it is consistent with the thermally induced dimensional change of the heat sink 114. In one embodiment, the thinned die 110 is part of a package assembly 100 that forms an article that includes a heat sink 114, and the heat sink 114 includes a heat sink-characteristic CTE that is based on its material and configuration. The thinned die 110 contains a grain-characteristic CTE. The TIM 112 bonds the thinned die 110 to the heat sink and constitutes one embodiment of the article without the substrate 116. Because of the thickness of the thinned grains 11 提出 as set forth in this disclosure, the thinned grains 11 0 contain a grain-effective CTE greater than the grain-characteristic CTE. In other words, the die-effective CTE is substantially matched to the heat sink-characteristic CTE. In one embodiment, the article that is part of the package assembly 100 contains a die-effective CTE that is about 5 times greater than the die-characteristic CTE. In one embodiment, the correct die-effective CTE is substantially matched to the heat sink-characteristic C T E . In one embodiment, the grain-effective C T E is in the range of from about 10 ppm/°C to about 17 ppm/°C. In one embodiment, the grain-effective CTE is about 16.2 ppm/°C. -10- (8) 1313505 FIG. 2A is a cross-sectional view of the wafer package assembly 200 during processing, in accordance with an embodiment. Wafer package assembly 200 represents an intermediate structure during assembly. The thinned die 210, which includes the thinness embodiments set forth in this disclosure, is described as being assembled to the heat sink 214 by thermal interface materials (TIMs) 211. Prior to the die 210 being bonded to the heat sink 214, the die 210 is thinned in accordance with an embodiment. According to one embodiment, the thickness of the die 210 is reduced in accordance with one or more of various techniques such as honing, chemical mechanical polishing, plasma etching, or other techniques. In one embodiment, chemical etching is used to reduce the thickness of the die 210. In one embodiment, honing is used to reduce the thickness of the die 210. In one embodiment, any two of the above techniques are used to reduce the thickness of the die 210. In one embodiment, any three of the above techniques are used to reduce the thickness of the die 210. In one embodiment, all of the above techniques are used to reduce the thickness of the die 210. In one embodiment, the heat sink 2 14 is substantially copper. In an embodiment φ, the TIMs 211 include a nickel cladding layer 23 on the heat sink 214, a gold layer 232 disposed on the nickel cladding layer 230, and a gold layer 232 disposed on the gold layer 232. Tin layer 2〗 4. In one embodiment, the TIMs 21 1 includes a titanium cladding layer 224 disposed on the thinned die 210, a nickel-vanadium layer 226 disposed on the titanium cladding layer 224, and a nickel-vanadium layer. Gold sublayer 228 on layer 226. The choice of layer thickness includes consideration of the final BLT associated with the BLT 122 depicted in FIG. In one embodiment, the heat sink 214 is substantially copper. In the embodiment, the nickel clad layer 230 is in a thickness ranging from about 〇·〇5 μm to about 66 μm. In one embodiment, the nickel cladding layer 230 is in a thickness ranging from about -11 - (9) 1313505 to about 〇 45 μm. In one embodiment, the nickel cladding layer 230 is about 0. 3 μm. In one embodiment, the gold layer 232 is in a thickness ranging from about 〇5 μm to about 6 μm. In an embodiment, the gold layer 232 is in a thickness ranging from about 1 to 111 to about 4,111. In one embodiment, the gold layer 232 is about 3 μm. In one embodiment, the tin layer 234 is in a thickness ranging from about 〇.5 μm to about 66 μηι. In one embodiment, the tin layer 23 4 is in a thickness ranging from about ί.ίμηι to about 〇15 μιη. In one embodiment, the tin layer 234 is about 〇.3μιη. In one embodiment, the titanium cladding layer 224 is in a thickness ranging from about 〇·〇5 μm to about 0. 2 μm. In one embodiment, the titanium cladding layer 224 is in a thickness ranging from about 0.075 μηη to about 0.15 μηη. In one embodiment, the titanium cladding layer 224 is about 0.1 μm. In one embodiment, the nickel-vanadium layer 226 is in a thickness ranging from about 0.05 μm to about 〇6 μm. In one embodiment, the nickel-vanadium layer 226 is in a thickness ranging from about 0.1 μηη to about 0.15 μηη. In one embodiment, the nickel-vanadium layer 22 6 is about 0.3 μηη. In one embodiment, the gold base layer 228 is in a thickness ranging from about 0.05 μm to about 0.2 μm. In one embodiment, the gold base layer 228 is in a thickness ranging from about 0.075 μηη to about 0.15 μηη. In one embodiment, the gold underlayer 228 is about Ο.ίμιη. In one embodiment, the heat sink 214 is substantially copper, the nickel cladding layer 230 is about 3 μm, the gold layer 232 is about 3 μm, the tin layer 234 is about 3 μm, and the titanium cladding layer 224 is about Ο. ίμηι, nickel- The vanadium layer 226 is about 〇·3 μm, and the gold underlayer 228 is about 0.1 μm. 2 is a cross-sectional detailed view of the wafer package assembly 200 depicted in FIG. 2A during further processing in accordance with an embodiment, the cross-sectional detail drawing taken from -12-1313505 no) from the selection line 2B in FIG. 2A, and has been The wafer package assembly 200 of Figure 2A is brought together. Wafer package assembly 201 is depicted as an article comprising bonded TIM 212, and FIG. 2 illustrates a single thinned die 210 bonded (mounted) to heat sink 214 with an adhesive (TIM) 212. In one embodiment, a hot press (e.g., a thermocompression bonding machine, a reflow oven) is used to join the thinned pellets 210 to the fins 214. With several TIM embodiments, a fluxless bonding procedure was implemented. For example, the fluxless bonding process is performed with a copper heat sink 214 and a substantially thinned die 210, the thinned die 210 is about 50 μm thick, and when the bonding is completed, the TIM 212 It is about 6 μm. In the fluxless bonding process, the titanium cladding layer 224 is about Ο.ΐμπι, the nickel-vanadium layer 226 is about 0.3 μm, and the gold underlayer 228 is about Ο.ίμιη. In addition, in the fluxless bonding process, the nickel cladding layer 230 is about 3 μm, the gold layer 232 is about 3 μm, and the tin layer 234 is about 3 μm. Bonding is performed by melting the tin layer 234 at its solid phase temperature (TSQlidusSn) and further heating. In one embodiment, the bonding is performed by an instant wafer bonding process, such as φ titanium and/or chrome and ruthenium, which is generally known to those skilled in the art, but the bonding process is applied as a thinning for this disclosure. Part of the grain processing embodiment. The TIM 212 allows heat to be transferred from the thinned die 210 to the heat sink 214 by conduction. In one embodiment, the TIM 21 2 includes a gold-tin-nickel region 236 which is formed by a fused portion of a nickel cladding layer 203, a gold layer 23, a tin layer 23 4, a nickel-vanadium layer 226, and Gold bottom layer 228. Although the gold-tin-nickel region 236 is depicted in FIG. 2B as having a different boundary between the nickel cladding layer 23 and the nickel-vanadium layer 226, the treatment can be apparent at the residue of the nickel cladding layer 230. a diffusion gradient of -13 (11) 1313505 near pure nickel, and a nickel-vanadium region is produced at the residue of the nickel-vanadium layer 226, the treatment intensity including processing time and temperature can change the diffusion gradient, in one embodiment, The gold-tin-nickel region 236 comprises a ratio of gold to tin of from about 60:40 to about 80:20. In this embodiment, the amount of nickel is from about 1 ppm to about the total amount of gold-tin-nickel. Half of the range. In one embodiment, the gold and tin are in a ratio of about 70:30, and in this embodiment the amount of nickel is in the range of from about 1 ppm to about half of the total amount of gold-tin-nickel. . The specific ratio of gold and tin in the gold-tin-nickel zone 23 6 depends on the starting conditions and conditions. In one embodiment, the processing conditions during assembly of the wafer package assembly 20 1 include pressing the heat sink 214 and its layers 230, 232, and 234 along its layers 224, 226, and 230. Thin in the die 210. The treatment also includes thermal bonding under solid phase temperature (TsclidusSn) conditions in the tin layer 234. When Ts < jlidusSn is reached and is exceeded, the tin begins to melt and forms a eutectic with the gold in the different layers (including the gold-containing layer 232 and the gold-based layer 228). In addition to this, part of the nickel is also pulled into the gold-tin-nickel zone. In one embodiment, a process includes thinning the die 210 and bonding the die 210 to the heat sink 214. In one embodiment, after bonding, the thinned die 210 exhibits a grain-effective CTE that is greater than the grain-characteristic CTE. In this process, the thinned die 210 comprises a grain-TIM precursor, the grain-TIM precursor comprising a titanium cladding 224 disposed on the thinned die 210, placed A nickel-vanadium layer 226 on the titanium cladding layer 224 and a gold underlayer 228 disposed on the nickel-vanadium layer 226. The heat sink 214 includes a dispersion of -14" (12) 1313505 hot sheet-TIM precursor, and the heat sink-TIM precursor comprises a nickel coating layer 230 disposed on the heat sink 214, and is disposed on the nickel cladding layer 230. The gold layer 232 and the tin layer 234 disposed on the gold layer 232. The TIM 212 is included in a thickness ranging from about Ο.ίμηι to about 50 μm after thermal bonding as proposed herein. According to an embodiment, after bonding, the process forms a titanium region 224 over the thinned die 210 and on the thinned die 210, a φ above the titanium region 224 and in the titanium region. a nickel-vanadium region 226 on 224, a gold-tin-nickel region 236 disposed above the nickel-vanadium region 226 and on the nickel-vanadium region 226, and a gold/tin-nickel region 236 And in the nickel tin zone 230 on the gold tin tin zone 236, it is finally placed on the heat sink 21 4 . 3 is a cross-sectional view of a wafer package assembly 300 in accordance with an embodiment. A plurality of thinned dies 310 are described as being bonded to the heat sink 314 with the TIM 312 and bonded to a plurality of substrates (e.g., organic interposer) at the active surface of the thinned die 310. The thinned die 310 is coupled to the substrate 316 via a series of electrical bumps, one of which is designated by reference numeral 318. In one embodiment, the thinned die 310 is substantially the same microelectronic device, such as a parallel processor manufactured by Intel Corporation of Santa Clara, California. In one embodiment, the thinned die 310 is a complementary microelectronic device, such as at least a portion of a wafer set manufactured by Intel Corporation. In one embodiment, the thinned grains 310 each have a different thickness 'the same thickness regardless of the thickness' or any of the embodiments of -15 - (13) 1313505 proposed in this disclosure The same thickness of thickness. In an embodiment, the B LT of TIM 3 1 2 is combined with any of the thicknesses of any of the embodiments set forth in this disclosure and the thickness of the thinned die 310. Thus, the die-effective CTE system according to several embodiments according to an embodiment is at least twice as large as the grain-characteristic CTE. In one embodiment, the grain-effective CTE system is at least about two times to about five times greater than the grain size characteristic C T E . 4 is a cross-sectional view of a wafer package assembly 400 in accordance with an embodiment. The thinned φ die 410 is described as being bonded to the heat sink 414 by the TIM 412, which is the mounting substrate 416, for example, an organic plate made of metal laminated glass fibers. The active surface of the thinned die 410 is coupled to the heat sink/substrate 41 4/4 16 via a series of wire bonds 418. The heat sink structure 414' is described in accordance with an embodiment of a metal stack that is metal-concentrated below the thinned die 410 and with the heat sink/substrate 414 /416 is integrated. In one embodiment, the wafer package assembly 400 is applied to a portable device, such as a handheld device or a notebook computer. FIG. 5 is a process flow diagram 500 in accordance with an embodiment. At 5 10, the process involves thinning the wafer before cutting the wafer into a plurality of grains, or thinning the grains after the grains have been chipped from the wafer. The die 210 is thinned by any of the thinner process embodiments or equivalents thereof as set forth herein, by way of non-limiting example. The process flow embodiment is continued at 51 1 2 by coating the thinned grains. By way of a non-limiting example, the thinned die 210 (Fig. 2) is coated with a titanium cladding layer 224. In addition, the process flow includes forming a nickel-vanadium layer 226 on the titanium-16-(14) 1313505 cladding layer 224 and forming a gold underlayer 228 on the nickel-vanadium layer 226. In one embodiment, the process flow ends at 5 12 . At 5, the process flow continues by joining the thinned die to the heat sink. Heat sink 214 (Fig. 2A) is prepared by forming a nickel cladding layer 230 over heat sink 214, by way of non-limiting example. In one embodiment, the formation of the nickel cladding layer 230 on the heat sink 214 is performed by a separate business entity and is not part of the φ process embodiment claimed by the present invention. In any case, a gold layer 23 2 is formed on the nickel cladding layer 230, and a tin layer 234 is formed on the gold layer 232. In an embodiment, the process flow ends at 514. At 520, the process includes bonding the die to the substrate. By way of a non-limiting example, the die 310 is attached to a substrate 3 16 (e.g., an interposer). According to this process flow embodiment, the process flow ends at 5 20 . At 530, the process flow embodiment includes dicing the wafer prior to thinning the wafer. In one embodiment, the process flow begins with wafer dicing φ at 53 0 ' and then at 510, which includes thinning the grains. FIG. 6 is a depiction of computing system 600 in accordance with an embodiment. Computing system 600 includes thinned grains (e.g., thinned grains 11A) and TIm (e.g., 'TIM 112). As such, computing system 600 includes a heat sink (eg, heat sink 114). In the following, according to various embodiments presented in the disclosure, when the computing system 600 refers to a thinned die, it is understood that the TIM and the heat sink are included. One or more of the foregoing embodiments of the thinned die configuration may be utilized in a computing system 6 (e.g., computing system 600 of FIG. 6). Similarly, any of the object embodiments proposed in the disclosure herein is -17-(15) 1313505
何一者，此計算系統可以包含晶粒、金-錫TIM 在一實施例中，計算系統6 0 0，舉例來說， 在封裝組件610中之至少一處理器（未圖示出）、 系統6 1 2、至少一輸入裝置（例如，鍵盤6 1 4 )、及 出裝置（例如，監視器）。此計算系統6 0 0包含一 訊號之處理器，並且可以，舉例來說，包含一可 φ 爾（Intel)公司之微處理器。除了鍵盤614之外， 600可以包含另一使用者輸入裝置，舉例來說， -鼠 6 1 8。 - 對此揭示來說，依據本發明所主張之標的物 具體化之計算系統600可以包含任何利用變薄的 例之系統’該系統可以被耦接至安裝基板620。 數位訊號處理器（DSP)、微控制器、特殊應用 (ASIC)、或微處理器的晶粒而言，此變薄的晶粒 • 可以被稱接至安裝基板620。 對此揭示來說，依據本發明所主張之標的物 具體化之計算系統600可以包含任何利用微電子 之系統’該系統可以包含，舉例來說，一變薄的 ，該組態被耦接至資料儲存裝置，例如，動態隨 億體（DRAM)、聚合物記憶體（p〇iymer memory) _ 憶體、及相變記憶體。在此實施例中，變薄的晶 由被耦接至輸入-輸出裝置而被被耦接至這些機 組合。但是’在一實施例中，在此揭示中所提出 、和散熱 包含被封 資料儲存 至少一輸 處理資料 獲自英特 計算系統 例如，滑 來使組件 晶粒實施 對於含有 積體電路 實施例也 來使組件 裝置系統 晶粒組態 機存取記 、快閃記 粒組態藉 能的任何 之變薄的 -18 - (16) (16)1313505 晶粒組態被耦接至這些機能的任何一者。對於一實例實施 例而言，資料儲存裝置包含在變薄的晶粒上之嵌入式 DRAM快取記憶體。除此之外，在一實施例中，變薄的晶 粒組態爲具有耦接至dram快取記憶體之資料儲存裝置 之變薄的晶粒組態之系統的一部分。除此之外，在一實施 例中，變薄的晶粒組態係耦接至資料儲存裝置6 1 2 » 在一實施例中，計算系統6 0 0能夠包含一變薄的晶粒 ，而此變薄的晶粒含有數位訊號處理器（DSP)、微控制器 、特殊應用積體電路（ASIC)、或微處理器。在此實施例中 ，變薄的晶粒組態係藉由被耦接至主機板等等而爲這些機 能的任何一者。對於一實例實施例而言，D S P (未圖示出） 爲一晶片組的一部分，而此晶片組可以包含一直立式變薄 晶粒處理器（在封裝組件6 1 〇中）及該DSP做爲該晶片組的 分開部件。在此實施例中，變薄的晶粒組態爲DSP封裝 組件的一部分，並且分開之變薄的晶粒組態可以呈現爲處 理器封裝組件6 1 0的一部分。除此之外，在一實施例中， 變薄的晶粒組態係耦接至被安裝在相同的板6 2 0上做爲封 裝組件610之DSP。 現在可以領會到，在此揭示中所提出之實施例能夠被 應用在傳統電腦以外的裝置及設備上。舉例來說，晶粒可 以和變薄的晶粒組態之實施例一起被封裝，並且被置於可 攜式裝置（例如，無線通訊器）或手持式裝置（例如，個人 資料助理）等等中。·另一實例爲一能夠被封裝做爲一實施 例且被置於載具（例如，汽車、火車 '船、飛機、或太空 -19- (17) 1313505 船）中之變薄的晶粒。 提供揭示之摘要部分以符合37(：1.11.§1.72(1))’其要 求將可以讓讀者能夠快速地弄清技術揭示之本質和主旨的 揭示之摘要部分。可了解到揭示之摘要部分不被用來解釋 或限制申請專利範圍之範疇或意義。 在前面的實施方式部分中，爲了揭示之流暢而將各種 特徵以單一實施例而被分組在一起。此種揭示方法並不被 φ 解釋爲反映出本發明之所主張的實施例需要比在各申請專 利範圍中所表達詳述者還多的特徵之意圖。反而是，當下 -面的申請專利範圍反映時，本發明之標的物處於少於單一 -揭示之實施例的所有特徵之情況。因此，下面的申請專利 範圍在此被倂入於實施方式部分中，連同各申請專利範圍 單獨做爲個別的較佳實施例。 習於此技藝者將可很輕易地了解到在詳細內容、材料 、及部件和方法階段的配置上之各種其他的改變（其已經 • 被敘述及例舉以便解釋本發明之本質）可以被做成，而沒 有違離本發明的精神及範疇，如同由所附加之申請專利範 圍所表述的。 【圖式簡單說明】 爲了了解取得實施例之方式，將藉由參照附加之圖形 來做出槪略敘述於上面之各種實施例的更特別說明，這些 圖形描述不需要按照實際大小來予以畫出，並且不被認爲 是限定範圍之實施例。有些實施例將經由使用伴隨之圖形 -20 - (18) 1313505 ，而以額外的具體性及詳細內容來做說明和解釋，在這些 圖形中： 圖1係依據實施例，晶片封裝組件的剖面圖； 圖2A係依據實施例，在處理期間，晶片封裝組件的 剖面圖； 圖2B係依據實施例，在進一步處理期間，圖2A所描 述之晶片封裝組件的剖面詳細圖； 圖3係依據實施例，晶片封裝組件的剖面圖； 圖4係依據實施例，晶片封裝組件的剖面圖； 圖5係依據實施例之製程流程圖；以及 圖6係依據實施例，計算系統之描述。 【主要元件符號說明】 1 0 0 ·晶片封裝組件 110 :變薄的晶粒 112 :熱介面材料（TIM) 114 :散熱片 11 6 :基板 11 7 :互連結構 11 8 :電凸塊 120 :厚度 122 :介面厚度（BLT) 200 :晶片封裝組件 2 1 0 :變薄的晶粒 -21 - (19) 1313505 211 :熱介面材料（TIM) 2 1 4 :散熱片 2 2 4 :鈦包覆層 2 2 6 :鎳-釩層 228 :金底層 23 0 :也包覆層 2 3 2 :層 • 2 3 4 :鶬層 212 :熱介面材料（TIM) 2 3 6 .金-錫-鏡區 . 201 :晶片封裝組件 300 :晶片封裝組件 310:變薄的晶粒 312 :熱介面材料（TIM) 314 :散熱片 φ 3 1 6 :基板 318 :電凸塊 400 :晶片封裝組件 4 1 0 :變薄的晶粒 412:熱介面材料（TIM) 414 :散熱片 4 1 6 :基板 4 1 8 :打線接合 414’ ：散熱片結構 1313505 (20) 600 :計算系統 6 1 0 :變薄的晶粒（封裝組件） 6 1 2 :資料儲存系統 6 1 4 :鍵盤 6 1 6 :監視器 6 1 8 :滑鼠 620 :安裝基板（板）In one embodiment, the computing system can include a die, a gold-tin TIM. In one embodiment, the computing system 600, for example, at least one processor (not shown), system in the package component 610 6 1 2. At least one input device (for example, keyboard 6 1 4), and an outgoing device (for example, a monitor). The computing system 600 includes a processor for the signal and can, for example, comprise a microprocessor from Intel Corporation. In addition to the keyboard 614, the 600 can include another user input device, for example, - mouse 6 18 . For purposes of this disclosure, the computing system 600 embodied in accordance with the subject matter of the present invention can include any system that utilizes thinning. The system can be coupled to a mounting substrate 620. In the case of a digital signal processor (DSP), a microcontroller, an application specific (ASIC), or a microprocessor die, the thinned die can be referred to as a mounting substrate 620. In this disclosure, the computing system 600 embodied in accordance with the subject matter of the present invention can include any system that utilizes microelectronics. The system can include, for example, a thinner configuration coupled to Data storage devices, for example, dynamic DRAM, polymer memory, memory, and phase change memory. In this embodiment, the thinned crystals are coupled to the input-output devices and coupled to the combination of these machines. However, in an embodiment, the heat dissipation and the heat dissipation including the sealed data are stored in at least one of the processing data obtained from the Intel computing system, for example, sliding to enable the component die to be implemented for the integrated circuit embodiment. To make the component device system configurator access, flash granule configuration, any thinning -18 - (16) (16) 1313505 die configuration is coupled to any of these functions By. For an example embodiment, the data storage device includes embedded DRAM cache memory on thinned dies. In addition, in one embodiment, the thinned crystal grain is configured as part of a system having a thinned die configuration coupled to a data storage device of a dram cache memory. In addition, in one embodiment, the thinned die configuration is coupled to the data storage device 6 1 2 » In one embodiment, the computing system 600 can include a thinned die, and The thinned die contains a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor. In this embodiment, the thinned die configuration is any of these functions by being coupled to a motherboard or the like. For an example embodiment, the DSP (not shown) is part of a chipset that can include an upright thinned die processor (in package component 61) and the DSP It is a separate component of the wafer set. In this embodiment, the thinned die configuration is part of the DSP package assembly and the separate thinned die configuration can be presented as part of the processor package assembly 61. In addition, in one embodiment, the thinned die configuration is coupled to a DSP that is mounted on the same board 620 as package assembly 610. It will now be appreciated that the embodiments presented in this disclosure can be applied to devices and devices other than conventional computers. For example, the die can be packaged with an embodiment of a thinned die configuration and placed in a portable device (eg, a wireless communicator) or a handheld device (eg, a personal data assistant), etc. in. Another example is a thinned die that can be packaged as an embodiment and placed in a carrier (e.g., a car, train 'ship, airplane, or space -19-(17) 1313505 ship). The abstract portion of the disclosure is provided to comply with 37 (: 1.11. § 1.72(1))' and its requirements will enable the reader to quickly ascertain the abstract portion of the disclosure of the nature and subject matter of the technical disclosure. It is understood that the abstract of the disclosure is not to be construed as limiting or limiting the scope or meaning of the scope of the patent application. In the foregoing embodiments, various features are grouped together in a single embodiment for the sake of clarity. This method of disclosure is not to be interpreted as being inferred that the claimed embodiments of the present invention are intended to require more features than those described in the claims. Instead, the subject matter of the present invention is less than all of the features of the single disclosed embodiment when the scope of the invention is reflected. Therefore, the scope of the following patent application is hereby incorporated by reference in its entirety in its entirety in its entirety in the the the the the the Various other changes in the details, materials, and configurations of the components and method stages (which have been described and exemplified to explain the nature of the invention) can be readily made by those skilled in the art. This is done without departing from the spirit and scope of the invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to understand the manner in which the embodiments are obtained, a more particular description of the various embodiments above will be made by referring to the appended figures, which are not necessarily drawn to the actual size. It is not considered to be a limited embodiment. Some embodiments will be illustrated and explained with additional specificity and detail by using the accompanying figures -20 - (18) 1313505, in which: Figure 1 is a cross-sectional view of a wafer package assembly in accordance with an embodiment. 2A is a cross-sectional view of a wafer package assembly during processing, in accordance with an embodiment; FIG. 2B is a cross-sectional detailed view of the wafer package assembly depicted in FIG. 2A during further processing, in accordance with an embodiment; FIG. 3 is in accordance with an embodiment. FIG. 4 is a cross-sectional view of a wafer package assembly in accordance with an embodiment; FIG. 5 is a process flow diagram in accordance with an embodiment; and FIG. 6 is a description of a computing system in accordance with an embodiment. [Main component symbol description] 1 0 0 · Chip package assembly 110: Thinned die 112: Thermal interface material (TIM) 114: Heat sink 11 6 : Substrate 11 7 : Interconnect structure 11 8 : Electrical bump 120 : Thickness 122: interface thickness (BLT) 200: chip package assembly 2 1 0 : thinned die 21 - (19) 1313505 211: thermal interface material (TIM) 2 1 4 : heat sink 2 2 4 : titanium coated Layer 2 2 6 : Nickel-vanadium layer 228 : Gold underlayer 23 0 : Also cladding layer 2 3 2 : Layer • 2 3 4 : Tantalum layer 212 : Thermal interface material (TIM) 2 3 6 . Gold-tin-mirror region 201: chip package assembly 300: chip package assembly 310: thinned die 312: thermal interface material (TIM) 314: heat sink φ 3 1 6 : substrate 318: electrical bump 400: chip package assembly 4 1 0 : Thinned die 412: Thermal interface material (TIM) 414: Heat sink 4 1 6 : Substrate 4 1 8 : Wire bond 414': Heat sink structure 1313505 (20) 600: Computation system 6 1 0: Thinned crystal Grain (packaging kit) 6 1 2 : Data storage system 6 1 4 : Keyboard 6 1 6 : Monitor 6 1 8 : Mouse 620 : Mounting substrate (board)